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In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to investigate the impact of NSH channel thickness (tSi) ranging from 15 nm to 2 nm on device performance and reliability. Thinning tSi from 15 nm to 10 nm resulted in improved control of channel potential by the gate voltage, leading to a decreased threshold voltage (VTH) and subthreshold swing (SS). However, further reduction of tSi to 5 nm, while continuing to decrease SS, caused an increase in VTH due to the grain size reduction and quantum confinement (QC) effects. Lastly, reducing tSi to 2 nm resulted in an increase in both SS and VTH mainly due to the QC effect. In terms of reliability, under a fixed positive gate bias stress condition, thinning tSi enhanced the electric field stress, leading to more severe device damage. However, due to the enhanced ability of gate voltage control over the channel potential and the buried channel effect on electron transport resulting from thinning the channel thickness, there exists an optimal range between 10 nm and 5 nm for the selection of tSi in terms of the degradation of VTH, SS, and on-state current. Consequently, it is evident that for transistors utilizing NSH channels, the selection of tSi is not a case of “the thinner, the better.” This finding highlights the need to consider the optimal tSi range between 10 nm and 5 nm, balancing the performance and reliability aspects of the device design. [ABSTRACT FROM AUTHOR]

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (${G}_{m\_{}{\text {max}}}$) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (${V}_{\text {BG}}$) operation mode, the ${V}_{\text {BG}}$ can provide a wide threshold voltage (${V}_{\text {TH}}$) tuning range ~2 V when the ${V}_{\text {BG}}$ is modulated from 0 to −4 V. The negative ${V}_{\text {BG}}$ bias stress would induce electron injection from the BG, resulting in positive ${V}_{\text {TH}}$ shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative ${V}_{\text {BG}}$ stress, using ${V}_{\text {BG}}$ to modulate the ${V}_{\text {TH}}$ of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent ${V}_{\text {BG}}$ to adjust the ${V}_{\text {TH}}$ of the JL-TFTs to meet the multiple- ${V}_{\text {TH}}$ requirement of advanced integrated circuits. [ABSTRACT FROM AUTHOR]

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage ($V_{\text {TH}}$) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to −0.82 V, respectively. The degradation of on-state current is also improved significantly from −87% to −40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step $V_{\text {TH}}$ shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C. [ABSTRACT FROM AUTHOR]

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ($V_{\mathrm {TH}}$) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ($I_{\mathrm {ON}}$) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$. The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT. [ABSTRACT FROM AUTHOR]

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing (SS) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS. Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor. [ABSTRACT FROM AUTHOR]

We demonstrate the polycrystalline-silicon (poly-Si) junctionless (JL) thin-film transistor (TFT) with a planar structure and an ultra-thin channel film thickness ~1.5-nm exhibiting subthreshold swing (S.S.) less than 60 mV/decade. The S.S. of the poly-Si JL-TFT shows abnormal drain-voltage dependence, which the higher drain voltage leads to the smaller S.S. The minimum S.S. (S.S.min) observed in this letter is about 30 mV/decade, which is a record low S.S.min. The sub-60-mV/decade S.S. of the poly-Si JL-TFT is attributed to the impact ionization effect resulting from the high lateral electric field at the drain side at OFF-state. It is different from the conventional inversion-mode transistor, whose pinch-off point is observed at ON-state rather than the OFF-state. The lateral electric field is also found to be increasing with decreasing the channel thickness, and as a consequence, the impact ionization effect is more pronounced when the channel thickness is thinner. This letter shows a new concept for JL transistors, which would be helpful for the development of poly-Si JL-TFTs and the applications of 3-D integrated circuit and non-volatile memory. [ABSTRACT FROM AUTHOR]

The drain lapping effect of tunneling FETs (TFETs) with polycrystalline-silicon (poly-Si) channel film is well investigated for the first time. The carrier transport mechanisms of poly-Si TFETs can be divided into several transport mechanisms due to the device structure of source to drain. The interband tunneling at source/channel junction, carrier drift in the channel region, and drain-to-gate underlap region are elemental carrier transport mechanisms of TFETs with single-crystalline channel material. The poly-Si channel has many grain boundary trap states among bandgap due to the grain boundary defects, resulting in strong recombination effect in the drain-to-gate underlap region of poly-Si TFETs. The recombination rate of the underlap region would be significantly enhanced with the increased temperature and lead to obvious ON-state current ( I \mathrm{ ON} ) degradation. Therefore, the I \mathrm{ ON} behavior of the drain lapping effect is sensitive to the temperature and underlap length. In addition, the poly-Si TFETs with drain-to-gate overlap structure exhibit less temperature dependence and drain-to-gate overlap length dependence of the I \mathrm{ ON} to exhibit stable electrical behavior. Consequently, the drain lapping structure of poly-Si TFETs would trade the suppression of ambipolar behavior of poly-Si TFETs by the drain-to-gate underlap structure off against the I \mathrm{ ON} instability of temperature and device dimension. [ABSTRACT FROM AUTHOR]

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states ( N\mathrm {{it}} ) near the conduction band edge. The ON-state current ( I\mathrm{\scriptscriptstyle ON} ) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N2 plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N\mathrm {it} obviously, which greatly enhances the surface potential modulation by the gate and improves the I\mathrm{\scriptscriptstyle ON} value of poly-Si TFETs \sim 3.7\times . The OFF-state current ( I_{\mathrm { {min}}} ) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of \sim 40 %, because of the passivation of grain boundary trap ( N\mathrm {trap} ) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42\times 10^{5} to 6.13\times 10^6 . In addition, the subthreshold swing, $I_{{\mathrm{\scriptscriptstyle ON}}}$ , and I_{\mathrm { {min}}} of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device. [ABSTRACT FROM AUTHOR]

In this paper, NH3 plasma directly applied to the surface of poly-Si channel is studied for the development of high-performance low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with HfO2 high- \kappa gate dielectric. The reduction of threshold voltage from 1.52 to 0.62 V, the decrease of subthreshold swing from 227 to 151 mV/decade, and the enhancement of field effect mobility \mu _{\mathrm {FE}} from 31 to 65 cm ^{\mathrm {\mathbf {2}}}$ /Vs are observed after NH3 plasma surface treatment. It can be attributed to the NH3 plasma surface treatment enabling defect passivation and plasma-induced interfacial layer (PIL) growth. To decouple the impacts of defect passivation and PIL growth, the device without PIL is also fabricated. This paper demonstrates the important impacts of NH3 plasma surface treatment on the improvement of electrical characteristics of LTPS-TFTs. [ABSTRACT FROM PUBLISHER]

In this paper, the opposite impacts of N2O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N2O plasma surface treatment is observed, including threshold voltage reduction \Delta V\mathrm {\mathbf {TH}}\sim -0.57 V, 1.55× higher transconductance G\mathit {m} , and 1.82× higher driving current I{\rm{drv}} . However, p-channel LTPS-TFT shows serious performance degradation after N2O plasma surface treatment, including threshold voltage increase \Delta V\mathrm {\mathbf {TH}}~\sim -0.99 V, transconductance G\mathit {m} reduction, and driving current I\mathrm {\mathbf {drv}} degradation. The difference of the two mechanisms of N2O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N2O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit. [ABSTRACT FROM PUBLISHER]

In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (Nit) and bulk traps (NGB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit \sim 4.5\times higher ON-state current I_{\text {ON}} , subthreshold swing reduction \Delta \text{S}$ .S. \sim 202$ mV/decade, and larger \sim 7.2\times $ ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced and a reduced \text{N}_{\mathrm {\mathbf {GB}}}\sim 0.36 \times , respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics. [ABSTRACT FROM PUBLISHER]

In this paper, the asymmetric driving current Idrv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO{2} gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO{2}/poly-Si interface. P-channel LTPS-TFT has much higher Idrv\sim 0.789~mA than the n-channel LTPS-TFT \sim0.274~mA under the same overdrive gate voltage. This asymmetric Idrv is due to the characteristics of field effect mobility \muFE that p-channel LTPS-TFT has much higher hole \muFE\sim 80.16~cm^{{2}}/Vs than the electron \muFE\sim 38.26~cm^{{2}}/V~s of n-channel LTPS-TFT. The modification of HfO{2}/poly-Si interface by O{2} plasma can enhance the electron \muFE\sim {34\%} and reduce the hole \muFE\sim{22.4\%}, resulting in balanced Idrv of CMOS LTPS-TFTs that n-channel device shows Idrv\sim 0.553~mA and p-channel device shows Idrv\sim 0.590~mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO{2} gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

In this letter, for the first time, a novel p-n-diode (PND) structure of SONOS-type thin-film transistor (TFT) nonvolatile memory (NVM) with embedded silicon nanocrystals (Si-NCs) in the silicon nitride layer using an in situ method is successfully demonstrated. This novel structure has many advantages, including high density and suitability for 3-D circuit integration. Hot-electron injection and hot-hole injection are used as the program and erase methods, respectively. The sensing current of the three-terminal PND-TFT NVM is \10^-7 A by the band-to-band tunneling current. A much larger memory window (>\12 \ \V) and good data retention time (>\10^8\ \s for 12% charge loss) are exhibited. The device appears to have great potential for system-on-panel applications. [ABSTRACT FROM PUBLISHER]