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HfO2 based ferroelectric field-effect transistors (FeFETs) are promising for low-power and high-speed non-volatile memories. However, FeFETs can be susceptible to write disturbs due to their accumulative switching behavior, which limits their application in large scale memory arrays. Here we show that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs under both ${V}_{\textit {dd}}$ /2 and ${V}_{\textit {dd}}$ /3 inhibit schemes, but not to continuous write disturb. This contrasts with previous reports which found no difference between pulsed and continuous write disturbs. Our findings suggest that accumulative polarization switching is not an intrinsic property of HfO2 based FeFETs, but might be related to charge trapping dynamics instead. [ABSTRACT FROM AUTHOR]

The ferroelectric field-effect transistor (FEFET) is an emerging nonvolatile memory technology that can offer ultra-scalability, fast operation, and reduced power consumption. However, a limited understanding of FEFET physics poses challenges for optimum device design. In this article, we provide physical insights into the operation of FinFET-based FEFETs (FEFinFETs) using a phase-field framework built on time-dependent Landau–Ginzburg (TDGL) thermodynamic theory. We exploit the source–drain fringing field to stabilize a monodomain configuration in the OFF state of short channel FEFinFETs. Based on recent experiments, we first analyze the switching dynamics of FEFinFETs with low remnant polarization (${P}_{r}$) and high coercive field (${E}_{c}$) hafnium zirconium oxide (HZO) FE. We find that the switching in these FEFinFETs occurs via domain nucleation and growth from the gate metal edges at the source–drain spacers. We also show that a non-zero drain bias can be used for dynamically modulating the memory window (MW) of FEFinFET to lower its power consumption. Furthermore, we find the spacer permittivity to be a crucial design parameter to control the MW and show that a lower spacer permittivity can significantly increase the MW. Finally, we show that the commonly held idea that a large ${P}_{r}$ leads to a large MW is not always valid. For a large ${P}_{r}$ , the formation of multiple domains in the FE layer can lead to a significant reduction in the MW. In addition, these devices can suffer from low write endurance due to exposure of the interfacial oxide layer to high electric fields. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FeFETs) based on HfO2 are promising for low-power and high-speed non-volatile memory devices. However, most reported FeFETs show limited write endurance and significant read-after-write delay due to parasitic charge trapping. Here we show that n-type FeFETs with SiNx interfacial layer and high write endurance also exhibit immediate read-after-write behavior due to negligible charge trapping. This overcomes one of the major challenges faced by FeFET technologies today. [ABSTRACT FROM AUTHOR]

State-of-the-art Fully-Depleted Silicon-on-Insulator Transistors of different gate lengths were measured down to ${\text{L}}_{G}=20$ nm. A quasi-ballistic virtual source model was found to be in good agreement with the observed data for both NFET and PFET. The extracted injection velocity increases with decreasing channel length, as expected, reaching ${9.51}\times {10}^{{6}}\text {cm/s}$ for electrons and ${7.16}\times {10}^{{6}}\textit {cm/s}$ for holes at ${\text{L}}_{G}=20$ nm. These values are more than 80% of the thermal velocity in lightly-doped bulk silicon. Analysis shows that quantum confinement in the thin SOI channel as well as strain effects are potentially responsible for such ultra-high velocity. These results indicate that further scaling of the channel length could make it possible to approach the non-degenerate thermal velocity. [ABSTRACT FROM AUTHOR]

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles. The ferroelectric transistors (FeFETs) incorporate a high- $\kappa $ interfacial layer (IL) of thermally grown silicon nitride (SiNx) and a thin 4.5 nm layer of Zr-doped FE-HfO2 (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of $\text {V}_{\text {G}}= \pm \,\,3\text{V}$ at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability. [ABSTRACT FROM AUTHOR]

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and 2 μm, in an inverter circuit. At 2-μm gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors. [ABSTRACT FROM AUTHOR]

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator. ${\Omega }$ -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 108 endurance cycles. The impact of ${V} _{\text {D}}$ on erase speed provides insights into the importance of holes on memory operation. [ABSTRACT FROM AUTHOR]

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency (Ft) by ~10% and minimum number of substacks and minimum substack spacing should be used. [ABSTRACT FROM AUTHOR]

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance. [ABSTRACT FROM AUTHOR]

The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit. [ABSTRACT FROM AUTHOR]

The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming. [ABSTRACT FROM AUTHOR]

We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current (${I}_{ \mathrm{OFF}}$) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$. On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$. Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes. [ABSTRACT FROM AUTHOR]

1/ ${f}$ noise is characterized on thick and thin-gate oxide-based FinFETs for different channel lengths. The devices exhibit gate bias dependence in 1/ ${f}$ noise even in the weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or space. Based on our characterization results for n- and p-channel FinFETs, we have improved the BSIM-CMG industry standard compact model for the FinFETs. The improved model is able to capture the 1/ ${f}$ noise behavior over a wide range of biases, channel lengths, fin numbers, and number of fingers. [ABSTRACT FROM AUTHOR]

The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance. [ABSTRACT FROM AUTHOR]

A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor is presented in this letter. By introducing nonuniform oxidation, the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness of SiO2 at the center region of the channel. As a result, the capacitance along the channel becomes more uniform, and better capacitance matching between the dielectric and ferroelectric can be achieved. The Sentaurus TCAD results show improvement of matching in the center region and a significant boost of ON-current (20% improvement). [ABSTRACT FROM AUTHOR]

We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations. [ABSTRACT FROM AUTHOR]

Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance (${C}_{\textsf {fe}}$) and the underlying MOS transistor (${C}_{\textsf {MOS}}$). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$. The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor. [ABSTRACT FROM AUTHOR]

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices. [ABSTRACT FROM AUTHOR]

We propose a new scheme to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials. The scheme is used to extract material parameters from experimental polarization-electric field (P-E) measurements from the literature. A Sentaurus TCAD structure is constructed with the extracted parameters, and the simulated P-E curve is in a good agreement with the experimental data. Furthermore, variation of the device performance in a negative capacitance field-effect transistor (NCFET) due to the spatial distribution of DE and FE phases is studied using Sentaurus TCAD. It is found that the resultant variations of on and off currents can be up to 14.44% and 30.23%, respectively, thus showing the impact of inhomogeneous crystalline phases of the FE material on device performance. [ABSTRACT FROM AUTHOR]

Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$. Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

Negative capacitance (NC) FETs with channel lengths from 30 nm to 50~\mu \textm , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation. [ABSTRACT FROM PUBLISHER]

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements. [ABSTRACT FROM PUBLISHER]

We show that recently fabricated Chevron-type graphene nanoribbons act as a monolithic superlattice structure. This is enabled by the large periodic unit cells with regions of different effective bandgaps in these nanoribbons, resulting in minibands and gaps in the density of states above the conduction band edge. Quantum transport calculations based on non-equilibrium Green’s function formalism reveal that a negative differential resistance (NDR) is expected to manifest in these nanoribbons. Due to the relatively low density of states, such NDR behavior can also be modulated with a gate electric field. We show that a sub-thermal subthreshold swing ( < \textit kT/q ) can potentially be obtained in a three-terminal configuration, even in the presence of optical phonon scattering. [ABSTRACT FROM AUTHOR]

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of >10^10 read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated. [ABSTRACT FROM PUBLISHER]

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data. [ABSTRACT FROM PUBLISHER]

We analyze the effects of ferroelectric leakage on the performance of a negative capacitance field-effect transistor (NCFET), which has an intermediatemetallic layer between the ferroelectric and the high-K dielectric. We show that, when designed without taking the dielectric leakage into account, the NCFET performance can actually degrade significantlywith respect to that of the baseline FET. To overcome these detrimental effects of leakage, we propose the concept of work-function engineering, where metals of dissimilar work-functions are used for the external gate electrode and the intermediate metallic layer. Using this approach, the ferroelectric charge–voltage characteristic is shifted along the voltage axis, which results in superior performance of the NCFET. [ABSTRACT FROM PUBLISHER]

We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel–Kramers–Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with smaller effective mass and with increasing bias. We at first use the Gaussian quadrature method to integrate Landauer’s equation for tunneling current computation without further approximations. To boost simulation speed, some approximations are made. The simplified equation shows a good accuracy and has more flexibility for compact model purpose. The model is implemented into industry standard Berkeley Short-channel IGFET Model-common multi-gate model for future technology node, and is validated by the full-band atomistic quantum transport simulation data. [ABSTRACT FROM PUBLISHER]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

We present a simulation study of the negative capacitance effect incorporating leakage through the ferroelectric (FE) negative capacitor. The dynamics of the FE is modeled using the Landau–Khalatnikov equation. When an FE and a dielectric are simply connected in series without a metal contact between them, the stabilization of negative capacitance remains unchanged irrespective of leakage. However, when a metal is used, any finite leakage through the FE makes it impossible to stabilize negative capacitance at the steady state. Nonetheless, when a voltage is applied, the series configuration enters the negative capacitance state and as long as the gate voltage is cycled faster than the time needed by the leakage current to discharge all the capacitors, the transistor shows improved subthreshold swing. These results are expected to provide insight into understanding and analyzing recent experimental results on negative capacitance. [ABSTRACT FROM AUTHOR]

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg=100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau–Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective $S$ -shaped ferroelectric charge–voltage characteristics that provides important insights into the device operation. [ABSTRACT FROM PUBLISHER]

Full-band ballistic quantum transport calculations were used to study the screening effects in ultrashort-channel few-layer MoS2 transistors. A large density of states resulted in small screening lengths while inhibiting direct source-to-drain tunneling. Short-channel effects were observed even for the structurally confined 2-D transistors resulting in degraded electrostatic control. Electron confinement effects were also observed in the OFF-state in multilayered devices. [ABSTRACT FROM AUTHOR]

The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question of response delay of ferroelectric negative capacitance. Latency requirements for digital logic require a response time on the order of 10 ps or less. In this letter, we establish a coherent theoretical framework to analyze the delay between the clock edge at the gate and the response of the semiconductor channel in a ferroelectric negative capacitance transistor. The standard Landau–Khalatnikov equation approximates the slow, diffusive limit of the classical equation of motion. Therefore, using it to predict the response speed is unphysical. After extracting the damping and kinetic inductance from THz spectroscopy data, we simulate the full classical equation of motion and analyze the delay. We find that for doped hafnium oxides, the intrinsic delay is around 270 fs, far less than what is required for digital logic. [ABSTRACT FROM PUBLISHER]

In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters. [ABSTRACT FROM PUBLISHER]

With the recent upsurge in experimental efforts toward fabrication of short-channel graphene field-effect transistors (GFETs) for analog and high-frequency RF applications—where the advantages of distinctive intrinsic properties of gapless graphene are expected to be leveraged—a critical understanding of the factors affecting both output and transfer characteristics is necessary for device optimization. Analyzing the device characteristics through ballistic electronic transport simulations within the nonequilibrium Green's function formalism, we show that a doping in the drain underlap region can significantly improve the quasi-saturation behavior in the GFET output characteristics and, hence, the output resistance and intrinsic gain. From this understanding, we provide a unified and coherent explanation for seemingly disparate phenomena—quasi-saturation and the recently reported three-terminal negative differential resistance in GFETs. We also investigate the scaling behavior of cutoff frequency and comment on some of the observed scaling trends in recent experiments. [ABSTRACT FROM AUTHOR]

We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation ( $\sim \pm 3$ %) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized. [ABSTRACT FROM AUTHOR]

In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W\textrm {fin} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data. [ABSTRACT FROM AUTHOR]

In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an off-state breakdown voltage of 600 V, and high on/off drain current ratio of \(\sim 10^{\mathrm {\mathbf {9}}}\) . [ABSTRACT FROM AUTHOR]

We propose a heterojunction vertical tunneling field-effect transistor and show using self-consistent ballistic quantum transport simulations that it can provide very steep subthreshold swings and high on current, thereby improving the scalability of TFETs for high performance. The turn-on in the pocket region of the device is dictated by the modulation of heterojunction barrier height. The steepness of turn-on is increased because of simultaneous onset of tunneling in the pocket and the region underneath and also due to the contribution of vertical tunneling in the pocket to the current. These factors can be engineered by tuning heterojunction band offsets. [ABSTRACT FROM AUTHOR]