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This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ($I_{\text {ON}}$). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ($I_{\text {OFF}}$) and $I_{\text {ON}}$ relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing. [ABSTRACT FROM AUTHOR]

This brief investigates scaled 2-D MoS2 ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS2 channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS2 FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS2 and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS2 FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs. [ABSTRACT FROM AUTHOR]

This article investigates the impact of interface trapped-charge variations on the dimensional scaling of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) under two scenarios: a uniform ferroelectric and random ferroelectric-dielectric (FE-DE) phase distribution. Our study indicates that both memory window (MW) and read margin decrease with increasing trap density (< nT >), and the MW of FeFET devices with scaled channel width can be more vulnerable to the trapped-charge variations than that with scaled gate length. Under the presence of the FE-DE phase variation, for low < nT >, the impact of trapped charges is mainly on the MW degradation for the high MW instances. As the < nT > continues to rise, the trapped charges can further worsen the worst case MW significantly. Besides, when down-scaling the interfacial layer thickness of the FeFET device to increase the MW, the increased σ MW due to the random interface trapped charges may also need to be considered. Our study may provide insights for device design with advanced FeFET NVMs. [ABSTRACT FROM AUTHOR]

Single ferroelectric-FET (FeFET) reconfigurable logic-in-memory is an attractive beyond-von-Neumann scheme for data-centric computing. Different from using body-to-source voltage to tune the operating point of the FeFET for reconfigurability, this brief presents an alternative approach based on the unique ferroelectric minor-loop behavior (which results from the partial switching of domains). Through simulation, we show that the NAND/ NOR reconfigurability can theoretically be achieved by adequately modulating the reference and writing pulses for the FeFET nonvolatile memory (NVM). Our approach may serve as an option when the body-effect capability is lacking for nonplanar FeFETs or 3-D stacked FeFETs which can be crucial to future high-density integration. [ABSTRACT FROM AUTHOR]

This paper investigates the fin-width ($\text{W}_{\textsf {Fin}}$) sensitivity of threshold voltage ($\text{V}_{\textsf {T}}$) for InGaAs and Si channel negative-capacitance FinFETs (NC-FinFETs) using a theoretically derived quantum subthreshold model corroborated with TCAD numerical simulation. Our study indicates that due to the action of negative capacitance, the NC-FinFET possesses smaller $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ than the FinFET counterpart. In addition, we point out and demonstrate that a device design with higher internal voltage amplification can be utilized to further reduce the $\text{V}_{\textsf {T}}$ sensitivity to $\text{W}_{\textsf {Fin}}$ for NC-FinFETs. Our study may provide insights for future scaling of FinFETs. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

For the first time, the drain-bias dependence of mean free path, predicted by previous Monte Carlo simulations, is experimentally confirmed in Si ${n}$ FinFETs by using an improved formulation, considering the additional scatterings attributed to source/drain as well as the carrier degeneracy. This letter indicates that, for optimized Si ${n}$ FinFETs, the carrier velocity and drive current still increase monotonically with decreasing channel length. However, the degradation in mean free path leads to the saturation in ballistic ratio (~60%), resulting in quasi-ballistic transport for devices even with sub-20-nm channel length. [ABSTRACT FROM AUTHOR]

This letter investigates the impact of fin line-edge roughness (Fin-LER) on the intrinsic variation of negative capacitance FinFETs (NC-FinFETs) by TCAD atomistic simulation coupled with the Landau–Khalatnikov equation. We report a feedback mechanism stemming from the internal voltage amplification inherent in the negative capacitance FET. This feedback mechanism results in the superior immunity to Fin-LER-induced threshold-voltage and subthreshold-swing variations for NC-FinFETs as compared with the FinFET counterparts. This letter may provide insights for device/circuit designs using negative capacitance FETs. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design. [ABSTRACT FROM PUBLISHER]

This brief presents a compact subthreshold model for short-channel monolayer transition metal dichalcogenide (TMD) field-effect transistors. In this model, the impact of fringe fields from the high-K gate dielectric is considered and incorporated into a new characteristic-length expression using a single model parameter. This model has been verified with 2-D numerical simulations for TMD devices with gate length down to 5.9 nm based on ITRS 2028 low-power technology node. [ABSTRACT FROM PUBLISHER]

This letter evaluates and analyzes the impacts of random variations on cell stability and write-ability of low-voltage SRAMs using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) node with the aid of atomistic TCAD mixed-mode simulations. Our study indicates that, for 6T SRAM, the monolayer/bilayer TMD devices may fail to provide the $6\sigma $ yield requirement for read static noise margin (RSNM) due to severe metal-gate work function variation in spite of their excellent electrostatics, and hence circuit techniques, such as bootstrapped dynamic power rails or the standard 8T cell, are needed. Besides, R_{\mathrm {SD}} as a major concern of TMDs should be less of an issue for near-/sub-threshold SRAMs for ultra low-power applications. For the standard 8T cell structure, the RSNMs of both monolayer and bilayer 8T SRAMs improve significantly, and the bilayer 8T SRAM exhibits better write static noise margin (WSNM). In addition, write-assist techniques (including negative bit-line, boosted word-line, and lower cell supply) for improving WSNM are examined and shown to be more effective for monolayer 8T SRAMs than the bilayer counterparts. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

This paper provides an analytical subthreshold model for trigate MOSFETs with thin buried oxide (BOX) for multithreshold (multi- Vth ) applications. This model shows a fairly good scalability in substrate bias and BOX thickness, which is crucial to the prediction of multi- Vth modulation through BOX. In addition, we demonstrate the application of our model in multi- Vth device design for trigate GeOI p-MOSFETs with the body-effect coefficient ( $\gamma $ ) over a wide range of design space efficiently examined. We have shown an enhanced multi- Vth modulation behavior in trigate GeOI p-MOSFETs. Our study indicates that, for a given subthreshold swing and $\gamma $ , the GeOI trigate p-MOSFET can possess a higher fin aspect ratio than the SOI counterpart. [ABSTRACT FROM PUBLISHER]

We present a comparative leakage analysis of germanium-on-insulator (GeOI) FinFET and germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit levels. Band-to-band tunneling (BTBT) leakage-induced bipolar effect is found to result in an amplified BTBT leakage for GeOI FinFET. Device and circuit designs to mitigate the amplified BTBT leakage of GeOI FinFETs are suggested. The effectiveness of various high threshold voltage technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed. [ABSTRACT FROM AUTHOR]

Using a novel Voronoi method that can provide a more realistic representation of metal-gate granularity, we investigate and compare the impact of work-function variation (WFV) on FinFET and ultrathin body (UTB) silicon-on-insulator (SOI) devices. Our study indicates that, for a given electrostatic integrity and total effective gate area, the FinFET device exhibits better immunity to WFV than its UTB SOI counterpart. We further show that, unlike other sources of random variation, the WFV cannot be suppressed by equivalent oxide thickness scaling. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of intrinsic random variability on the robustness of sense amplifier (SA) for fin-shaped field-effect transistor (FinFET) subthreshold static random access memory (SRAM) applications. We employ a model-assisted statistical approach to consider both fin line edge roughness (fin LER) and work function variation, which are regarded as the major variation sources in an advanced FinFET device. Our results indicate that fin LER dominates the overall variability of subthreshold SA robustness and sensing margin. In addition, it is observed that the offset voltage (\VOS) of current latch SA calculated solely from threshold voltage (\VT) mismatch underestimates the actual variation and is shown to be optimistic. For large-signal single-ended inverter sensing, we find that sense “0” hinders the allowable sensing margin and needs to be carefully designed. Compared with bulk CMOS, the superior electrostatic integrity and variability of FinFET enhance the feasibility of differential sensing in subthreshold SRAM applications. [ABSTRACT FROM AUTHOR]

In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS= 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (Leff, \rm EOT, Wfin, and Hfin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of \mu/\sigma ratio. [ABSTRACT FROM AUTHOR]

This paper provides a closed-form model of the “dark space (DS)” for Ge MOSFETs with high- k gate dielectrics. This model shows accurate dependences on barrier height, surface electric field, and quantization effective mass of the channel and gate dielectric. Our model predicts that the surface DS due to quantum confinement decreases with reverse substrate bias and increasing channel doping. Our model can be also used for devices with a steep retrograde doping profile. This physically accurate model will be crucial to the prediction of the subthreshold swing and electrostatic integrity of advanced Ge devices. [ABSTRACT FROM AUTHOR]

For the first time, the high-frequency noise behavior of tensile-strained n-channel metal–oxide–semiconductor field-effect transistors, including their temperature dependency, is experimentally examined. Our experimental results show that with similar saturation voltages, the strained device is found to have larger channel noise than the control device at the same bias point. For given direct-current power consumption, however, due to enhanced transconductance, the strained device has better small-signal behaviors (higher ft and f\max) and noise characteristics (smaller NF\min and Rn) than the control device. [ABSTRACT FROM PUBLISHER]

This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating in a subthreshold region using an efficient model-based approach to consider the impact of device variations. Compared with the 6T cell, this paper indicates that 4T SRAM cells exhibit a better nominal read static noise margin (RSNM) because of the reduced read disturb. For 4T cells, the nearly ideal values of Vwrite, 0 and Vwrite, 1 guarantee the positive nominal write static noise margin (WSNM) for selected cells. For half-selected cells on the selected bit line, a sufficient margin is observed between write time (for selected cells) and write disturb (for half-selected cells). Using the established model-based approach, the variability of subthreshold 6T and 4T SRAM cells is assessed with 1000 samples. Our results indicate that the 4T driverless cell with a larger \mu\RSNM and a slightly worse \sigma\RSNM shows a comparable \mu/\sigma ratio in RSNM with the 6T cell. Furthermore, for a given cell area, 4T SRAM cells using relaxed device dimensions with reduced \sigma\RSNM can outperform the 6T cell. For write operation, 4T SRAM cells exhibit a superior WSNM, whereas the design margin between write time and write disturb needs to be carefully examined to ensure an adequate margin considering device variability. [ABSTRACT FROM PUBLISHER]

This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading read static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of write SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-k metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (\SiO2 and \SiO2/\HfO2) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the \mu/\sigma ratio in RSNM. [ABSTRACT FROM PUBLISHER]

This letter reports a built-in effective body-bias effect in ultra-thin-body (UTB) hetero-channel III-V-on-insulator n-MOSFETs. This effect results from the discrepancies in electron affinity and the effective density-of-states of conduction band between the III–V and conventional Si channels. Our study indicates that, in addition to permittivity, it is the built-in effective body-bias effect that determines the drain-induced-barrier-lowering characteristics of the hetero-channel devices. This intrinsic effect has to be considered when one-to-one comparisons among various UTB hetero-channel MOSFETs regarding the electrostatic integrity are made. [ABSTRACT FROM PUBLISHER]