Search

In the present work, the impact of ZrO2 gate dielectric thickness on the electrical performance of TiO2 thin film transistors (TFTs) is systematically investigated. Exhaustive electrical measuremen...

We report one-volt TiO2 thin film transistors (TFTs) with a low-temperature fabrication process. The TFTs with the 300 °C-annealed TiO2 channel exhibit a high on/off current ratio ( $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}})$ of $5.4\times 10^{7}$ , a low subthreshold swing (SS) of 75 mV/dec and a saturation field effect mobility ( $\mu _{{\mathrm {sat}}}$ ) of 2.13 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ under an ultra-low voltage of 1 V. In contrast, the TFTs with the 200 °C-annealed TiO2 channel show no appreciable currents. Such a distinct conductivity difference is attributed to the crystallinity transformation of stoichiometric TiO2, the charge transport of which can be well explained by the multiple-trapping-and-release (MTR) model. The channel/dielectric interfaces of these one-volt TiO2 TFTs are further investigated by transmission electron microscopy (TEM), multi-frequency ( ${f}$ ) capacitance-voltage (C-V), and conductance-voltage (G-V) measurements. The interface trap density ( $\text{D}_{{\mathrm {it}}}$ ) values of $\sim 5\times 10^{12}$ cm $^{-2}\cdot {\mathrm {eV}}^{-1}$ obtained from both C-V and G-V measurements are in good agreement, suggesting a high-quality channel/dielectric interface. These one-volt TiO2 TFTs show a great potential in emerging applications, such as foldable displays and wearable sensors, where a battery-powered operation is required.

Device surface properties are critical for its performance such as channel electron density, leakage current, subthreshold swing (SS), and noise in gallium nitride high-electron-mobility transistors (HEMTs). In this article, the improved surface property of InAlN/GaN HEMTs with forming gas (FG, 5% H2, and 95% N2) annealing is demonstrated. X-ray photoelectron spectra (XPS) show that the number of Ga–O bonds decreases while that of the Ga–N bonds increases, an indication of the surface native oxide removal after FG annealing. Compared with N2 annealing, an increase of two-dimensional electron gas (2DEG) electron density with FG annealing is determined by both energy band simulation and capacitance–voltage measurement. Transmission line measurement (TLM) shows that N2 annealing offers a lower ohmic contact resistance ( ${R}_{\text {C}}$ ) while FG annealing features a lower sheet resistance ( ${R}_{\text {sheet}}$ ). Herein, a FG/N2 two-step ohmic contact annealing is developed to achieve a SS of 110 mV/dec, a transconductance ( ${g}_{\text {m}}$ ) peak of 415 mS/mm, a record low drain-induced barrier lowing (DIBL) of 65 mV/V, and a record high power gain cutoff frequency ( ${f}_{\text {max}}$ ) of 270 GHz on a 50-nm InAlN/GaN HEMT on Si.

Germanium tin (GeSn) with a Sn content of >12% has a great potential for optoelectronic devices due to its direct bandgap property. In this work, the anisotropic etching of GeSn with Sn content of 12.5% and selective etching of Ge over GeSn were explored by inductively couple plasma (ICP) dry etching to obtain various microstructures. Through adding oxygen into chlorine and argon and adjusting the process pressure, the anisotropic etching of GeSn was optimized with an ideal sidewall angle of 89o. The optimized process is compatible with both positive and negative resists. By altering the ICP power, Ge etching recipes with low and high etching rates were developed, which are favorable for fabricating GeSn nano- and micro-structures, respectively. An etching selectivity of >126 for Ge over GeSn with Sn content of >10% can be achieved. With the optimized dry etching recipes, suspended GeSn microribbons and microdisks were realized. Ultimately, the suspended GeSn microstructures were transferred onto 40-nm-thick ZrO2 on p+-Si to form a GeSn-on-insulator (GeSnOI) substrate. For a fabricated 45-nm-thick Ge0.875Sn0.125OI back-gated transistor, the subthreshold swing (SS) of 240 mV/dec is reasonably low for a non-optimized device, suggesting that the explored dry etching methods are promising for device processing.

In this letter, a subthreshold swing (SS) of sub-60 mV/dec is for the first time observed in InAlN/GaN high electron mobility transistors (HMETs). With a 40-nm gate length ( ${L} _{{\text {g}}}$ ), an average SS of 30 mV/dec over three orders of magnitude in drain current ( I d) and a minimum point-by-point SS of 15 mV/dec are achieved. The transistor body factor ( m ) of 4.99/6.98 (in forward/reverse sweep) determined from temperature-variation measurements indicates that the sub-60 mV/dec SS characteristic is not attributed to the negative capacitance effect. The negative differential resistance (NDR) of gate current ( I g) is observed and the hot electron transfer from channel to gate is believed to account for the sub-60 mV/dec SS characteristic. It is further confirmed by the fact that, SS decreases as drain-source voltage ( V ds) increases and L g decreases. Due to the increased V ds and decreased $L_{\text {g,}}$ the channel lateral electric field is strengthened, leading to the hot electron formation and thus the enhanced effect of hot electron transfer on the SS. This sub-60 mV/dec SS characteristic in the nanoscale devices shows the great potential of the InAlN/GaN HEMTs to be applied in future logic switches.

Metal-oxide thin-film transistors (TFTs) promise to enable lightweight and low-power applications, such as ultrathin active matrix displays and low-cost RF identification tags. However, most reported high-performance metal-oxide TFTs contain high-cost indium and gallium elements, leading to constraints in cost-sensitive application. Herein, we present enhancement-/depletion-mode (E-/D-mode) TiO2 TFTs via $\text{O}_{{2}}/\text{N}_{{2}}$ preannealing of TiO2 channel material prior to device fabrication process. It is found that the O2-annealed TiO2 TFTs exhibit improved performances compared to N2-annealed TiO2 TFTs, including increased mobility ( $\mu $ ), higher ON-/OFF-current ratio (ION/IOFF), and lower subthreshold swing (SS). This can be attributed to the passivation effects of O2 annealing, which leads to less oxygen vacancies at the channel and channel/oxide interface. On the other hand, the ionized oxygen vacancies result in the increased electron concentration in N2-annealed films and, thus, the negative shift of ${V}_{\text {th}}$ in the TFT performance. This article delivers a possible approach to improve oxide TFT performance by passivation of oxygen vacancies. Furthermore, the controlled annealing process has a great potential in the logic inverter applications when both E- and D-mode TFTs are implemented.

In this article, multilayer MoS2 manufactured from a multiple-transfer process of chemical vapor deposition (CVD)-grown monolayer MoS2 is studied. Because of the lattice mismatch and larger distanc...

In this letter, we report ultrathin-body (~15 nm) TiO2 thin film transistors (TFTs) with unprecedented electrical performance: ON-current density ( $I_{\text{on}}$ ) of 16.7 mA/mm, ON/OFF current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of $1.2 \times 10^{9}$ and subthreshold swing (SS) of 101 mV/dec. The TiO2 channel layer was deposited by thermal atomic layer deposition (ALD) followed by post-annealing in O2 ambient. The material characterizations indicate the formation of anatase TiO2 polycrystalline films and a lack of detectable oxygen vacancies, which could have acted as charging traps in channel and channel/dielectric interface, benefiting the $I_{\text{ON}}$ and the SS. These high-performance ultrathin-body TiO2 TFTs open a new venue in many applications such as high-resolution display and radiofrequency identification (RFID) tag, where high on currents and steep SS are required.

This paper presents a benchmarking comparison between InAs FinFET and gate-all-around (GAA) MOSFET by a 3-D TCAD simulation. The complete FinFET fabrication process is demonstrated followed by a TCAD simulation platform based on the experimental data. Both DC and RF simulation results are shown here. Further optimizations are explored for InAs FinFET/GAA MOSFET through TCAD simulations. It is found that with optimizations in materials, device geometry and fabrication, significant enhancement in DC/RF performances is possible with these devices. In addition, GAA MOSFET shows a better potential for future RF application.

Dielectric polymer composites consisting of inorganic fillers and polymers have wide applications in high energy density electronic devices. However, development of dielectric polymer composites with enhanced energy storage density and thermal conductivity is desired but challenge. Herein, we report polymer composites consisting of epoxy resin and silver nanoparticle-decorated Al2O3 microspheres (Al2O3-AgNPs), which show enhanced energy storage density and thermal conductivity (1.11 W/m K), at 70 wt% Al2O3-AgNPs. The discharged energy density of Al2O3-AgNPs/epoxy resin composites with 70 wt% hybrid fillers is 4.28 × 10-3 J cm−3, while the composites without AgNPs is 3.09 × 10-3 J cm−3 at 200 kV cm−1. The enhanced energy storage density and thermal conductivity are attributed to the enhanced the interfacial polarization and the bridge role of AgNp in facilitating the heat flow across the interfacial boundary, respectively. The results support the potential applications of the Al2O3-AgNPs/epoxy resin composites used as dielectric materials in modern electronics and electric power systems.

Combining high thermoelectric (TE) performance, excellent mechanical properties, and good thermal stability, half-Heusler materials show great potential in real applications, such as industrial waste heat recovery. However, the materials synthesis technology developed in the laboratory scale environment cannot fulfil the requirements of massive device fabrication. In this work, a batch synthesis utilizing the self-propagating high-temperature synthesis (SHS) method was used to prepare state-of-the-art n-type Zr0.5Hf0.5NiSn0.985Sb0.015 and p-type Zr0.5Hf0.5CoSb0.8Sn0.2 half-Heusler alloys. Due to the nonequilibrium reaction process, dense dislocation arrays were introduced in both n-type and p-type materials, which greatly depressed the lattice thermal conductivity. As a consequence, the zT values of samples cut from ingots weighing a few hundreds of grams compared favorably with those prepared from few gram laboratory size pellets. Based on the high TE performance, a three-dimensional finite element model encompassing all relevant parameters was applied to optimize the topological structures of both a half-Heusler single-stage module and a half-Heusler/Bi2Te3 segmented module. The optimized modules attained record-high conversion efficiencies of 9.6% and 12.4% for the single-stage and the segmented module, respectively. The work documents a comprehensive processing of novel TE materials culminating in the assembly of efficient TE modules. As such, it paves the way for widespread commercial applications of TE power generation.

Over decades, the electrical properties of metal oxides have been a myth, stimulating rigorous debate and research. It is commonly accepted that the oxygen vacancy, working as shallow donors, gives rise to the n-type semiconductor behavior in these metal oxides. However, the function of the oxygen vacancy has been doubted, the energy level of which is reported to be far below conduction band to be responsible for the n-type conductivity [1] . In addition, metal oxides with oxygen deficiency in nature is susceptible to the spurious oxidation from the environment, resulting in stability and reliability issue in electronic device. In this work, we observe the conductivity transition from insulator to semiconductor of the stoichiometric TiO 2 films via judicious control of the crystallinity, highlighting the important role of crystallinity in the electrical properties of metal oxide. Based on this observation, high-performance thin film transistors (TFTs) with polycrystalline TiO 2 (poly-TiO 2 ) as the active channel and InAlN/GaN metal-insulator-semiconductor high-mobility-electron-transistors (MISHEMTs) with amorphous TiO 2 (a-TiO 2 ) as the gate dielectrics are demonstrated, indicating the full potential of stoichiometric TiO 2 films as functional electronic materials in device applications.

We report on, for the first time, high-performance, sub-2 volts TiO 2 thin film transistors (TFTs) enabled by ultrathin ZrO 2 gate dielectrics. The effect of ZrO 2 thickness on TFT performance is systematically studied. It is found that the TFT performances are enhanced with the reduced ZrO 2 thickness, benefiting from the increased gate oxide capacitance $(\mathrm{C}_{\text{ox}})$ . The TiO 2 TFTs with an ultrathin ZrO 2 dielectric of 5 nm show a high $\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}}$ of $7.7\times 10^{7}$ and a nearly ideal SS of 72 mV under an ultra-low voltage of 2 V. The highperformance, sub-2 volts TiO 2 TFTs show great promise for future portable electronic applications.

This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.

Due to the thin InAlN barrier layer, leakage current is a serious problem in InAlN/GaN high-electron-mobility transistors (HEMTs). The InGaN back-barrier can raise the conduction band of the GaN buffer layer and enhance the carrier confinement, resulting in a reduced buffer leakage current. The surface oxidation treatment prior to gate deposition can form an oxide layer and reduce the barrier leakage current. In this study, using both technologies, a record low off current (Ioff) and a record high on/off current (Ion/Ioff) ratio are achieved on InAlN/GaN HEMTs on silicon substrate. The InAlN/GaN HEMT with a 70-nm rectangular gate presents a low Ioff of 7.15 × 10−8 A/mm, a high Ion/Ioff ratio of 2.20 × 107, an average subthreshold swing (SS) of 69 mV/dec, and a low drain-induced barrier lowering (DIBL) of 90 mV/V. The InAlN/GaN HEMT with a 70-nm T-shaped gate exhibits a low Ioff of 3.26 × 10−8 A/mm, a high Ion/Ioff of 4.5 × 107, an average SS of 60 mV/dec, and a DIBL of 30 mV/V. To the best of our knowledge, these are record values among the reported InAlN/GaN HEMTs on Si. RF measurements present that current/power gain cutoff frequency (fT/fmax) of 215/45 GHz and 130/160 GHz are achieved on the 70-nm InAlN/GaN HEMTs with rectangular and T-shaped gate, respectively.

GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted much attention owing to the low-cost and the large area availability of the Si substrate. In this paper, the 90-nm-gate-length InAlN/GaN HEMT on silicon was fabricated and the device electrical properties were studied. The device presents a low drain-induced barrier lowing (DIBL) of 43 mV/V, a parasitic source resistance (RS) of 0.91 Ω⸱mm, and a peak of the intrinsic transconductance (gm0) of 553 mS/mm. To the best of our knowledge, this is the lowest DIBL value among the reported GaN HMET on Si with gate length (Lg ) below 100 nm. The low-filed two-dimensional electron gas (2DEG) electron mobility ( μn) was extracted and the dominated polarization Coulomb field scattering contributed to the increased μn with the increased of two-dimensional electron gas electron density (n2D). A current gain cutoff frequency (fT) of 175 GHz was achieved on InAlN/GaN HEMTs with a gate length of 90-nm.

A method to engineer the peak-to-valley ratio (PVR) by design of the epitaxial layers is presented. The impact of Al content on PVR of InAs/AlSb/Al(x)Ga(1−x)Sb tunnelling diode is studied. A simplified analytical model is used to explain the PVRs dependence on Al content. It was found that PVR reaches its maximum when Al content x is zero with a quantised InAs layer. The peak positions appeared in the negative differential region are effectively controlled by the applied gate bias. A PVR ratio as high as 7.1 was achieved, which is beneficial for a wide range of circuit applications. Adjusting Al content provides a new way to engineer the PVR as opposed to the conventional way of being optimised by varying barrier thicknesses or doping levels.

Recently, oxide-based thin film transistors (TFTs) are considered as a potential alternative to Si -based TFTs in backplane technology for the active-matrix display application due to its good optical transparency and excellent uniformity over large area [1]–[2]. Among all the oxide semiconductors, TiO 2 , with its high transparency to visible light, low-cost growth method, as well as great chemical and mechanical stability, has attracted more attentions [2]–[4]. TiO 2 -based TFTs with appreciable performances have been reported in some previous works, demonstrating their potential in display applications [2]–[6]. Herein, we present high-performance TFTs based on 15 nm ultrathin body TiO 2 with record on/off current ratio of $4.87\times 10^{8}$ and average subthreshold swing (SS) of 129 mV/dec.

In this work, the effects of bis(trifluoromethane) sulfonimide (TFSI) (a superacid) surface treatment on electrical properties of nickel/InAs contacts and InAs material are investigated with transmission line measurements (TLMs). After TFSI treatments on bare InAs TLM patterns, the contact resistance between InAs and Ni contact increased. While for InAs TLM structure passivated with a ZrO2 thin film, the total resistance of InAs decreased drastically after TFSI treatments. X-ray photoelectron spectroscopy measurements revealed that the TFSI reduced the indium oxide at the InAs/ZrO2 interface. This novel passivation method can be adopted in III–V semiconductor device fabrication process to reduce contact resistance and, therefore, enhance device performances, providing a new guidance for III–V fabrication process technology.

In this paper, a post superacid (SA) treatment was proposed to enhance the performance of InAs FinFETs on SiO2/Si substrates. Typically, the subthreshold swing (SS) has reduced from 217 to 170 mV/decade and the transconductance ( ${g}_{m}$ ) has increased from 6.44 to 26.5 $\mu \text{S}/\mu \text{m}$ after SA treatment. It was found that the interfacial In2O3 at the InAs/ZrO2 interface was effectively reduced after SA treatment due to the strong protonating nature of the SA solution. As a result, the interface trap density was reduced leading to a pronounced reduction of sheet resistance after SA treatment. The modeling of transfer characteristics indicates that the carrier mobility is enhanced by 5.8~7.1 folds after SA treatment due to interfacial traps reduction. The results suggest that SA treatment can be potentially extended to other III–V MOSFETs to enhance the device performances.

In this work, three-dimensional (3D) Ge condensation of sputtered “Si/SiGe” nanostructures on SiO2/Si substrate was investigated. Through varying the width of sputtered Si/SiGe structures from 50 μm to 400 nm, the Ge content of fabricated SiGe structures can be modulated from 0.49 to 1.0 after 3D Ge condensation. By further constructing a width modified nanowire (NW) with adjacent widths of 800 nm and 400 nm before 3D Ge condensation, a Si0.33Ge0.67/Ge heterostructure NW was fabricated after 3D Ge condensation. Due to inter-diffusion of Si and Ge atoms, a ∼2-μm-long region with gradually varied Ge content from ∼0.67 to 1.0 is formed between Si0.33Ge0.67 and Ge. The low Schottky barrier height (0.29 eV) of Ge NW/metal contact and good conductivity of the Ge NW suggest that the 3D Ge condensation technique is very promising for fabrication of scalable and low-cost SiGe or Ge nano-electronic/photonic devices.

This paper demonstrates the design strategy in the self-aligned quantum-well InAs MOSFETs with T-shape S/D. A 2-D TCAD simulation is performed based on the experimental data. The effect of air gap between the T-shape metal contacts is taken into account. It is found that the fringing effects induced by the air gap has significant impacts on both DC and RF performances. Further study is carried out based on this TCAD simulation platform. The channel extension region, which is simply considered as part of series resistances, needs to be properly designed to maximize fT and fMAX. RF performances can’t be further improved even if the gate length is aggressively scaled down. However, the reduction of contact resistance can improve fT and fMAX without any limitations. This contact resistance reduction can be realized by incorporating the additional annealing process in the self-aligned gate-last T-S/D process.

In this work, the Ge condensation effect of amorphous SiGe on a SiO2/Si substrate is systematically investigated. As Ge condensation proceeds, the Ge content gradually enriches from an initial 0.24–1.0 with improving crystal quality. The enlargement of the grain size results in gradual roughening of the surface roughness. As the Ge content reaches 0.36, a high hole mobility of ∼211 cm2 · V−1 · s−1 is achieved with a hole concentration of ∼3.7 × 1015 cm−3. As the Ge content further accumulates, the grain number increases resulting in a higher hole concentration. The film mobility gradually deteriorates probably due to the following factors: strong impurity scattering at high hole concentration, increase of grain boundaries, decrease of SiGe thickness, and increase of surface roughness. A polycrystalline Ge-on-insulator with a hole concentration of ∼5.1 × 1018 cm−3 and mobility of ∼15 cm2 · V−1 · s−1 is ultimately fabricated. The investigation provides a promising method to fabricate a high hole mobility SiGe-on-insulator platform from low-cost amorphous SiGe.

In this letter, we present the electrical properties of the InAlN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MISHEMT) with plasma enhanced atomic layer-deposited ZrO2 as the gate dielectric. The InAlN/GaN MISHEMT with an on/off current (Ion/Ioff) ratio of 1.46×109 as well as a subthreshold swing (SS) of 85 mV/dec was achieved. The interface trap density (Dit) decreased from 1.16 × 1012 eV-1cm-2 (at EC-ET = 0.26 eV) to 4.68 × 1011 eV-1cm-2 (at EC-ET = 0.40 eV), indicating a good interface property. This study suggests a feasible way for the application of ZrO2/InAlN/GaN MISHEMTs

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at $V_{{\rm GS}} = V_{{\rm DS}} = 0.4$ V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.

In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >104 is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.

Various surface treatment methods have been previously applied on the GaN high electron mobility transistor (HEMT). In this study, the effects of N2O surface treatment on the electrical properties of InAlN/GaN HEMT were studied. With this surface treatment, the ideality factor of the gate Schottky barrier diode (SBD) decreases from 7.70 to 1.30, and the barrier height of SBD increases from 0.508 eV to 1.053 eV (~ two folds), an indication of the improved Schottky contact characteristic. Negative-shifted threshold voltage, decreased gate capacitance and two-dimensional electron gas (2DEG) electron density were observed. Both the intrinsic transconductance and 2DEG electron mobility are improved. The 2DEG electron mobilities limited by various scattering mechanisms are extracted using two-dimensional scattering theory. It is found that N2O surface treatment results in the increase of the 2DEG electron mobility due to the weakened polar optical phonon, interface roughness, polarization Coulomb field scatterings. This study offers a feasible way to further enhance InAlN/GaN HEMT performances by using N2O surface treatment.

Low-power, nonvolatile transistors are demanded in the digital electronics development. In our work, molybdenum disulfide (MoS2) acts as the channel material integrated with TiN, which is used as a floating gate to build a floating gate transistor. Our transistor exhibits a large hysteresis of 4 V (Vd = 0.1 V), high on/off ratio of 105, and symmetry writing and erase voltage. The excellent device characteristics such as nondestructive data readout, low operation voltage, and wide memory window inherent in single-layer MoS2 show their great potential to be applied in nonvolatile memory cells.

In this work, three-dimensional (3D) Ge condensation was carried out to explore the merits of Ge condensation method in fabricating low-dimensional SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures. Through varying the width of SGOI wires from 220 nm to 50 μm before Ge condensation, the Ge content of SiGe wires can be easily modulated from 1.0 to 0.55 after 3D Ge condensation facilitating fabrication of SiGe/Ge heterojunction nanowires (NWs). Based on the volume change of Si, Ge and SiO2 with consideration of a geometry factor, a simple 3D Ge condensation model was built. It is found that the enrichment of Ge content mainly comes from condensation effect along directions with small dimensions. The proposed 3D condensation model can be a guidance to design and fabricate low-dimensional SGOI, GOI and even SiGe/Ge heterostructures on insulator materials.

We report an 80-nm-gate-length Inalt;subagt;0.17alt;/subagt;Alalt;subagt;0.83alt;/subagt;N/GaN high-electron mobility transistor (HEMT) on silicon substrate with a record low gate leakage current of 7.12 × 10alt;supagt;-7alt;/supagt; A/mm, a record high on/off current ratio of 1.58 × 10alt;supagt;6alt;/supagt;, and a steep subthreshold swing of 65 mV/dec, which are excellent features among the reported InAlN/GaN HEMTs on Si. Due to the excellent DC performance, a current gain cutoff frequency alt;iagt;falt;/iagt;alt;subagt;Talt;/subagt; of 200 GHz is achieved, resulting in alt;iagt;falt;/iagt;alt;subagt;Talt;/subagt; × alt;iagt;Lalt;/iagt;alt;subagt;galt;/subagt; = 16 GHz μm for GaN HEMTs on Si which to the best of our knowledge is a new record.

The effect of the negative substrate bias (V sub) on the device performance of the InAlN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) is studied. When the V sub decreased from 0 V to −40 V, the two-dimensional electron gas (2DEG) electron density (n 2D) under the gate region decreased, while the 2DEG electron mobility (µ 2DEG) under the gate region was significantly improved. Due to the InGaN back barrier layer and the thin GaN channel layer (15 nm), the 2DEG electrons in the channel are injected into the InGaN back barrier layer with negative V sub, leading to the decreased n 2D. The decrease of the n 2D caused the decrease of the collision probability between the polar optical phonon (POP) and the 2DEG electrons, and the enlarged distance between the 2DEG electrons and the AlN/GaN interface, resulting in the weaker POP and interface roughness scatterings and higher µ 2DEG. This provides a possible way to increase 2DEG electron mobility and further improve the device performance of InAlN/GaN MIS-HEMTs.

We reported high performance anatase-TiOalt;subagt;2alt;/subagt; thin film transistors (TFTs) with two-step oxidized TiOalt;subagt;2alt;/subagt; channel (Oalt;subagt;2alt;/subagt; annealing and Nalt;subagt;2alt;/subagt;O plasma treatmen) and Oalt;subagt;2alt;/subagt; plasma enhanced atomic layer-deposited ZrOalt;subagt;2alt;/subagt; gate dielectric. The transistors using 60-nm TiOalt;subagt;2alt;/subagt; as the active channel exhibited a steep subthreshold swing (SS) of 112 mV/dec and a high on/off current ratio (Ialt;subagt;onalt;/subagt;/Ialt;subagt;offalt;/subagt;) of 1.4×10alt;supagt;8alt;/supagt;. The superior performances, achieved by the two-step oxidizing process and the utilization of ZrOalt;subagt;2alt;/subagt; as the high-k gate dielectric, show their great potential to be applied in future electronic and optical systems, such as active matrix displays and ultraviolet (UV) sensors.

A flexible and wearable microsensor array is described for simultaneous multiplexed monitoring of heavy metals in human body fluids. Zn, Cd, Pb, Cu, and Hg ions are chosen as target analytes for detection via electrochemical square wave anodic stripping voltammetry (SWASV) on Au and Bi microelectrodes. The oxidation peaks of these metals are calibrated and compensated by incorporating a skin temperature sensor. High selectivity, repeatability, and flexibility of the sensor arrays are presented. Human sweat and urine samples are collected for heavy metal analysis, and measured results from the microsensors are validated through inductively coupled plasma mass spectrometry (ICP-MS). Real-time on-body evaluation of heavy metal (e.g., zinc and copper) levels in sweat of human subjects by cycling is performed to examine the change in concentrations with time. This platform is anticipated to provide insightful information about an individual's health state such as heavy metal exposure and aid the related clinical investigations.

The III–V compound semiconductors exhibit superb electronic and optoelectronic properties. Traditionally, closely lattice-matched epitaxial substrates have been required for the growth of high-quality single-crystal III–V thin films and patterned microstructures. To remove this materials constraint, here we introduce a growth mode that enables direct writing of single-crystalline III–V's on amorphous substrates, thus further expanding their utility for various applications. The process utilizes templated liquid-phase crystal growth that results in user-tunable, patterned micro and nanostructures of single-crystalline III–V's of up to tens of micrometres in lateral dimensions. InP is chosen as a model material system owing to its technological importance. The patterned InP single crystals are configured as high-performance transistors and photodetectors directly on amorphous SiO2 growth substrates, with performance matching state-of-the-art epitaxially grown devices. The work presents an important advance towards universal integration of III–V's on application-specific substrates by direct growth., Growth of high-quality III–V semiconductors for electronics and optoelectronics usually requires an atomic-lattice matched substrate. Here, the authors use templated liquid-phase crystal growth to create single-crystalline III–V material up to ten micrometres across on an amorphous substrate.

The airflow dynamics observed during a cough process in a CT-scanned respiratory airway model were numerically analyzed using the computational fluid dynamics (CFD) method. The model and methodology were validated by a comparison with published experimental results. The influence of the cough peak flow rate on airflow dynamics and flow distribution was studied. The maximum velocity, wall pressure, and wall shear stress increased linearly as the cough peak flow increased. However, the cough peak flow rate had little influence on the flow distribution of the left and right main bronchi during the cough process. This article focuses on the mathematical and numerical modelling for human cough process in bioengineering.

(Ga,In)P/GaAsSb DHBTs with different emitter sizes were fabricated with the standard triple-mesa process on wafers with GaInP [Ga] emitter contents of 0, 0.15, 0.24 in the emitter. The effect of the gallium content on the DC and RF characteristics of the DHBTs was studied. It was found that gain increases as the Ga mole fraction increases. This is due to a reduced surface recombination current and intrinsic recombination current with increasing [Ga]. 0.45 × 9.5 μm2 devices with a Ga content of 0.24 show the highest cut-off frequency of 387 GHz. This is attributed to the reducing barrier at the E/B interface, which eases the injection of electrons from the emitter into the GaAsSb base. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Reinforced concrete column strengthened with angle steel has strong high temperature resistance. Through the quantitative analysis and testing of the high temperature collapse of concrete column, the formula design of reinforced concrete column is improved to enhance the high temperature collapse performance of concrete column. Reinforced concrete columns high temperature collapse technology strengthened by angle steel based on bilinear elastic hysteretic model is proposed and equivalent linear recursive analysis method is used to calculate the restoring force model of concrete column. Experimental results show that the method can be used to calculate the ultimate crack depth and fracture toughness reliability of concrete column and detect high temperature collapse of reinforced concrete columns. It can be effectively combined with regular field nondestructive testing and long-term strain monitoring to achieve high temperature collapse of concrete column detection.

A series of nanostructured iron compounds including cubic Fe3O4 and orthorhombic FeOOH were synthesized via a facile low temperature (in the range of 60−100°C) solution method. In the whole process, the interaction between FeCl2·4H2O and methenamine (C6H12N4) was carried out through a reflux device under different reaction conditions such as temperature, solvent, and duration. The samples were detected by XRD, TEM, SAED, physical property measurement system, and Mossbauer spectroscopy, separately. The experiments showed that magnetic mixture nanoparticles had flake and rod morphologies, and cubic Fe3O4 took on grain nanostructure. Magnetism measurements indicated that the saturated magnetization of the as-obtained magnetic mixture was lower than that of the cubic magnetite. Mossbauer spectroscopy testified the sample consisting of cubic magnetite rather than γ-Fe2O3. In addition, a possible growth mechanism of cubic magnetic nanoparticles under different conditions was discussed.

Combining a pseudomorphically strained (Ga,In)P emitter with a GaAs0.6Sb0.4 base effectively eliminates the emitter heterojunction type-II conduction band offset in InP/GaAsSb double heterojunction bipolar transistors (DHBTs). A peak fT of 436 GHz at JC = 10 mA/mum2, with BVCEO = 3.8 V, is achieved with 0.6 times 5 mum2 InP/GalnP/GaAsSb DHBTs with a 75-nm InP collector. Compared to a binary InP emitter, the (Ga,In)P emitter doubles the DC current gain from 166 to 338 for otherwise identical devices. These are the highest DC current gain and cutoff frequencies to date in uniform base GaAsSb DHBTs. The gain improvement reported here will greatly facilitate device design tradeoffs that are encountered while scaling InP/GaAsSb DHBTs toward higher frequencies by allowing higher base doping levels and smaller emitter geometries.

Type-II n-p-n InP/GaAsSb/InP double heterostructure bipolar transistors (DHBTs) that are fabricated by optical lithography with a 0.6 times 5 mum2 emitter on a 20-nm compositionally uniform GaAsSbxSb1-x, carbon-doped base with x = 0.60 and a 75-nm InP collector show current-gain cutoff frequencies as high as 423 GHz at 10 mA/mum2 and feature a BVCEO = 4 V. The pseudomorphic As-rich InP/GaAsSb DHBTs feature a high maximum dc current gain of > 160, owing to the reduction of the type-II conduction band discontinuity DeltaEC and the associated recombination at the InP/GaAsSb emitter-base interface. This brief demonstrates that the InP/GaAsSb DHBT technology can combine high gain, wide bandwidths, high-current drivability, and structural simplicity.

Good-quality metamorphic InP buffer layers have been successfully grown on GaAs substrates by metal-organic chemical vapor deposition. Characterization by atomic force microscope, transmission electron microscopy, high-resolution X-ray diffraction, and Hall measurements indicated that the layers are of high crystalline quality, good mobility, and excellent surface morphology. On this buffer, we demonstrated the first metamorphic InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with good material quality and device performance. Metamorphic DHBTs showed direct-current and radio-frequency characteristics that are comparable to those grown on lattice-matched InP substrates.

The non-toxic and wide bandgap material TiO2 is explored as an n-type buffer layer on p-type Cu(In,Ga)Se2 (CIGS) absorber layer for thin film solar cells. The amorphous TiO2 thin film deposited by atomic layer deposition process at low temperatures shows conformal coverage on the CIGS absorber layer. Solar cells from non-vacuum deposited CIGS absorbers with TiO2 buffer layer result in a high short-circuit current density of 38.9 mA/cm2 as compared to 36.9 mA/cm2 measured in the reference cell with CdS buffer layer, without compromising open-circuit voltage. The significant photocurrent gain, mainly in the UV part of the spectrum, can be attributed to the low parasitic absorption loss in the ultrathin TiO2 layer (~10 nm) with a larger bandgap of 3.4 eV compared to 2.4 eV of the traditionally used CdS. Overall the solar cell conversion efficiency was improved from 9.5% to 9.9% by substituting the CdS by TiO2 on an active cell area of 10.5 mm2. Optimized TiO2/CIGS solar cells show excellent long-term stability. The results imply that TiO2 is a promising buffer layer material for CIGS solar cells, avoiding the toxic CdS buffer layer with added performance advantage.

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.

In this paper, 2D MOSFET operation of a fully-depleted double-gate bulk MoS 2 is studied at a quasi-flatband of the back-gate for the first time. Several key device parameters such as equivalent oxide thickness (EOT), carrier concentration, flatband voltage, dielectric constant and carrier mobility were extracted from I-V and C-V characteristics and at room temperature. In a similar operation to the inversion-mode SOI MOSFETs in [1], the backgate was used to keep a sheet of mobile charges on the flake back-side by its quasi-flatband operation at a fixed voltage (0 V). Afterward, the top-gate was used as the active gate to perform mobile charge accumulation or depletion in the channel. Fig. 1 shows the device architecture together with the high frequency R-C equivalent circuit model for this underlap gate architecture. Fig. 2 represents the top-view microscope picture of the fabricated MoS 2 bulk MOSFET with a flake thickness of 38 nm, measured by AFM. The fabrication steps include mechanical exfoliation of MoS 2 crystals on a 260 nm thick oxidized Si substrate, e-beam lithography to make S/D pads, 50 nm Ni by thermal evaporation and lift-off, gate patterning, high-k/metal-gate stack deposition (1 nm of SiO x by thermal evaporation, 11 nm of ZrO 2 by ALD deposition at 105 °C, 30 nm of Ni by thermal evaporation) and lift-off. The measurements were done at room temperature using an Agilent B1500A Semiconductor Parameter Analyzer. Fig. 3 shows its I d -V g , reporting a subthreshold slope of 110 mV/dec. and I on /I off of ∼1×105, both at V ds =100 mV.

Porous SiC ceramics were fabricated without and with Y 2 O 3 addition from SiC, Al 2 O 3 and graphite in air by the in situ reaction bonding process. This process is based on the oxidation of SiC and the mullitization between Al 2 O 3 and oxidation-derived SiO 2 . SiC particles are bonded by the mullite (3Al 2 O 3 ·2SiO 2 ) and SiO 2 . The pores are produced by both stacking SiC particles and burning out graphite. Comparison of phase composition, microstructure, flexural strength, open porosity and pore size distribution of reaction-bonded porous SiC ceramics without and with Y 2 O 3 addition was conducted. Moreover, the effect of Y 2 O 3 content was investigated. Due to the enhancement of neck formation (bonding part between SiC particles) by the addition of Y 2 O 3 , a high strength of 27.5 MPa was achieved at an open porosity of 44.4%.