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We propose Multi Gate Oxide — Dual Work-Function (MGO-DWF)-MOSFET which is suitable for low power AB-class RF power amplifier (RF PA). This was examined for the first time by comparing with a standard Cascode connection circuitry composed of LV- and HV- MOSFETs. Dramatically improved FMAX (150 GHz) with sufficient drain break-down voltage (VBD) was experimentally confirmed in a practical device structure. MGO-DWF-MOSFET has multiple roles in a unit device such as LV-MOSFET in source side regions and HV-MOSFET in drain side regions. This distinctive structure enables the reduction of the device area and a gate capacitance (CG) with a higher transconductance (Gm) and the suppression of drain conductance (GDS). Enhancement of FMAX, in other words, DC operation current reduction is achieved at a given operation point. This indicates that MGO-DWF MOSFET is advantageous for low power amplifier circuitry applications, typically for RF PA in internet of things (IoT) products.

We develop a non-quasi-static MOSFET compact model suitable for simulating RF circuits operating under GHz frequency. The model takes into account the carrier dynamics by incorporating the time delay for the carriers to form a channel. Both the time-domain and frequency-domain expressions are successfully derived from the same basic equation by using the proposed modeling methodology, and the consistency of the both representations are verified. The model accuracy in predicting transient currents is demonstrated by comparing with simulation results of a 2D device simulator. The developed NQS model is implemented into SPICE3f5 and achieves stable circuit simulations with only 3% simulation time increase.

Non-linearity of metal oxide semiconductor field-effect transistor (MOSFET) characteristics induces harmonic distortions, which causes serious problems for RF analog applications. Features of the harmonic distortions are investigated experimentally under high frequency operations. Comparison of measured harmonic distortions with inter-modulation distortions concludes that the harmonic distortions are frequency dependent under high frequency operations. A reason for this is enhanced contribution of the displacement, which is originally frequency dependent.

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

SUMMARY A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nmMOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [111] is larger than that on [100] until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for [100] and [111] substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the [111] substrate is slightly better than that on the [100] substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4/spl deg/ from [100] axis were investigated. It was found that there are few differences in the mobility between [100] and [100] 4/spl deg/ off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal [100] substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs.

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO/sub 2/-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated.

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-/spl mu/m and 0.06-/spl mu/m gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-/spl mu/m gate length pMOSFETs using 1.5-nm gate SiO/sub 2/ for the first time. The normal oscillations of the 1.5-nm gate SiO/sub 2/ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-/spl mu/m gate length CMOS in terms of high-frequency, high-speed operation.

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.

A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

A silicided silicon-sidewall source and drain (S/sup 4/D) structure is proposed for sub-0.1-/spl mu/m devices. The merit of the S/sup 4/D structure is that the series resistance of the source and drain is significantly reduced since the silicide layer is attached very close to the gate electrode and the silicon sidewall can be doped very highly. Thus, very high drain current drive can be expected, Another advantage of this structure is that the source and drain extensions are produced by the solid-phase diffusion of boron from the highly doped silicon-sidewall. Thus, shallow extensions with very high doping can be realized. A 75-nm gate length pMOSFET fabricated with this structure is shown to exhibit excellent electrical characteristics.

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices.

We analyze the linearity of metal oxide semiconductor field effect transistors (MOSFETs) at radio frequency switching using the conventional extraction method of IP3, measured harmonic distortion (HD), and a surface-potential-based MOSFET model for circuit-simulation. The applicability of the conventional extraction method of IP3 at low frequency to represent IP3 at high frequency is also investigated. At low frequency, measured HD characteristics and extracted IP3 values correspond to the prediction by the model which adopts the quasistatic approximation, i.e., instantaneous carrier response is assumed. Beyond half of the cutoff frequency, the carrier response delay enhances the MOSFET nonlinearity, which is manifested by a decreased first order harmonic and a pronounced curvature of the third order harmonic. Consequently, the conventional extraction method of IP3 value from the intersection point of linearly extrapolated first and third harmonics becomes unreliable

A silicided silicon-sidewall source and drain (S/sup 4/D) nMOSFET is demonstrated and its hot carrier reliability is investigated for the first time. This S/sup 4/D nMOSFET exhibited high drain current and well-suppressed short channel effects concurrently. In spite of the impact ionization rate issue, the S/sup 4/D structure offers a major improvement in current and transconductance degradations as compared with the LDD structure. The mechanism of the improved hot carrier reliability is explained using a two-dimensional (2-D) simulation.

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used.

The reduction of gate length improves the performance of a MOSFET. However, this is difficult to do when the gate length is less than 0.1 μm for numerous reasons. This paper reports the results of improvement of the MOSFET performance employing various means. It was found that the current drive was only 30 percent higher with a gate length of 40 nm than with a gate length of 0.1 μm. Even when the gate oxide was 1.5 nm, which is half the oxide thickness for a direct tunneling leakage limit, it was found that the MOSFETs operate normally and the current drive was 1.6 times higher than when the gate oxide was 3 nm, because of the increase of gate capacitance. When a low-doped thin Si epitaxial layer was used as the intrinsic channel, the channel drive was improved by 20 percent because of higher carrier mobility, compared with the current-driving efficiency of a MOSFET formed by bulk material. The problem of source drain parasitic resistance increase in small-geometry MOSFETs was solved by using a novel device structure, i.e., S4D. Using this new structure, the parasitic resistance was reduced by one order of magnitude. Combining the aforementioned techniques, the current-driving efficiency could be improved further even when the gate length is in the sub-0.1 μm region.

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFET's was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFET's also operated at higher speed. >

A systematic investigation of the influences of high substrate doping on the hot carrier characteristics of small geometry n-MOSFETs down to 0.1 /spl mu/m has been carried out. Results indicate that the dependence of substrate current and impact ionization rate on substrate impurity concentration is reversed in long channel and short channel devices. In the long channel case, both increase with rising substrate impurity concentration, while they decrease in the case of short channel devices. An explanation for this phenomenon based on the lucky electron model has been developed. The dependence of other characteristics on impurity concentration has also been studied. The dependence of off-leakage current has been found to fall as the gate oxide is reduced in thickness. Regarding the dependence of hot carrier degradations, the degradation of drain currents becomes smaller as the substrate impurity concentration increases in the case of short channel devices. Further, in the extremely high impurity doping region, a new hot carrier degradation mode was found, in which the maximum transconductance values of n-MOSFETs increase after hot carrier stress. This new degradation mode can be explained in terms of effective channel length shortening caused by electron trapping. >

Forty nm gate length n-MOSFETs with ultra-shallow source and drain junctions of around 10 nm are fabricated for the first time. In order to fabricate such small geometry MOSFETs, two special techniques have been adopted. One is a resist thinning technique using isotropic oxygen plasma ashing for the fabrication of 40 nm gate electrodes. The other is a solid phase diffusion technique from phosphorus doped silicated glass (PSG) for the fabrication of 10 nm source and drain junctions. The resulting 40 mm gate length n-MOSFETs operate quite normally at room temperature. Using these n-MOSFETs, we investigated short channel effects and current drivability in the 40 nm region at room temperature. We have also investigated hot-carrier related phenomena in the 40-nm region. Results indicate that the impact ionization rate increases slightly as the gate length is reduced to around 40 nm, and that both impact ionization rate and substrate current fall significantly as V/sub d/ falls below 1.5 V. This demonstrates that reliability as regards degradation due to hot carriers is not a serious problem even in the 40 mm region if V/sub d/ is less than or equal to 1.5 V. >

In planar MOSFET, the optimization of finger length should be carried out with considering f T , f max and flicker noise because the noise degradation at STI edge effect appears below 1µm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our measurement results, the flicker noise of FinFET decreases with scaling of fin width and it is possible to satisfy the 24nm technology node requirement in ITRS roadmap 2011 at fin width below 20nm.

Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. It was also found that the gate leakage current and 1/f noise in (110) samples were sensitive to off-axis angle.

STARC (Semiconductor Technology Academic Research Center) is a research consortium co-founded by major Japanese semiconductor companies, whose mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies. One of the achievements enabled by the academia collaboration is HiSIM (Hiroshima University STARC IGFET Model) an advanced MOSFET Model. The HiSIM2 version includes required features in modeling for the 45 nm technology node and beyond such as the STI effect. A major development is an improved model consistency, which enables even modeling of the technology variation accurately. HiSIM2 realizes both accurate and fast circuit simulation.

We have developed a high-frequency noise model for short channel MOSFETs by considering the position dependent surface potential which results in a non-uniform mobility distribution along the channel. The chosen approach successfully reproduces the induced-gate noise and the cross-correlation noise between drain and gate for short channel MOSFETs without additional model parameters. In particular, the gate noise characteristics at GHz frequencies are accurately captured. The newly developed high-frequency noise model is implemented in the complete surface-potential based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model) for circuit simulation.

We have developed MOSFETs noise models for the 1/f, thermal and induced-gate noise based on self-consistent surface-potential description. Consideration of non-uniform mobility and carrier distributions arising from the surface potential distribution along the channel is indispensable for accurate noise modeling for RF applications. The developed noise models are implemented in the complete surface-potential based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model) for circuit simulations

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.

Under radio-frequency operation of MOSFETs, not only conventional 1-V characteristics and their derivatives but also higher-order phenomena have to be modeled accurately for reliable circuit performance prediction. To reproduce such critical device characteristics model development tends to follow device physics as much as possible. The surface-potential distribution, which is the origin of all device features, is the key modeling quantity and leads to straightforward description accurate even for higher-order phenomena. This is demonstrated with the circuit simulation model HiSIM for the cases of noise modeling, small-signal analysis as well as large-signal analysis.

In this paper, we describe the high analog performance of MOSFETs and inductors on 1.7/spl mu/m ultra-thin chip with permalloy film.

Fully oxygen precipitated (FOP) wafers can suppress slip generation during the STI process and maintain high substrate resistivity. Additional boron implantation can suppress the leakage current between the adjacent wells due to shallow Xj. No effect on MOSFET characteristics by this implantation was observed. The high resistivity substrate (HRS) can provide good ESD performance and suppress the passage of high frequency signals through the substrate in resistors. Thus, HRS with FOP & additional implantation is effective for future mixed signal CMOS with RF circuits.

A non-doped selective epitaxial Si channel technique has been applied to ultra-thin gate oxide CMOS transistors with TiN and polysilicon gate electrodes, and its effect on direct-tunneling gate leakage current has been investigated. It was found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current in both the TiN and polysilicon gate electrode cases. Improved drain current drive and transconductance of the epitaxial channel MOSFETs with ultra-thin gate oxides in the direct-tunneling regime has been also demonstrated.

We have, for the first time, demonstrated silicon MOSFET's with an ultra-thin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, so it is easily possible to adjust the threshold voltage of the p-MOSFET's even in the case of n-type polysilicon gates. It was confirmed that choosing an ultra-thin epitaxial layer-in the 10 nm range-leads to suppression of the short-channel effects in n-type polysilicon gate buried-channel MOSFET's, while maintaining an appropriate value of threshold voltage. >

We have presented a design method of RF power Si-MOSFETs for low voltage and high power-added efficiency operation. It has been demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve high power-added efficiency of more than 50% at 2 GHz RF operation with sufficient breakdown voltage (V/sub dss/S) by choosing optimum gate oxide thickness and N/sup -/ extension impurity concentration. Especially, efficiency of more than 50% was confirmed under very low supply voltage of 1.0 V, as well as higher supply voltage such as 2 and 3 V. The small gate length Co salicided Si-MOSFET is a good candidate for low-voltage, high efficiency RF power circuits for 2 GHz operation.

Flicker noise characteristics of 1.5 nn direct-tunneling gate oxide n- and pMOSFETs have been investigated It was confirmed that in the shorter gate length region, less than 0.2 /spl mu/m, the flicker noise decreased with the decrease in gate oxide thickness even in the direct-tunneling regime. On the contrary, it was found that with gate length larger than 0.45 /spl mu/m, the flicker noise becomes larger than that of the thicker gate oxide MOSFETs due to large gate leakage current. The degradation of flicker noise after charge injection was also compared for MOSFETs with various gate oxide thickness.

For low power operation in analog CMOS, a lot of attempts using new drain structures to reduce the parasitic capacitance of the source and drain junction capacitance (Cj) have been reported. However, there are not many approaches from the channel doping process. In the usual MOSFET structures, the highly doped channel implanted regions are localized under the gate by the mask used in the channel implantation step in order to reduce Cj. In this process, however, it is limited to localize the channel implanted region by the requirement of the margin for the mask misalignment in the photolithography process. Hence, Cj remained a serious problem to realize the high speed and low power operation. On the other hand, the importance of low frequency noise in RF and microwave circuit applications have been also increased. The authors show the gate length dependence of low frequency noise of MOSFETs. The spectral density of the drain current noise (SID) increases as the gate length decreased. This low frequency noise can be reduced by decreasing the dose of channel implantation process. However it is very difficult to suppress the low frequency noise with optimizing threshold voltage simultaneously. One of the reasons for higher 1/f noise at higher Vth is estimated to be due to the larger damage caused by larger dose of the channel implantation as explained later. The main object of this paper is the investigation of a self-align doped channel (SADC) structure as one of the candidates which can reduce the low frequency noise and the parasitic capacitance simultaneously. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate, hence the doped region is fully sell-aligned to the gate, and the junction capacitance can be reduced. Moreover the implantation damage in the channel is reduced. We examine the feasibility study of SADC structure and demonstrate high performance 0.25 /spl mu/m gate length nMOSEFTs with low noise and low power consumption by using SADC structure.

We introduce 0.18 /spl mu/m CMOS with multi-V/sub th/'s for mixed high-speed digital and RF-analog applications. The V/sub th/'s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-Vth for RF analog circuits. The zero-volt-Vth MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD), the film quality is good because higher pre-heating temperature (940/spl deg/C for 30 seconds) is used in H/sub 2/ atmosphere before epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values show significantly improved performances under the low supply voltage, which is important for 0.18 /spl mu/m CMOS with low power/low supply voltage operation. Additionally, in our experiment no significant difference was observed between the reliability of gate oxide grown on bulk and the reliability of that grown on epitaxial layers. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will be effective to realize high performance and low power CMOS devices for mixed digital and RF-analog applications.

Hot-carrier degradation in the direct-tunneling regime of the gate oxide was investigated under a wide range of conditions such as stress bias, oxide thickness, gate length, and channel-type dependencies for the first time. It was confirmed that n-MOSFETs with thinner gate oxides have higher hot-carrier reliability in the direct-tunneling regime from 1.5 nm to 3.8 nm. For p-MOSFETs, little degradation was observed under all conditions of stress bias, oxide thickness, and gate length. These results indicate that ultra-thin gate oxides in the direct-tunneling regime have extremely high hot-carrier reliability.

Very high gm values of intrinsic doped epitaxial channel MOSFETs compared with those of bulk MOSFETs has been experimentally confirmed for the first time. It has been found that preheating of the wafer before the UHV-CVD epitaxial growth is critically important to improve the crystal quality of the epitaxial layer and thus to obtain the high gm values. By adopting 700/spl deg/C 5 minutes preheating, a very high gm value of 630 mS/mm was obtained for a 0.1 /spl mu/m epitaxial channel n-MOSFET.

Silicided Silicon-Sidewall Source and Drain (S/sup 4/D) structures were proposed for sub-0.1 /spl mu/m gate length p-MOSFETs as the structure which can realize extremely small source and drain series resistance with small short-channel effects. By using this structure, 75 mm gate length p-MOSFETs were fabricated and very good electrical characteristics were confirmed. In this experiment, only p-MOSFETs were fabricated, but the S/sup 4/D structures are also suitable for the sub-0.1 /spl mu/m gate length CMOS devices, because, basically, the sidewall amorphous silicon is easily doped with the dopant of source and drain by source and drain implantation without prior in situ doping.

Low noise high-frequency analog operation of small geometry silicon MOSFETs is demonstrated. By scaling gate length down to 0.3-sub 0.1 /spl mu/m regions, excellent low noise figure of 1.5 dB at 2 GHz was obtained with low drain current of 0.3 mA//spl mu/m at f/sub T/ value of 20-65 GHz-the same level as today's high performance silicon bipolar transistors in research level. Even at low voltage operation such as 0.5 V, extremely high cutoff frequency of 48 GHz was realized by sub 0.1 /spl mu/m gate length nMOSFETs. Such low voltage operations allow one order of magnitude smaller power consumption compared with 2 V power supply voltage.

Recently, heavily nitrided NO oxynitride has been proposed as an alternative to pure oxide in order to realize high drivability and suppress a large gate leakage current (Fujiwara et al, Digest of IEDM 2000, pp. 227-30, 2000). However, in general, oxynitride has higher interface state density than that of pure oxide, and brings low frequency noise (or 1/f noise) degradation (Kimijima et al., 1999). Thus, analog characteristics under such aggressive doping conditions should be observed carefully for realization of high performance mixed analog and digital LSIs. In this paper, we report analysis of the 1/f noise degradation due to heavily nitrided NO oxynitrides and predict the interface state density value to satisfy 1999 ITRS Roadmap requirements. Additionally, a buried channel type MOSFET is proposed for suppression of the 1/f noise and f/sub T/ degradation.

We investigated the analog performance of a 0.11 /spl mu/m CMOS under a low supply voltage. In order to avoid flicker noise degradation under the low supply voltage, an epitaxial channel MOSFET without halo implantation was shown to be effective.

CMOS has been used for advanced LSIs so many years because of its excellent low-power and high-speed characteristics for highly-integrated digital circuits. For high frequency analog applications such as RF, it has not been used popularly because CMOS has been assumed to have poor capability compared with silicon bipolar and compound semiconductor devices. However, recent miniaturization of CMOS devices has significantly improved the CMOS RF characteristics. For example, typical values of f T and fmax for 0.25 μm n-MOSFETs already exceed 40 GHz, and those for 0.1 μm n-MOSFETs are more than 100 GHz. RF noise of the MOSFETs is also as good as less than 1 dB at 2 GHz operations. In this paper, CMOS technology for RF front-end circuit for mobile telecommunication devices is explained.

The high thermal-drain-noise coefficient γ for short-channel metal-oxide-semiconductor-field-effect transistors (MOSFETs) has little to do with hot electrons or velocity saturation, but is determined by the potential gradient along the channel. Consequently, an analytical model for circuit simulation, derived by integration with the surface-potential distribution along the channel, reproduces measured noise characteristics without additional fitting parameters. Furthermore, experimental and theoretical data suggest a fixed relation between the source-drain voltage (Vds) gradients of γ under the saturation condition and the threshold-voltage shift (ΔVth) relative to a long-channel MOSFET.

A method of fabricating 40‐nm gate‐length n‐metal–oxide–semiconductor field effect transistors (MOSFETs) is described in detail. The fabrication of MOSFETs with gate lengths of this order poses two major problems: how to fabricate such small‐geometry gate electrodes, and how to fabricate the ultrashallow source and drain junctions required. Two special techniques are used to overcome these problems: a resist‐thinning process using isotropic oxygen plasma ashing for the fabrication of the gate electrodes, and a process of solid‐phase diffusion from phosphorus‐doped silicated‐glass gate sidewalls for fabrication of the source and drain junctions. The resulting 40‐nm gate electrodes and ultrashallow 10‐nm junctions have an adequate impurity concentration and have been shown to function successfully. It has been confirmed that these 40‐nm gate‐length n‐MOSFETs have good electrical characteristics at room temperature. Certain details of small‐geometry MOSFET electrical characteristics are studied using these devices.

Recently, direct tunneling gate oxide MOSFETs have shown the potential of enabling extremely high RF performance in analog applications. An excellent cutoff frequency of more than 150 GHz was reported at a gate length of less than 0.1 /spl mu/m. In this paper, RF noise characteristics of the MOSFETs are reported in detail. The gate oxide thickness and supply voltage dependencies were investigated. In addition, NMOS LNA (low noise amplifier) circuits made with 1.5 nm gate oxide MOSFETs were evaluated for the first time. Good RF analog circuit operation with very low noise and high gain was confirmed.

A nitrogen-doped NiSi technique has been developed for deep submicron CMOS. It was found that the nitrogen suppresses oxidation of the silicide film, resulting in significantly reduced roughness at the interface between silicide and the Si substrate. It was confirmed that, as a consequence, the leakage current through the silicided ultra-shallow diffused layer was significantly suppressed. The nitrogen-doped NiSi film has the advantage of containing large single crystal grains, and this reduces the resistivity of the film. The nitrogen-doped NiSi technique was used to fabricate 0.15 /spl mu/m CMOS devices, and these devices, both n- and p-MOSFETs, exhibited very high Id and gm values without leakage current.