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Herein, the line-edge roughness (LER)-induced random performance variation–immune effect of metal–interlayer–semiconductor (MIS) source/drain (S/D) in 7 nm n-type Ge (n-Ge) junctionless field-effect transistors (JLFETs) were investigated by 3-D TCAD simulations. Compared to the device without MIS S/D, the n-Ge JLFET with MIS S/D could effectively reduce the Ge fin doping concentration while maintaining the performance. It was demonstrated analytically that the reduced Ge fin doping concentration of the device with MIS S/D, compared to the device without MIS S/D, decreased the LER-induced random performance variations of the n-Ge JLFET; the standard deviations were reduced to ~0.0318 V for Vth (reduced by ~51.6%), 4.89 ×10−6 A/μm for Ion (reduced by ~92.1%), 1.44 ×10−9 A/μm for Ioff (reduced by ~93.7%), 1.27 mV/dec for SS (reduced by ~23.1%), and ~5.40 mV/V for drain-induced barrier lowering (DIBL) (reduced by ~30.8%). In addition, LER-induced random performance variation was investigated in terms of scaling down fin widths. The results provided critical insight into the variability reduction of the 7 nm n-Ge JLFETs. [ABSTRACT FROM AUTHOR]

We present a universal metal–interlayer–semiconductor (MIS) contact model to demonstrate the effect of Fermi-level unpinning, considering both the extrinsic interface-state density (${D} _{\textsf {it}}$) and the density of metal-induced gap states (${D} _{\textsf {MIGS}}$) at the semiconductor surface. Previous studies on MIS contact modeling have quantified only the impact of ${D} _{\textsf {MIGS}}$ on Fermi-level pinning. However, the extrinsic interface states such as interface traps and local vacancies significantly affect the contact resistivity degradation in MIS contacts. Moreover, field emission (FE) and thermionic FE (TFE) current density models in MIS contact are described in detail, for the extraction of the specific contact resistivity ($\rho _{c}$). The physical validity of the proposed model is demonstrated by comparing its calculated $\rho _{c}$ with those obtained in prior experimental studies employing a GaAs substrate (Ti/ZnO/n-GaAs and Ti/TiO2/n-GaAs). The $\rho _{c}$ values for the MIS contacts are also evaluated with various ${D} _{\textsf {it}}$ levels and the interlayers. This model is promising for the development of a comprehensive next-generation MIS contact for the sub-10-nm complementary metal–oxide–semiconductor technology. [ABSTRACT FROM AUTHOR]

In this paper, the effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal–semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (${I}_{ \mathrm{OFF}}$) and extremely low on-state current (${I}_{ \mathrm{ON}}$). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, ${I}_{ \mathrm{OFF}}$ of $9.42 \times 10^{-10}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{ON}}$ of $6.09 \times 10^{{-4}}$ A/ $\mu \text{m}$ , and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node. [ABSTRACT FROM AUTHOR]

The impact of process-induced random dopant fluctuation (RDF)-induced threshold voltage ( V\mathrm{ th} ) variation on the performance of 7-nm n-type germanium (Ge) FinFETs with and without a metal–interlayer–semiconductor (MIS) source/drain (S/D) structure is investigated using 3-D TCAD simulations. In order to reduce the RDF-induced V\mathrm{ th} variation, an MIS S/D structure with a heavily doped n-type zinc oxide (ZnO) interlayer is used in the S/D region of the Ge FinFET. Thus, without performance degradation, the Ge FinFET with an MIS S/D structure achieves approximately threefold reduction in the RDF-induced V\mathrm{ th} variation (versus without an MIS S/D structure). The impact of various fin parameters (i.e., fin height and fin width) on the RDF-induced V\mathrm{ th} variation is also investigated. It is noteworthy that variation is suppressed as the fin height (fin width) increases (decreases). [ABSTRACT FROM AUTHOR]

A metal nitride-interlayer-semiconductor source/drain (MN-I-S S/D) model is newly proposed to investigate the effect of tantalum nitride (TaN) on the specific contact resistivity ( \rho c ) of an MN-I-S S/D with an undoped interlayer (undoped-IL) or a heavily doped IL (n+-IL) in sub-10-nm n-type Ge FinFETs. In this model, the workfunction variation of TaN was considered following the Rayleigh distribution. Compared with MN-I-S structures with an undoped-IL, structures with an n+-IL generate much lower \rho c values (i.e., $\sim 2 \times 10^{{\mathbf {-9}}}\Omega \cdot \text {cm}^{2}$ ) and are less prone to variation. In addition, the impact of \rho c variation on device performance is investigated using 3-D technology computer aided design simulation for undoped or heavily doped ILs in MN-I-S S/D structures. MN-I-S S/Ds with an n+-IL can achieve much lower current variation and a higher ON-state drive current. [ABSTRACT FROM PUBLISHER]

Abstract: We investigate phosphorus in-situ doping characteristics in germanium (Ge) during epitaxial growth by spreading resistance profiling analysis. In addition, we present an accurate model for the kinetics of the diffusion in the in-situ process, modeling combined growth and diffusion events. The activation energy and pre-exponential factor for phosphorus (P) diffusion are determined to be 1.91 eV and 3.75 × 10−5 cm2/s. These results show that P in-situ doping diffusivity is low enough to form shallow junctions for high performance Ge devices. [Copyright &y& Elsevier]

We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n+-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal-semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S S/D structure with n+-IL provides much lower contact resistivity, resulting in \sim 5 \times lower contact resistivity than 1\times 10^{\mathrm {\mathbf {-8 }}}~\Omega - \mathrm{cm}^{\mathrm {\mathbf {2}}}$ , specified in International Technology Roadmap for Semiconductors. In addition, we found that the M-I-S structure with n+-IL remarkably suppresses the sensitivity of contact resistivity to S/D doping concentration. [ABSTRACT FROM AUTHOR]