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The epitaxial growth of Si and SiGe layers on (1 1 0) Si substrates using UHV-CVD is studied with comparing that on (1 0 0) substrates. It is revealed that, while the growth rate on (1 1 0) surfaces is quite lower than that on (1 0 0) surfaces, the Ge content of SiGe is the same between (1 0 0) and (1 1 0) surfaces, meaning that the ratio of decomposition yields of source molecules for Si and Ge are same in both the (1 0 0) and (1 1 0) substrates. This characteristic is expected to lead to the epitaxial growth of SiGe films with uniform Ge content over the three-dimensional patterned structure, which can be utilized for vertical FET and Fin-FETs. Actually, it has been experimentally confirmed that the SiGe films grown over trench structures has a uniform Ge content. [Copyright &y& Elsevier]

Abstract: Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, the recent mobility enhancement technologies including application of strain and new channel materials such as SiGe, Ge and III–V materials are reviewed. These carrier transport enhancement technologies can be classified into three categories; global enhancement techniques, local enhancement techniques and global/local-merged techniques. We present our recent results on MOSFETs using these three types of the technologies with an emphasis on the global strained-Si/SiGe/Ge substrates and the combination with the local techniques. Finally, issues on device structures merged with III–V materials are briefly described. [Copyright &y& Elsevier]

Abstract: We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels. [Copyright &y& Elsevier]