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Kinetic inductance is an important property of carbon nanotubes (CNTs) in high-frequency applications. However, disagreements exist in whether the kinetic inductance of CNTs is present in the diffusive transport regime. In this paper, we fabricated the horizontally aligned multiwalled nanotube (MWNT) arrays on silicon substrates and investigated the inductance properties of the MWNT arrays with different lengths using direct current and radio frequency characterizations. The experimental results show that the electron transport in the CNT arrays is diffusive and that the value of the kinetic inductance is proportional to the length of the CNT arrays. We have experimentally validated that the kinetic inductance theory is applicable to CNTs in the diffusive transport regime. This paper could quell the existing disagreements about the kinetic inductance and provide insights to the potential applications of CNTs as interconnects and on-chip inductors. [ABSTRACT FROM AUTHOR]

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized. [ABSTRACT FROM AUTHOR]

A local silicon-gate carbon nanotube field effect transistor (CNFET) configuration has been proposed and implemented for integration purpose. By combining the advantages of in situ carbon nanotube growth technology and the silicon-on-insulator technology, we have realized the CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the complementary-metal-oxide-semiconductor (CMOS) process. The CNFETs show up-to-date electrical performance. The scaling effect of gate oxide is also explored. This configuration makes CNFET a step closer to the CMOS integrated circuit application. [ABSTRACT FROM AUTHOR]