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This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential. [ABSTRACT FROM AUTHOR]

To get a better insight into the vertical leakage mechanism of GaN-on-Si, the carrier transport from n+, n, p+, and p-Si(111) substrates through the AlN nucleation layer was investigated. A plateau in the current-voltage curve was found only for the AlN/p-Si heterojunction due to depletion of the p-Si substrate. Detailed study illustrated that it was the leaky AlN that cannot effectively block the increasing amount of electrons in the inversion layer at the interface and triggered the depletion. Temperature-dependent characterization suggested that the forward vertical leakage mechanism of AlN/Si could be explained sequentially by Ohm’s law, space-charge-limited conduction, variable-range hopping, and trap-assisted tunneling. A model involving shallow donor traps, interface traps, and deep level traps was proposed to explain the leakage characteristics. This paper shows that the carrier concentration of the Si substrates strongly impacts the vertical leakage characteristics, and also that the carrier transport from the Si substrate through the AlN nucleation layer is heavily influenced by traps. [ABSTRACT FROM AUTHOR]

Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (silicon-on-insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electron mobility transistors with a gate width of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size. [ABSTRACT FROM AUTHOR]

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum. [ABSTRACT FROM AUTHOR]

Au-free GaN-based metal–insulator–semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al2O3-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si3N4 and Al2O3. The Si3N4 layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al2O3 layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600~V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <1~\Omega\cdotmm. The devices show high maximum output current density (>0.4~A/mm); and low gate and drain leakage (<10^-10~A/mm). The maximum pulsed mode drain–source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m \Omega\cdotcm^2. [ABSTRACT FROM AUTHOR]

The ESD robustness of GaN-on-Si Schottky diodes is investigated using on-wafer HBM and TLP. Both forward and reverse diode operation modes are analyzed as a function of device geometry, which strongly impact the corresponding failure mechanism. In forward mode, the anode-to-cathode length reduction and the total device width increase are beneficial for ESD robustness; however, in reverse mode, the ESD robustness does not depend on the total device width and saturates at around 400 V for medium and long anode-to-cathode lengths. The corresponding failure mechanisms are respectively attributed to the current distribution and Si substrate breakdown under forward and reverse mode ESD stresses. [ABSTRACT FROM PUBLISHER]

Abstract: In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high growth rate and high electrically-active doping levels of arsenic. The resultant devices show improvement of open-base breakdown voltage and no degradation of cutoff frequency with incorporation of a Ge spike in the monoemitter. [Copyright &y& Elsevier]

This paper investigates the influence of the electrode spacing, chamber pressure, total gas flow, and H2 dilution on the crystallinity, resistivity, uniformity, and Stress of polycrystalline silicon-germanium (poly-SiGe) films grown by plasma-enhanced chemical vapor deposition (PECVD). Boron-doped PECVD SiGe films of 1.6 tim thick are deposited on 400 nm chemical vapor deposition layers from SiH4, GeH4, and B2H6 precursors. The microstructure is verified by transmission electron microscopy and by X-ray diffraction. It was discovered that for constant temperature and deposition rate, the PECVD SiGe microstructure changes from completely amorphous to polycrystalline by increasing the electrode spacing and pressure due to reduced ion bombardment. A process window of an electrode spacing and pressure for the PECVD poly-SiGe deposition is thus identified based on a sheet resistance mapping method. Increasing the total gas flow dramatically improves the within-wafer crystallinity variation and further reduces the resistivity. Increasing the H2 flow during PECVD shifts the Stress from -51 to 17 MPa and further reduces the crystallinity variation over the wafer. In addition, the effect of changing the SiH4 to GeH4 ratio and the in situ boron doping by adding B2H6 is also investigated. The findings in this paper are expected to facilitate the use of poly-SiGe in the above complementarv metal oxide semiconductor (CMOS) microelectromechanical system (MEMS) applications. [ABSTRACT FROM AUTHOR]

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs. [ABSTRACT FROM AUTHOR]

Presents a study which measured boron and germanium (Ge) concentration profiles in rapid thermal and furnace annealed silicon (Si)-doped, epitaxial layers. Experimental procedure; Mathematical model for boron diffusion; Results and discussion; Conclusion.

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (R \(_{\mathrm {{on}}}\) ) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) R \(_{\mathrm {{on}}}\) -increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C–140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the R \(_{\mathrm {{on}}}\) -increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length. [ABSTRACT FROM AUTHOR]

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded \Si3\N4\/ \Al2\O3 bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance Ron, sp of 2.9 \m\Omega\cdot\cm^2. The off-state drain leakage at 600 V is 7 \mu\A. We show robust gate dielectrics with a large gate bias swing. [ABSTRACT FROM PUBLISHER]

III-Nitride materials are very promising to be used in next-generation high-frequency power switching applications. In this letter, we demonstrate the performance of normally off AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs) using a boost-converter circuit. The figures of merit of our large (57.6-mm gate width) GaN transistor are presented: RON \ast QG of 2.5 \Omega\cdot\nC is obtained at VDS = \140\ V. The switching performance of the GaN DHFET is studied in a dedicated high-frequency boost converter: both the switching times and power losses are characterized. We show converter efficiency values up to 96.1% at 500 kHz and 93.9% at 850 kHz at output power of 100 W. [ABSTRACT FROM AUTHOR]

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double-heterostructure FETs on a Si (111) substrate with only 2-\mu\m-thick AlGaN buffer. Before local Si removal, VBD saturates at \sim700 V at a gate–drain distance (LGD) \geq \8\ \mu\m. However, after etching away the substrate locally, we measure a record VBD of 2200 V for the devices with LGD = \20\ \mu\m . Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties. [ABSTRACT FROM AUTHOR]

In this letter, we present a novel approach to enhance the breakdown voltage (VBD) for AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs), grown by metal-organic chemical vapor deposition on Si (111) substrates through a silicon-substrate-removal and a layer-transfer process. Before removing the Si substrate, both buffer isolation test structures and DHFET devices showed a saturation of VBD due to the electrical breakdown through the Si substrate. We observed a VBD saturation of 500 V for isolation gaps larger than 6 µm. After Si removal, we measured a VBD enhancement of the AlGaN buffer to 1100 V for buffer isolation structures with an isolation gap of 12 µm. The DHFET devices with a gate-drain (LGD) distance of 15 µm have a VBD > 1100 V compared with ~300 V for devices with Si substrate. Moreover, from Hall measurements, we conclude that the substrate-removal and layer-transfer processes have no impact on the 2-D electron gas channel properties. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents an analytical method to simultaneously determine the complex characteristic impedance and the pad parasitics of transmission lines fabricated on silicon. The method uses experimental two-port network parameters of two lines differing in length without the need of a reflect standard such as that required in TRL-like formulations. Furthermore, the losses associated with the silicon substrate are accurately considered using the experimentally determined complex propagation constant of the lines and three different configurations for the pad parasitics can be assumed. When using the extracted parameters in a model to represent transmission lines, excellent agreement between simulated and experimental data was achieved up to 50GHz even for lines with lengths different to those used in the determination process. [Copyright &y& Elsevier]