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This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

Presents a study that investigated low-termperature reaction of thin-film platinum with silicon. Sheet resistance measurement of silicide formation sequence; Use nitrogen furnace; X-ray diffraction analysis.

Studies the capability of using platinum and platinum-silicon in the ion implantation through metal or metal silicide technique. Procedure of the experiment; Measured electrical characteristics of the sample; Results of the leakage current analysis; Conclusion.

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology. [ABSTRACT FROM PUBLISHER]

Presents information on a study which examined proposed mechanisms on the role of fluorine in the thermal stability of silicide/silicon structures. Background of the study; Methodology of the study; Results and discussion.

Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications. [ABSTRACT FROM PUBLISHER]

The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunneling orientation was proposed. The ETL structure performs more favorably than does the traditional lateral tunnel FET structure in an all-silicon device. By using low bandgap materials in the ETL, the ON-state BTBT current increases and an extremely low intrinsic OFF-state current is maintained because of the small low bandgap junction area. The onset voltage of the bipolar BTBT can also be postponed using ETL band engineering. The optimized parameters of the Six\rm Ge1\-{\rm x} ETL tunnel FET structure increase the ON-state current 10^7\--10^8 times compared with that of the traditional lateral silicon tunnel FET. The minimal subthreshold swing (SS) and ON/OFF current ratio also improve, the SS decreases from 47 mV/decade to 29 mV/decade, and the ON/OFF current ratio increase from 10^5 to 10^10. In this paper, the effects of the ETL parameters on device performance are discussed in detail. [ABSTRACT FROM PUBLISHER]

The effects of extreme-ultraviolet (EUV)-irradiation-induced damage on the characteristics of a silicon–oxide–nitride–oxide–silicon (SONOS) memory device are investigated. After EUV irradiation, changes in the memory window and program/erase speed indicate the generation of positive charges and new traps. Retention performance degrades after high-dose irradiation, which indicates that the tunneling layer is damaged. Endurance performance degrades severely because the damage in the blocking oxide results in serious electron back injection after cycling operations. These defects cannot be recovered after 600 ^\circ\C annealing. It is recommended that in-process high-dose EUV irradiation on a SONOS stack after a front-end-of-line process should be avoided. [ABSTRACT FROM AUTHOR]

High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) using hafnium dioxide (\HfO2) as gate dielectric is successfully fabricated for the first time. The excellent short-channel characteristics are attributed to the high- \kappa gate dielectric, ultrathin poly-Si NW channel thickness, and omega-shaped gate structure. The record high driving capability of 549 \mu \A/\mu\m results from the ultrashort gate length (LG), thin equivalent oxide thickness, and Ni silicide metal source/drain. This letter reveals the opportunity of high-performance poly-Si TFT circuits for system-on-panel and 3-D integrated circuit (3-D IC) applications. [ABSTRACT FROM PUBLISHER]