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In this paper the reverse gated-diode technique is examined for determining the carrier generation lifetime and surface generation velocities in thin-film silicon-on-insulator (SOI) devices. Using the modeling of the gate-controlled volume and surface generation components, SOI-specific aspects of the technique are highlighted. A reliable approach for extracting generation parameters in thin-film SOI devices from reverse gated-diode measurements is proposed and validated for high temperatures. The technique is demonstrated on the devices fabricated on two different SOI materials (zone-melt recrystallized and Unibond®), as examples of volume- and surface-dominated generation current behaviors. Finally, the technique is applied to characterize Unibond® SOI devices operating in the temperature range 100–300 °C to demonstrate the model and technique applicability at high temperatures. [ABSTRACT FROM AUTHOR]

Miniaturized humidity sensors combined with ZigBee transceiver and efficient data processing offer a powerful system for the monitoring of human breath. Every 10 ms, the expiration/inspiration phase is transmitted, allowing a medical diagnosis as efficient as required by the application. For the sensing system, a micro interdigitated capacitor, covered with a dense hydrophilic alumina layer, is connected to a capacitance-to-frequency circuit interface. A customized nasal canula-prototype embeds the microsystem underneath the patient's nostrils while offering cabling until the belt-fixed radio transceiver. The fast data processing, executed in a mini notebook process unit, gives to the medical staff a live broadcast of the patient's respiratory rate. In order to improve the size and the functionality of our sensing module, novel techniques for processing complementary metal oxide semiconductor (CMOS) in Silicon-on-Insulator (SOI) technology now allow for the construction of microsensors and CMOS circuits together on the same chip. These sensors consume extremely low power, of the order of 0.1 μW, present high sensitivity, occupy small chip area (1.25 mm2) and offer the prerequisite platform for a large variety of new sensors. [ABSTRACT FROM PUBLISHER]

Abstract: This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface, as a function of the gate length and substrate bias, on both the front threshold voltage () and subthreshold slope (S), for sub-32nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145nm (UTB) or thin 11.5nm (UTB2). This study details for the first time, the important impact of the substrate/BOX interface regime variations with gate length from 1μm down to 25nm, substrate bias and BOX thickness together, on the mean channel position into film and its related impact on the electrical parameters and S. Experimental results and conclusions are also completed and enlightened by ATLAS simulations and analytical modeling. [Copyright &y& Elsevier]

Two strategies to enhance transistor performance in SOI technology without increasing the operating voltage are compared. The first option is the use of the self-cascode transistor, a series connection of two conventional FD SOI MOSFETs which, with an appropriate choice of sizes, work as a single transistor with reduced output conductance. The second option is the use of the graded-channel (GC) SOI MOSFET, consisting of a modification of the fully-depleted (FD) SOI MOSFET which leads to better performance of the device in saturation. The paper shows the existing analogy between the operation of self-cascode and GC SOI transistors. The comparison between both strategies is carried out on the basis of simulations with the University of Florida SOI (UFSOI) model and experimental measurements. The area consumed by a self-cascode SOI transistor is estimated to be 10 times larger than that of a GC SOI transistor for the same improvement in output conductance. Experimental results validate the model used for the GC SOI device and also provide numerical quantification of output resistance increase in both configurations. [ABSTRACT FROM AUTHOR]

An investigation of radiation effect on edgeless accumulation mode (AM) p-channel and fully-depleted enhancement mode (EM) n-channel MOSFETs, fabricated on UNIBOND silicon on insulatior wafers (SOI), is presented in the paper. Characterization of trapped charge in the gate and buried oxides of the devices was performed by measuring only the front-gate transistors. It was revealed that the irradiation effect on EM n-MOSFET is stronger than that on AM p-MOSFET. Radiation-induced positive charge in the buried oxide proved to invert back interface what causes back channel creation in EM n-MOSFET but no such effect in AM p-MOSFET has been not observed. The effect of improving the quality of both interfaces for small irradiation doses is demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances, is firstly described regarding its process and layout parameters. Then the concept of the graded-base bipolar transistor is introduced. This device presents significantly improved output characteristics while preserving standard current gain and CMOS process compatibility. Measurements and simulations are used to demonstrate the improvements of the breakdown voltage and the Early voltage of the bipolar device. [Copyright &y& Elsevier]

Described are the design and characterisation of an ultra-low-power temperature level detector (TLD) and temperature sensor based on a silicon-on-insulator (SOI) CMOS integrated circuit (IC) for harsh environment applications. Since this IC is mainly for harsh environment applications (e.g. high temperatures and radiations), it has been designed and manufactured using the 1 µm high-temperature SOI-CMOS technology provided by X-FAB. The measured power dissipation of the TLD circuit is 9 µW at a supply voltage of 5 V and temperature of 27 °C, according to the measurement results of the manufactured design. [ABSTRACT FROM AUTHOR]

The origin of the low-frequency noise in graded-channel silicon-on-insulator nMOSFET is studied as a function of the back-gate bias at a low drain-to-source bias. It is shown that an excess noise peak that is correlated with the peak in the transconductance can be observed. This excess noise is due to a generation—recombination component in the low-frequency range, which is suppressed when the back gate is in accumulation mode. [ABSTRACT FROM AUTHOR]

This paper investigates the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs. It is shown for the first time that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance. It is demonstrated that the appearance of these transitions, the position and amplitude of which strongly depend on the substrate doping, is caused by the variation of the potential at substrate-buried oxide interface, which we call the Floating Effective Back-Gate (FEBG) effect. A first-order small-signal equivalent circuit is proposed to support our observations. [ABSTRACT FROM AUTHOR]

The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs. [ABSTRACT FROM AUTHOR]

This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation mode and under high temperatures of operation, independently of the anode voltage. The obtained results show that the doping concentration of the intrinsic region has influence on the sensitivity of the diodes: the larger the doping concentration, the smaller the IDR. Furthermore, the photocurrent and dark current present lower values as the silicon film thickness is decreased, resulting in a further increase in the illuminated to dark ratio. [ABSTRACT FROM AUTHOR]

Abstract: Even in fully-depleted (FD) SOI MOSFETs, the floating-body potential variations may lead to strong transient effects on the current characteristics. A physics-based model, enabling the fast computing of the potential variation with time, is proposed in this paper. The model is validated, for a wide range of technological parameters and biases, by 2D numerical simulations. This model reproduces the experimental data and clarifies the physics mechanisms responsible for the transient variations of gate and drain currents. Relevant applications in the field of EEPROM and capacitorless floating-body DRAM memories are addressed. [Copyright &y& Elsevier]

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, I d , and maximum transconductance, g m_max , values are demonstrated. Current gain cutoff frequency, f T , increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space). [ABSTRACT FROM AUTHOR]

This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225 °C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed. [ABSTRACT FROM AUTHOR]

Highlights: [•] Parasitic elements significantly impact the RF performances of UTBB devices especially in short channel devices. [•] UTBB devices are capable to meet the ITRS requirement for f T provided the parasitic elements are well tailored. [•] With appropriate configuration, ADG regime is expected to provide improved RF figures of merit. [Copyright &y& Elsevier]

Abstract: In this paper, we investigate the transconductance-to-current ratio (gm /ID ) methods for the threshold voltage extraction using two popular threshold voltage criteria applicable to advanced bulk and SOI MOSFETs, namely: the condition of the maximum of the second derivative of the inversion charge and of the equality of the drift and diffusion drain current components. Using analytical modeling, we derive the first-order electrical parameters matching these two physical conditions and show that in the ideal MOSFET they do not coincide. The first corresponds to the point on the gm /ID versus gate voltage (Vg ) curve where d(gm /ID )/dVG exhibits a minimum and where the ratio of gm /ID to its maximum value is equal to 2/3, whereas the second is met at the point where this ratio equals 1/2. The gm /ID methods for the VTH extraction using the above two criteria and their correlation with other methods are discussed. Since our modeling is based on the unified charge control model, its predictions are expected to be valid for both bulk and SOI MOSFETs. Experimental and simulation results for advanced SOI MOSFETs are used to validate modeling derivations and clarify practical applicability and limitations of the gm /ID methods. [Copyright &y& Elsevier]

Abstract: The frequency variation of the output conductance in ultra-thin body with ultra-thin BOX (UTBB) SOI MOSFETs without a ground plane is studied through measurements and two-dimensional simulations. Two effects causing the output conductance variation with frequency, namely self-heating and source-to-drain coupling through the substrate, are discussed and qualitatively compared. Notwithstanding the use of ultra-thin BOX, which allows for improved heat evacuation from the channel to the Si substrate underneath BOX, a self-heating-related transition clearly appears in the output conductance frequency response. Furthermore, the use of an ultrathin BOX results in an increase of the substrate-related output conductance variation in frequency. As a result, the change in output conductance of UTBB MOSFETs caused by the substrate effect appears to be comparable and even stronger than the change due to self-heating. [Copyright &y& Elsevier]

Abstract: In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150–220GHz. Effect of operation regime, substrate bias, channel width and high temperature (up to 250°C) on analog figures-of-merit (FoM) are analyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented. [Copyright &y& Elsevier]

Abstract: A comparative investigation of high-energy neutrons effect on strained and non-strained devices with different geometries is presented. Both single-gate planar and multiple-gate (MuG) silicon-on-insulator (SOI) devices are considered. Device response to the neutron irradiation is assessed through the variations of threshold voltage and transconductance maximum. The difference between strained and non-strained device response to the high-energy neutrons exposure is clearly evidenced. The reasons for such a difference are discussed. Analysis of the experimental results allows for suggesting that strain relaxation is one of the probable causes. [Copyright &y& Elsevier]

Abstract: In this paper, we develop a model to simulate the single event transient (SET) phenomena in LDMOS-SOI devices. 3D simulations and compact model are coupled in order to reproduce the current pulse in LDMOS-SOI device generated by an ion strike through the different device locations, at various biases and temperatures. Obtained results allow for identifying the effects to be taken into account for accurate transient description. Furthermore, comparison with SET observed in Partially Depleted SOI MOSFET reveals that LDMOS device exhibits lower drain current upset whereas larger recovery time, which results in higher collected charge. [Copyright &y& Elsevier]

Abstract: This paper presents a compact model for partially depleted SOI MOSFETs, which allows for describing the total dose and the single event effects. It incorporates both temperature and charge buildup effects during irradiation. The developed model is implemented in a Verilog-A module. This original module can be coupled with Spice simulator, allowing for faster (time efficient) circuit simulations (comparing to numerical physical ones) at different bias, linear energy transfer (LET), buildup charges and temperatures. Better efficiency and flexibility than the standard current source method is achieved thanks to the direct link between the module and the irradiated transistor through the partially depleted SOI CMOS body contact terminal. Mixed-mode simulations of a partially depleted SOI CMOS D flip–flop at different conditions (biases, LETs, temperatures, buildup charge densities) are used in order to validate the model. Well-known high tolerance of SOI circuits to a single event effects is demonstrated to be degraded with the total dose increase (appearing as a positive charge buildup), which is further enhanced at higher temperatures. [Copyright &y& Elsevier]

Abstract: This paper presents a detailed experimental study of the electrical characteristics of long-channel ultra-thin body SOI MOSFETs with standard and thin buried oxides and high-k gate dielectric, using an analysis of the transconductance, gate-to-channel capacitance and mobility behaviors at different back-gate biases. The emphasis is on the evolution of the effective mobility when shifting the conduction channel in the film from front to back interface, and on the comparison between the two BOX thicknesses. It is found that the back-channel mobility significantly exceeds the front-channel mobility, which is presumably related to strongly different Coulomb scattering at the two interfaces, being in agreement with previously published experimental studies. Furthermore, the back-channel mobility is found to be the same for thick and thin BOX. This strongly suggests that BOX thinning does not degrade the quality of the back interface. The observed effect of much higher back-channel mobility, which is retained for the thin BOX, could find application for the additional improvement of the device performance, when adjusting the threshold voltage via back-gate bias. Adequate mobility interpretation is then required as a varying combination of front and back-channel mobilities. [Copyright &y& Elsevier]

Abstract: Silicon-on-insulator (SOI) technology is emerging as a major contender for heterogeneous microsystems applications. In this work, we demonstrate the advantages of SOI technology for building thin film sensors on membranes as well as three-dimensional (3D) surface micromachined sensors and actuators. The flatness and robustness of the thin membrane as well as the self-assembling of 3D microstructures rely on the chemical release of the microstructures and on the control of the residual stresses building up in multilayered structures undergoing a complete thermal process. The deflection of multilayered structures made of both elastic and plastic thin films results from the thermal expansion coefficient mismatches between the layers and from the plastic flow of a metallic layer. The proposed CMOS-compatible fabrication processes were successfully applied to suspended sensors on thin dielectric membranes such as gas-composition, gas-flow and pressure sensors and to 3D self-assembled microstructures such as thermal and flow sensors. [Copyright &y& Elsevier]

Abstract: The fully-depleted version of the SOI four-gate transistor (G4-FET) is introduced and its characteristics are systematically investigated. It is shown that the thinning-down of the silicon film promotes vertical coupling between the front and the back gates while mitigating the horizontal coupling between the lateral gates. As a consequence the direct influence of the lateral junction-gates on the body potential distribution is reduced. However, by biasing the back interface in inversion the junction-gates can indirectly modulate the body potential. This provides a very efficient control of the front-channel conduction parameters – such as threshold voltage, subthreshold swing and transconductance – by the junction-gates regardless the device width. The experimental results are clarified by 3-D device simulations and analytical modelling. [Copyright &y& Elsevier]

Abstract: In this paper, a novel method for the fabrication of planar double-gate (DG) MOS devices is presented. Successfully fabricated single-gate and DG MOSFET devices on the same wafer have been fully characterized and their electrical performances compared. The planar DG devices were fabricated using wafer bonding over pre-patterned cavities. Preliminary electrical characterization results show that the built planar DG devices exhibit the expected theoretical performances. We will also show the flexibility of this method in fabricating other devices besides planar DG and the possibility of changing the various materials used for the buried insulator layer. It is demonstrated that this fabrication method is a very promising and viable method for future technology application in fabricating novel devices. [Copyright &y& Elsevier]

The purpose of this paper is to completely describe the low and high frequency performance including microwave noise parameters of 0.25 μm fully depleted (FD) silicon-on-insulator (SOI) devices and to compare the noise performance with 0.25 μm partially depleted (PD) devices. These FD devices present a state of the art NFmin of 0.8 dB and high Gass of 13 dB at 6 GHz, at Vds=0.75 V, Pdc<3 mW at 80 μm total gate width. A extrapolated maximum oscillation frequency of about 70 GHz has been obtained at Vds=1 V and Jds=100 mA/mm. [Copyright &y& Elsevier]

Abstract: Tracking for particle physics instrumentation in SOI technology (TRAPPISTe-1) is an R&D project to study the feasibility of manufacturing a monolithic active pixel sensor (MAPS) in silicon on insulator (SOI) technology. The first prototype of this series of sensors has been designed with a 2μm SOI CMOS technology available in UCL, Louvain-la-Neuve. Simulations are presented for this prototype. Leakage measurements have been done on a photovoltaic cell, manufactured in the same process on a low-resistivity substrate. As a next step, a high-resistivity demonstrator will be designed. [Copyright &y& Elsevier]