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In recent years, DPDK (Data Plane Development Kit, a data plane development tool set provided by Intel, focusing on high-performance processing of data packets in network applications), one of the high-performance packet I/O frameworks, is widely used to improve the efficiency of data transmission in the cluster. But, the busy polling used in DPDK will not only waste a lot of CPU cycles and cause certain power consumption, but also the high CPU usage will have a great impact on the performance of other applications in the host. Although some technologies, such as DVFS (dynamic voltage and frequency scaling, which is to dynamically adjust the operating frequency and voltage of the chip according to the different needs of the computing power of the application running on the chip, so as to achieve the purpose of energy saving) and LPI (low power idle, a technology that saves power by turning off the power of certain supporting circuits when the CPU core is idle), can reduce power consumption by adjusting CPU voltage and frequency, they can also cause performance degradation in other applications. Using thread sleep technology is a promising method to reduce the CPU usage and power consumption. However, it is challenging because the appropriate thread sleep duration cannot be obtained accurately. In this paper, we propose a model that finds the optimal thread sleep duration to solve the above challenges. From the model, we can balance the thread CPU usage and transmission efficiency to obtain the optimal sleep duration called the transmission performance threshold. Experiments show that the proposed models can significantly reduce the thread CPU usage. Generally, while the communication performance is slightly reduced, the CPU utilization is reduced by about 80%.

A Bloatware is software that offers limited functionality at the expense of RAM and CPU cycles. The proliferation of bloatware in Android devices depletes not only hardware resources but also makes them more vulnerable to security and privacy threats. A consumer pays in terms of battery, wasted space, privacy and security compromises. These applications have also been known to be used for computer control and data collection. This, however, has some disadvantages. These bloatwares are often mounted in the device partition, making it difficult to remove them without root access. Each app that has been uninstalled can be reinstalled using the same program. The existing methods of rooting the device is complex and may render the device inoperable if not done cautiously. The proposed “Android Debloater and Optimizer” uninstall such bloatware without the risk of rooting your device.

In this paper, we propose ALICE Connex, a prototype of a volunteer mobile computing platform for the ALICE experiment. The platform adopts the “volunteer computing” concept on mobile devices. Untapped computing power of smartphones can be aggregated and exploited to help in the calibration of the ALICE’s Time-of-Flight (TOF) particle detector. ALICE Connex is built based on the Berkeley Open Infrastructure for Network Computing or BOINC, which is a well-known volunteer computing middleware. In addition, ALICE Connex will offer an outreach service to connect the ALICE experiment to the general public by a way of edutainment and volunteer computing allowing them to be a part of the big experiments at CERN.

Mobile computing is one of the largest untapped reservoirs in today's pervasive computing world as it has the potential to enable a variety of in situ, real-time applications. Yet, this computing paradigm suffers when the available resources—such as energy in the network, CPU cycles, memory, and I/O data rate—are limited. In this paper, the new paradigm of approximate computing is proposed to harness such potential and to enable energy-intensive mobile applications. A reduction in time and energy consumed by an application is obtained via closed-loop approximate computing by decreasing the amount of computation needed; such improvement, however, comes with the potential loss in accuracy. We present our framework on how approximation can be applied at different levels, namely, at the application level and the input data level. The effectiveness of the proposed closed-loop approach is validated both through extensive simulation and testbed experiments by comparing approximate versus exact-computation performance.

With the introduction of ultra-low latency SSDs, which complete I/O operations in a few microseconds, the use of polling is becoming an attractive solution for alleviating the overheads in interrupt-driven I/O completion. However, careful use of polling is essential because of its inherent CPU overhead. Hybrid polling, in which a timer-based sleep is inserted in the middle of polling, has recently been proposed to relieve the CPU overhead. However, there is still substantial headroom for further optimization to save CPU cycles. In this paper, we propose efficient hybrid polling scheme that minimizes the CPU cycles for polling without sacrificing the I/O latency. By considering I/O time characteristics of idle and busy storage devices, our scheme makes an appropriate sleep time decision that maximizes the I/O performance and minimizes the CPU cycles for polling. The proposed scheme is implemented in the Linux kernel and evaluated with various I/O workloads. The evaluation results show that whenever an SSD is heavily or lightly loaded, our scheme achieves I/O latency identical to that of classical polling while maintaining a low CPU utilization. Compared to the original hybrid polling, our scheme reduces CPU utilization by 5%–40% and provides faster I/O latency by up to 10%.

We propose a server-based approach to manage a general-purpose graphics processing unit (GPU) in a predictable and efficient manner. Our proposed approach introduces a GPU server that is a dedicated task to handle GPU requests from other tasks on their behalf. The GPU server ensures bounded time to access the GPU, and allows other tasks to suspend during their GPU computation to save CPU cycles. By doing so, we address the two major limitations of the existing real-time synchronization-based GPU management approach: busy waiting within critical sections and long priority inversion. We have implemented a prototype of the server-based approach on a real embedded platform. This case study demonstrates the practicality and effectiveness of the server-based approach. Experimental results indicate that the server-based approach yields significant improvements in task schedulability over the existing synchronization-based approach in most practical settings. Although we focus on a GPU in this paper, the server-based approach can also be used for other types of computational accelerators.

The explosive growth of data brings new challenges to the data storage and management in cloud environment. These data usually have to be processed in a timely fashion in the cloud. Thus, any increased latency may cause a massive loss to the enterprises. Similarity detection plays a very important role in data management. Many typical algorithms such as Shingle, Simhash, Traits and Traditional Sampling Algorithm (TSA) are extensively used. The Shingle, Simhash and Traits algorithms read entire source file to calculate the corresponding similarity characteristic value, thus requiring lots of CPU cycles and memory space and incurring tremendous disk accesses. In addition, the overhead increases with the growth of data set volume and results in a long delay. Instead of reading entire file, TSA samples some data blocks to calculate the fingerprints as similarity characteristics value. The overhead of TSA is fixed and negligible. However, a slight modification of source files will trigger the bit positions of file content shifting. Therefore, a failure of similarity identification is inevitable due to the slight modifications. This paper proposes an Enhanced Position-Aware Sampling algorithm (EPAS) to identify file similarity for the cloud by modulo file length. EPAS concurrently samples data blocks from the head and the tail of the modulated file to avoid the position shift incurred by the modifications. Meanwhile, an improved metric is proposed to measure the similarity between different files and make the possible detection probability close to the actual probability. Furthermore, this paper describes a query algorithm to reduce the time overhead of similarity detection. Our experimental results demonstrate that the EPAS significantly outperforms the existing well known algorithms in terms of time overhead, CPU and memory occupation. Moreover, EPAS makes a more preferable tradeoff between precision and recall than that of other similarity detection algorithms. Therefore, it is an effective approach of similarity identification for the cloud.

Cloud computing can leverage over-provisioned resources that are wasted in traditional data centers hosting production applications by consolidating tasks with lower QoS and SLA requirements. However, the dramatic fluctuation of workloads with lower QoS and SLA requirements may impact the performance of production applications. Frequent task eviction, killing and rescheduling operations also waste CPU cycles and create overhead. This paper aims to schedule hybrid workloads in the cloud data center to reduce task failures and increase resource utilization. The multi-prediction model, including the ARMA model and the feedback based online AR model, is used to predict the current and the future resource availability. Decision to accept or reject a new task is based on the available resources and task properties. Evaluations show that the scheduler can reduce the host overload and failed tasks by nearly 70%, and increase effective resource utilization by more than 65%. The task delay performance degradation is also acceptable.

Mobile edge computing (MEC) is a promising paradigm, which brings computation resources in proximity to mobile devices and allows the tasks of mobile devices to be offloaded to MEC servers with low latency. The joint problem of cooperative computation task offloading and resource allocation is a challenging issue. The joint problem of cooperative computation task offloading scheme and resource assignment in MEC is investigated in this paper, where the vertical cooperation among mobile devices, mobile edge server nodes and mobile cloud server nodes is considered, and the horizontal computation cooperation between edge nodes is considered as well. A computation offloading decision, cooperative selection, power allocation and CPU cycle frequency assignment problem is formulated. The objective is to minimize the latency while guaranteeing the constraint of transmission power, energy consumption and CPU cycle frequency. The formulated latency optimization problem is a nonconvex mixed-integer problem in general, which has binary variables and continuous variables. In order to solve the formulated problem. A joint iterative algorithm based on the Lagrangian dual decomposition, ShengJin Formula method, and monotonic optimization method is proposed. The CPU cycle frequence allocation is handled by the ShengJin Formula method due to the cubic equation of one variable about the CPU frequence allocation. The transmission power assignment is handled by the monotonic optimization method. In the algorithm convergence with different number of tasks, the proposed algorithm can quickly and effectively reach the convergence state and getting the minimum task execution delay. Numerical results demonstrate that the proposed algorithm outperforms the Full MEC, Full Local and Full Cloud three schemes in terms of execution latency.

Content based page sharing techniques improve memory efficiency in virtualized systems by identifying and merging identical pages. Kernel Same-page Merging (KSM), a Linux kernel utility for page sharing, sequentially scans memory pages of virtual machines to deduplicate pages. Sequential scanning of pages has several undesirable side effects---wasted CPU cycles when no sharing opportunities exist, and rate of discovery of sharing being dependent on the scanning rate and corresponding CPU availability. In this work, we exploit presence of GPUs on modern systems to enable rapid memory sharing through targeted scanning of pages. Our solution, Catalyst, works in two phases, the first where pages of virtual machines are processed by the GPU to identify likely pages for sharing and a second phase that performs page-level similarity checks on a targeted set of shareable pages. Opportunistic usage of the GPU to produce sharing hints enables rapid and low-overhead duplicate detection, and sharing of memory pages in virtualization environments. We evaluate Catalyst against various benchmarks and workloads to demonstrate that Catalyst can achieve higher memory sharing in lesser time compared to different scan rate configurations of KSM, at lower or comparable compute costs.

Multicore systems are prevalent now as high end computing systems for solving computationally complex problems. Energy consumed by these machines are enormous specially in instruction execution on the cores. It has been observed that if CPU cycle and latency cycle are properly managed, it is possible to save a good amount of energy. Dynamic voltage frequency scaling (DVFS) technique is often used to scale energy consumption at the cores. Job scheduling to the appropriate cores, in general, is an NP-hard problem. This work aims at effective use of DVFS technique at the instruction level and applies genetic algorithm, a popular meta-heuristics, for job scheduling at the appropriate core for optimal energy usage of multicore systems. Experimental results, on the benchmark data, exhibit that the proposed model is well scalable and energy efficient with acceptable performance tradeoff over other contemporary models.

International audience; In hybrid systems on chip (SoC) the algorithms must share limited resources classified as hardware (FPGA logic, memory and DSP blocks) and software (CPU cycle budget). Embedded applications are implemented with concurrent processes, which have to coexist. Therefore, the algorithm performance or precision is often downgraded to fit on a FPGA or to meet timing constraints. One of the solutions to relax these constraints is to reconfigure the SoC according to application requirements observed at runtime. Hardware (HW) reconfiguration can be performed by means of dynamic partial reconfiguration (DPR). Beyond the intrinsic DPR complexity, the most critical aspect is the implementation of the reconfiguration decision. Academic adaptive architectures are usually based on power / performance rules. Nevertheless such solutions are usually application agnostic and so cannot fully exploit the possible adaptation to the environment. So real-life systems require solutions to capture the knowledge of algorithm experts that can be leveraged at runtime to drive the reconfiguration decision according to application scenarios. In this paper we propose a methodology to design a reconfiguration controller based on quality of service (QoS) indicators to be specified by experts. This controller monitors the reconfigurable partitions (RP) and can make DPR decisions to optimize the global QoS. We illustrate our methodology in the Radar domain with a tracking system based on Kalman filters implemented on a Zynq Ultrascale+. This study highlights expected gains and obstacles, it presents the different strategies to cope with the issues and draws perspectives.

Cryptography is the art of converting readable data into indecipherable format using keys and vice versa. Strength of the algorithm is mainly measured by the complexity and CPU cycles required for cryptanalysis in the algorithm. But in an energy constrained environment like IoT, CPU intense complex algorithms will degrade the efficiency. Light-weight or cut down versions of symmetric and asymmetric cryptographies are found best suited for constrained environments. So accordingly, we in this paper have surveyed a lot of Hardware and software based Light-weight cryptographic algorithms in a quest to find the best suited cryptographic algorithm for signing and hashing blockchain in a constrained environment.

Volunteer computing is a distributed computing model in which individuals in possession of computing resources volunteer to provide them to a project. Owing to the availability of billions of computing devices all over the world, volunteer computing can help solve problems that are larger in scale even for supercomputers. However, volunteer computing projects are difficult to launch and deploy. These platforms also force volunteers to trust the authenticity of the project owner and to blindly accept credits allotted to their contribution by the project owner. As a result, very few high-profile trusted projects are able to sustain in this system. In this paper, we present an incentivized web-based volunteer computing platform that functions as a market place to buy and sell computing power. Launching a project on the system and contributing to an existing project happens over the browser without the need for a specialized software or hardware. We introduce the application of blockchain to remove the need to trust any other party in the system. We also present a prototype implementation and solve NP-Problems as examples using the proposed prototype.

We are working in the era of cloud computing, where all of the required resources are available online at pay-par-basis. It made all the IT industry easily accessible to all types of users. It provides the services in software, hardware and in storage terms. We are dealing the model of IAAS which provides on demand secured storage services. A number of researchers has designed and proposed a number of techniques and algorithms for assurance of storage services provided by cloud service providers. Our paper presents a modified approach of integrity verification in multiparty communication in decentralized cloud computing environment. We enhanced the basic model of AES with AES Poly Library 1305 and also redesigned the variant of secret sharing scheme for handling a secured group communication. Our factors for evaluation are the hardness and randomness of key i.e. entropy of the proposed technique and other measurable units which gives the efficiency of communication overhead and security.

In several fields such as statistics, machine learning, and bioinformatics, categorical variables are frequently represented as one-hot encoded vectors. For example, given 8 distinct values, we map each value to a byte where only a single bit has been set. We are motivated to quickly compute statistics over such encodings. Given a stream of k-bit words, we seek to compute k distinct sums corresponding to bit values at indexes 0, 1, 2, ..., k-1. If the k-bit words are one-hot encoded then the sums correspond to a frequency histogram. This multiple-sum problem is a generalization of the population-count problem where we seek the sum of all bit values. Accordingly, we refer to the multiple-sum problem as a positional population-count. Using SIMD (Single Instruction, Multiple Data) instructions from recent Intel processors, we describe algorithms for computing the 16-bit position population count using less than half of a CPU cycle per 16-bit word. Our best approach uses up to 400 times fewer instructions and is up to 50 times faster than baseline code using only regular (non-SIMD) instructions, for sufficiently large inputs.

Development of fast methods to conduct in silico experiments using computational models of cellular signaling is a promising approach toward advances in personalized medicine. However, software-based cellular network simulation has run-times plagued by wasted CPU cycles and unnecessary processes. Hardware-based simulation affords substantial speedup, but prior attempts at hardware-based biological simulation have been limited in scope and have suffered from inaccuracies due to poor random number generation. In this work, we propose several hardware-based simulation schemes utilizing novel random update index generation techniques for step-based and round-based stochastic simulations of cellular networks. Our results show improved runtimes while maintaining simulation accuracy compared to software implementations.

Classifying traffic signs is an indispensable part of Advanced Driver Assistant Systems. This strictly requires that the traffic sign classification model accurately classifies the images and consumes as few CPU cycles as possible to immediately release the CPU for other tasks. In this paper, we first propose a new ConvNet architecture. Then, we propose a new method for creating an optimal ensemble of ConvNets with highest possible accuracy and lowest number of ConvNets. Our experiments show that the ensemble of our proposed ConvNets (the ensemble is also constructed using our method) reduces the number of arithmetic operations 88 and $$73\,\%$$73% compared with two state-of-art ensemble of ConvNets. In addition, our ensemble is $$0.1\,\%$$0.1% more accurate than one of the state-of-art ensembles and it is only $$0.04\,\%$$0.04% less accurate than the other state-of-art ensemble when tested on the same dataset. Moreover, ensemble of our compact ConvNets reduces the number of the multiplications 95 and $$88\,\%$$88%, yet, the classification accuracy drops only 0.2 and $$0.4\,\%$$0.4% compared with these two ensembles. Besides, we also evaluate the cross-dataset performance of our ConvNet and analyze its transferability power in different layers. We show that our network is easily scalable to new datasets with much more number of traffic sign classes and it only needs to fine-tune the weights starting from the last convolution layer. We also assess our ConvNet through different visualization techniques. Besides, we propose a new method for finding the minimum additive noise which causes the network to incorrectly classify the image by minimum difference compared with the highest score in the loss vector.

Multicore processors are widely used in today's computer systems. Multicore virtualization technology provides an elastic solution to more efficiently utilize the multicore system. However, the Lock Holder Preemption (LHP) problem in the virtualized multicore systems causes significant CPU cycles wastes, which hurt virtual machine (VM) performance and reduces response latency. The system consolidates more VMs, the LHP problem becomes worse. In this paper, we propose an efficient consolidation-aware vCPU (CVS) scheduling scheme on multicore virtualization platform. Based on vCPU over-commitment rate, the CVS scheduling scheme adaptively selects one algorithm among three vCPU scheduling algorithms: co-scheduling, yield-to-head, and yield-to-tail based on the vCPU over-commitment rate because the actions of vCPU scheduling are split into many single steps such as scheduling vCPUs simultaneously or inserting one vCPU into the run-queue from the head or tail. The CVS scheme can effectively improve VM performance in the low, middle, and high VM consolidation scenarios. Using real-life parallel benchmarks, our experimental results show that the proposed CVS scheme improves the overall system performance while the optimization overhead remains low. We propose an efficient consolidation-aware vCPU (CVS) scheduling scheme.The CVS scheduling scheme adaptively selects three vCPU scheduling algorithms.The CVS scheme can effectively improve virtual machine performance.The CVS scheme works in different consolidation scenarios.

The high number of occupational accidents occurring every year in the industrial sector is still one of the main social policy action areas of governments worldwide. Both technical and human failures are often addressed as the main causes for accidents at work. However, the lack of full hazard prevention effectiveness from currently available Safeguarding Devices is another factor that should be considered, at least, from an engineering viewpoint. This paper presents a recently patented Access Detection and Machine Cycle Tracking System (ADMCTS) for industrial machinery with active safety purposes. Active safety paradigm has greatly succeeded in the automotive sector in the last years, dramatically improving road traffic accident prevention by means of active devices with real-time capabilities. Based on a dedicated Computer Vision System (CVS) for real-time video analysis of a monitored safety zone, the ADMCTS performs three main functions: access and presence detection of objects entering and/or remaining within the monitored zone, machine cycle tracking, and warning and alarm signal handling to ensure that machine functions are only allowed when workplace conditions are safe. Machine cycle tracking provides the ADMCTS with an adaptive risk assessment capability for optimal prevention. In order to provide a thoughtful description of its functionality, a state machine model of the ADMCTS is introduced, and a visual walk-through of this model, as applied on a generic cutting machine, is also discussed.

In virtualized environments, multiprocessor virtual machines encounter synchronization problems such as lock holder preemption (LHP) and lock waiter preemption (LWP). When the issue happens, a virtual CPU (VCPU) waiting for such locks spins for an extraordinarily long time and wastes CPU cycles seriously, resulting in a significant degradation of system performance. Recent research that addresses this issue has some shortcomings. To address these problems, this paper proposes an efficient lock-aware virtual machine scheduling scheme to avoid LHP and LWP. Our approach detects lock holders and waiters from the virtual machine monitor side, and gives preempted lock holders and waiters multiple, continuous, extra scheduling chances to release locks, assuring that the de-scheduled VCPUs are not lock holders or waiters with high probability. We implement a Xen-based prototype and evaluate the performance of lock-intensive workloads. The experimental results demonstrate that our scheduling scheme fundamentally eliminates lock holder preemptions and lock waiter preemptions.

In current NFV ecosystem, most software NFs delivered by NF vendors tend to be monolithic with multiple features. In runtime, an NF is configured with a subset of its features turned on/off. By our code analysis and primary test, we find that some of the (runtime) unused features are executed silently, which wastes CPU cycles and memory. We propose to use program analysis techniques to eliminate runtime redundant logic in NF code so that the NF performance can be accelerated. We prototype our idea and test it on Snort to show the feasibility.

The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware-based imaging systems arises. These fully hardware systems solve the fundamental problem inherent in software-based solutions, in which the speed of the algorithms depend on the instruction cycle speed of the processor. Once an algorithm is designed directly on hardware, the speed of the algorithm depends on the system clock frequency and the propagation delays of the logic cells (or standard cells) used in the design, usually measured in nanoseconds per cell. Therefore, such systems no longer depend on any instruction cycle delays, as there is no microprocessor involved. Most modern imaging and communications systems rely on digital signal processing (DSP) to compute complex mathematical operations. The emergence of powerful and low-cost field-programmable gate array (FPGA) devices with hundreds of arithmetic multipliers has enabled the development of many such DSP hardware applications, traditionally implemented only as software solutions.

CPU cache misses and branch mispredictions waste CPU cycles and affect program performance. Such software inefficiencies could be neither eliminated by existing compilers nor avoided by developers. In this paper, we propose a novel approach, named PERDICE, to automatically discover such performance bugs by leveraging concolic execution. PERDICE adopts a new path exploration algorithm to discover such software inefficiencies. In particular, we measure performance losses in the granularity of program locations (e.g., instructions, source code lines) instead of paths to avoid getting stuck into the code without software inefficiencies. Moreover, when scoring test inputs, our new approach prefers the test inputs incurring increments in performance losses. This strategy allows PERDICE to avoid getting stuck into the software inefficiencies that have been found. We have implemented PERDICE for both PC (X86 instructions) and Android smartphones (ARM instructions). The experimental results with real-world desktop software and Android native code show that PERDICE outperforms the other four popular algorithms and PROFs (a multi-path performance profiler) in terms of the speed to discover software inefficiencies and the severity (i.e, amount of wasted CPU cycles) of inefficiencies.

A large number of workloads are written in garbage-collected languages. These applications spend up to 10-35% of their CPU cycles on GC, and these numbers increase further for pause-free concurrent collectors. As this amounts to a significant fraction of resources in scenarios ranging from data centers to mobile devices, reducing the cost of GC would improve the efficiency of a wide range of workloads. We propose to decrease these overheads by moving GC into a small hardware accelerator that is located close to the memory controller and performs GC more efficiently than a CPU. We first show a general design of such a GC accelerator and describe how it can be integrated into both stop-the-world and pause-free garbage collectors. We then demonstrate an end-to-end RTL prototype of this design, integrated into a RocketChip RISC-V System-on-Chip (SoC) executing full Java benchmarks within JikesRVM running under Linux on FPGAs. Our prototype performs the mark phase of a tracing GC at 4.2x the performance of an in-order CPU, at just 18.5% the area (an amount equivalent to 64KB of SRAM). By prototyping our design in a real system, we show that our accelerator can be adopted without invasive changes to the SoC, and estimate its performance, area and energy.

In this article, we illustrate that the boundary of a general-purpose node can be extended into the network by extracting information from network traffic generated by that general-purpose node to infer the state of its hardware components. This information is represented in a delay signature latent within the network traffic. In contrast, the traditional approach to determine the internal state of a node’s resources meant that a software application with internal processes had to be resident on the node. The aforementioned delay signature is the keystone that provides a correlation between network traffic and the internal state of the source node. We characterize this delay signature by (1) identifying the different types of assembly language instructions that source this delay and (2) describing how architectural techniques, such as instruction pipelining and caching, give rise to this delay signature. In theory, highly utilized nodes (due to multiple threads) will contain excessive context switching and contention for shared resources. One important shared resource is main memory, and excessive use of this resource by applications and internal processes eventually leads to a decrease in cache efficiency that eventually stalls the instruction pipeline. Our results support this theory; specifically, we have observed that excessive context switching in active applications increases the effective memory access time and wastes precious CPU cycles, thus adding additional delay to the execution of load, store, and other instructions. Because the operating system (OS) kernel accesses memory to send network packets, the delay signature is induced into network traffic in situations where user-level utilization is high. We demonstrate this theory in two case studies: (1) resource discovery in cluster grids and (2) network-based detection of bitcoin mining on compromised nodes.

Peer-to-Peer (P2P) computing, the harnessing of idle CPU cycles through the Internet, offers new research challenges in the domain of distributed computing. This paper proposes an efficient, dynamic and scalable overlay orientated towards P2P computing, called DisCoP. Our proposal gathers the peers into markets according to their computational resources. Each market is arranged in an N-ari Tree and these trees are linked by a Bruijn graph. The tree topology allows efficient searching of available resources in a specific market, while the Bruijn provides good scalability. A Hilbert function is used to arrange markets in one ordered and mono-dimensional space. This way, the proposed architecture exploits the Bruijn and the N-ari tree topologies together with the Hilbert function to classify the computing markets. Searching efficiently for computational resources in P2P systems is a challenge and in turn, an essential requirement for the platform to provide. This article also proposes different search algorithms, each adapted to the DisCoP overlay and optimized to locate computing resources in different ways: exact, range, multi-attribute and approximate searches. A large number of experiments demonstrate the correct behavior of our proposals. The comparison of the obtained results obtained compared to other approaches in the literature reveals their competitiveness in terms of efficiency, latency and hit rates.

This paper focus on the integration of wireless technology and CAD/CAM system for CNC workshop development. A specific case study is described a system based on embedded wireless device and Internet of Things (IoT) concept with Bezier techniques for the proposed model. The focus of the case study is to show a complete stage of manufacturing process starting from modeling in CAD system passing through CAM system, transferring NC code, gathering machine data, monitoring whole process and finally manufacturing product. Using MATLAB and UG-NX software for modeling, Monitoring machining process using temperature, accelerometers and gyroscope sensors based on IoT concept. Transferring NC codes to CNC machines using FTP protocol and DNC software, real-time report demonstrate information about machine name, parts progress, time, operation condition and Machine Cycle Time depending on DNC network.

In Fine-Grained Cycle Sharing (FGCS) systems, machine owners voluntarily share their unused CPU cycles with guest jobs, as long as their performance degradation is tolerable. However, unpredictable evictions of guest jobs lead to fluctuating completion times. Checkpoint-recovery is an attractive mechanism for recovering from such "failures". Today's FGCS systems often use expensive, high-performance dedicated checkpoint servers. However, in geographically distributed clusters, this may incur high checkpoint transfer latencies. In this paper we present a distributed checkpointing system called Falcon that uses available disk resources of the FGCS machines as shared checkpoint repositories. However, an unavailable storage host may lead to loss of checkpoint data. Therefore, we model the failures of a storage host and develop a prediction algorithm for choosing reliable checkpoint repositories. We experiment with Falcon in the university-wide Condor testbed at Purdue and show improved and consistent performance for guest jobs in the presence of irregular resource availability.

The paper presents the design of an 8-bit RISC microcontroller, which is mainly targeted for performing non-timing crucial functions inside FPGAs. The microcontroller is based on popular Microchip PIC16 microcontrollers family. The main feature of the microcontroller is that it is 4 times faster for regular instructions, and 8 times faster for instructions which modify program counter, than its Microchip archetype clocked at the same frequency. Three versions of the microcontroller instruction cycle structures have been considered and performance tests of the versions have also been carried out. The paper also describes two sample applications which illustrate the usefulness of the microcontroller and show that using the FPGA embedded microcontroller, realization of some functions can be simpler and faster than applying a typical FPGA design flow without the microcontroller. To facilitate frequent exchange of the microcontroller program memory content, specifically at the software developing stage, the downloader module has been proposed to use as well. The downloader allows to directly load the compilers HEX output file to the program memory using a generic serial interface.

Computational grids are composed of heterogeneous autonomously managed resources. In such environment, any resource can join or leave the grid at any time. It makes the grid infrastructure unreliable in nature resulting in delay and failure of executing jobs. Thus, fault tolerance becomes a vital aspect of grid for realizing reliability, availability and quality-of-service. The most common technique, for achieving fault tolerance, used in High Performance Computing is rollback recovery. It relies on the availability of checkpoints and stability of storage media. Thus the checkpoints are replicated on storage media. It increases the job execution time, if replication is not done in proper manner. Furthermore, dedicating powerful resources solely as checkpoint storage results in loss of computation power of these resources. It may results in bottlenecks, when the load on the network is high. To address the problem, in this paper checkpoint replication based fault tolerance strategy named as Reliable Checkpoint Storage Strategy (RCSS) is proposed. In RCSS, the checkpoints are replicated on all checkpoint servers in the grid in distributed manner. It decreases the checkpoint replication time and in turn improves the overall job execution time. Additionally, if a resource fails during execution of a job, the RCSS restarts the job from its last valid checkpoint taken from any checkpoint server in the grid. Furthermore to increase the grid performance, CPU cycles of checkpoint servers are also utilized during high load on network. To evaluate the performance of RCSS simulations are carried out using GridSim. The simulation results show that RCSS outperforms in intra-cluster Checkpoint wave completion time by 12.5 % with varying number of checkpoint servers. RCSS also reduces checkpoint wave completion time by 50 % with varying number of clusters. Additionally RCSS reduces replication time within cluster by 39.5 %.

Intra-GPU synchronization is a problem for GPU controlled communication.Options, based on dynamic parallelism provide on-device synchronization.GPU controlled communication have a lower performance than CPU assisted approaches.Relieving the CPU from the communication work leads to lower energy consumption.Serialization leads to high number of instruction replays on GPUs. Graphic Processing Units (GPUs) are widely used in high performance computing, due to their high computational power and high performance per Watt. However, one of the main bottlenecks of GPU-accelerated cluster computing is the data transfer between distributed GPUs. This not only affects performance, but also power consumption. The most common way to utilize a GPU cluster is a hybrid model, in which the GPU is used to accelerate the computation, while the CPU is responsible for the communication. This approach always requires a dedicated CPU thread, which consumes additional CPU cycles and therefore increases the power consumption of the complete application. In recent work we have shown that the GPU is able to control the communication independently of the CPU. However, there are several problems with GPU-controlled communication. The main problem is intra-GPU synchronization, since GPU blocks are non-preemptive. Therefore, the use of communication requests within a GPU can easily result in a deadlock. In this work we show how dynamic parallelism solves this problem. GPU-controlled communication in combination with dynamic parallelism allows keeping the control flow of multi-GPU applications on the GPU and bypassing the CPU completely. Using other in-kernel synchronization methods results in massive performance losses, due to the forced serialization of the GPU thread blocks. Although the performance of applications using GPU-controlled communication is still slightly worse than the performance of hybrid applications, we will show that performance per Watt increases by up to 10% while still using commodity hardware.

This work was carried out in order to examine and compare selected models of genetic algorithms (through the implementation), using the latest tools and libraries that allow for multithreaded programming in a .NET environment. Implemented algorithms were then tested for the use of available resources, such as CPU cycles/cores consumption and the time at which they are able to provide the quality results at acceptable pace. With a choice of multi-core processors—allowing for parallel calculations on their cores, as well as genetic algorithms, one should think about how to implement the chosen algorithm so as to avoid the deadlocks and bottlenecks to make optimal use of the computing power of cores. There are many approaches to deal with such issues—a lot of tools and software libraries facilitate the implementation of such algorithms. This paper tries to address two essential questions what algorithms fit the best into multicore architecture, and which one benefits the best from available logical/physical cores producing the best possible results.

The ability of tiny embedded devices to run large feature-rich programs is typically constrained by the amount of memory installed on such devices. Furthermore, the useful operation of these devices in wireless sensor applications is limited by their battery life. This paper presents a call stack redesign targeted at an efficient use of RAM storage and CPU cycles by a Java program running on a wireless sensor mote. Without compromising the application programs, our call stack redesign saves 30% of RAM, on average, evaluated over a large number of benchmarks. On the same set of bench-marks, our design also avoids frequent RAM allocations and deallocations, resulting in average 80% fewer memory operations and 23% faster program execution. These may be critical improvements for tiny embedded devices that are equipped with small amount of RAM and limited battery life. However, our call stack redesign is equally effective for any complex multi-threaded object oriented program developed for desktop computers. We describe the redesign, measure its performance and report the resulting savings in RAM and execution time for a wide variety of programs.

Understanding and identifying performance problems is difficult for parallel applications, but is an essential part of software development for parallel systems. In addition to the same problems that exist when analysing sequential programs, software development tools for parallel systems must handle the large number of execution engines (cores) that result in different (possibly non-deterministic) schedules for different executions. Understanding where exactly a concurrent program spends its time (esp. if some aspects of the program paths depend on input data) is the first step towards improving program quality. State-of-the-art profilers, however, aid developers in performance diagnosis by providing hotness information at the level of a class or method (function) and usually report data for just a single program execution. This paper presents a profiling and analysis technique that consolidates execution information for multiple program executions. Currently, our tool's focus is on execution time (CPU cycles) but other metrics (stall cycles for functional units, cache miss rates, etc) are possible, provided such data can be obtained from the processor's monitoring unit. To detect the location of performance anomalies that are worth addressing, the average amount of time spent inside a code block, along with the statistical range of the minimum and maximum amount of time spent, is taken into account. The technique identifies performance bottlenecks at the fine-grained level of a basic block. It can indicate the probability of such a performance bottleneck appearing during actual program executions. The technique utilises profiling information across a range of inputs and tries to induce performance bottlenecks by delaying random memory accesses. The approach is evaluated by performing experiments on the data compression tool pbzip2, the multi-threaded download accelerator axel, the open source security scanner Nmap and Apache httpd web server. An experimental evaluation shows the tool to be effective in detecting performance bottlenecks at the level of a basic block. Modifications in the block that is identified by the tool result in performance improvement of over 2.6x in one case, compared to the original version of the program. The performance overhead incurred by the tool is a reasonable 2-7x in majority of the cases.

On shared-memory systems, Cilk-style work-stealing has been used to effectively parallelize irregular task-graph based applications such as Unbalanced Tree Search (UTS). There are two main difficulties in extending this approach to distributed memory. In the shared memory approach, thieves (nodes without work) constantly attempt to asynchronously steal work from randomly chosen victims until they find work. In distributed memory, thieves cannot autonomously steal work from a victim without disrupting its execution. When work is sparse, this results in performance degradation. In essence, a direct extension of traditional work-stealing to distributed memory violates the work-first principle underlying work-stealing. Further, thieves spend useless CPU cycles attacking victims that have no work, resulting in system inefficiencies in multi-programmed contexts. Second, it is non-trivial to detect active distributed termination (detect that programs at all nodes are looking for work, hence there is no work). This problem is well-studied and requires careful design for good performance. Unfortunately, in most existing languages/frameworks, application developers are forced to implement their own distributed termination detection. In this paper, we develop a simple set of ideas that allow work-stealing to be efficiently extended to distributed memory. First, we introduce lifeline graphs: low-degree, low-diameter, fully connected directed graphs. Such graphs can be constructed from k -dimensional hypercubes. When a node is unable to find work after w unsuccessful steals, it quiesces after informing the outgoing edges in its lifeline graph. Quiescent nodes do not disturb other nodes. A quiesced node is reactivated when work arrives from a lifeline and itself shares this work with those of its incoming lifelines that are activated. Termination occurs precisely when computation at all nodes has quiesced. In a language such as X10, such passive distributed termination can be detected automatically using the finish construct -- no application code is necessary. Our design is implemented in a few hundred lines of X10. On the binomial tree described in olivier:08}, the program achieve 87% efficiency on an Infiniband cluster of 1024 Power7 cores, with a peak throughput of 2.37 GNodes/sec. It achieves 87% efficiency on a Blue Gene/P with 2048 processors, and a peak throughput of 0.966 GNodes/s. All numbers are relative to single core sequential performance. This implementation has been refactored into a reusable global load balancing framework. Applications can use this framework to obtain global load balance with minimal code changes. In summary, we claim: (a) the first formulation of UTS that does not involve application level global termination detection, (b) the introduction of lifeline graphs to reduce failed steals (c) the demonstration of simple lifeline graphs based on k-hypercubes, (d) performance with superior efficiency (or the same efficiency but over a wider range) than published results on UTS. In particular, our framework can deliver the same or better performance as an unrestricted random work-stealing implementation, while reducing the number of attempted steals.

The inherent limitations of embedded systems make them particularly vulnerable to attacks. We have developed a hardware monitor that operates in parallel to the embedded processor and detects any attack that causes the embedded processor to deviate from its originally programmed behavior. We explore several different characteristics that can be used for monitoring and quantitative tradeoffs between these approaches. Our results show that our proposed hash-based monitoring pattern can detect attacks within one instruction cycle at lower memory requirements than traditional approaches that use control-flow information.

Transient faults are rising as a crucial concern in the reliability of computer systems. As the emerging trend of integrating coprocessors into symmetric multiprocessors, it offers a better choice for software-oriented fault tolerance approaches. This paper presents coprocessor-based process level redundancy (PLR) which makes use of coprocessors and frees CPU cycle to other tasks. The experiment is conducted by comparing the performance of one CPU version of PLR and one coprocessor version PLR using a subset of optimised SPEC CPU2006 benchmark. It shows that the proposed approach enhances performance by 32.6% on average. The performance can be enhanced more if one application contains more system calls. This common technique can be adapted to other software-based fault tolerance as well.

Volunteer computing projects have been used to make significant advances in knowledge since the 1990s. These projects use idle CPU cycles donated by people to solve computationally intensive problems in medicine, the sciences and other disciplines. It is important to use the donated cycles as efficiently as possible because participation in volunteer computing is low and the number of volunteer computing projects keeps increasing. Task retrieval policies, policies describing when a volunteered computer requests additional work from a server, can have an effect on the number of wasted CPU cycles and consequently, the number of tasks completed by clients. We present the results of simulating different task retrieval policies for clients under realistic conditions, including clients running on computers with one single-core CPU, clients running on computers with multi-core CPUs, and clients running on computers that are put into a power save mode by environmentally conscious owners.

Grid resources are non-dedicated, and thus grid users are forced to compete with resource owners for idle CPU cycles. As a result, the turnaround times of both the grid jobs and the owners' jobs are invariably delayed. To resolve this problem, the current study proposes a progressive multi-layer resource reconfiguration framework, designated as PMR-G, in which intra- and inter-site reconfiguration strategies are employed to adapt grid users' jobs dynamically to changes in the available CPU resources at each node. The experimental results show that PMR-G enables the idle CPU cycles of a resource to be fully exploited by grid users with minimum interference to the resource owner's jobs.

In the last years, diverse network interface designs have been proposed to cope with the link bandwidth increase that is shifting the communication bottleneck towards the nodes in the network. The main point behind some of these network interfaces is to reach an efficient distribution of the communication overheads among the different processing units of the node, thus leaving more host CPU cycles for the applications and other operating systems tasks. Among these proposals, protocol offloading searches for an efficient use of the processing elements in the network interface card (NIC) to free the host CPU from network processing. The lack of both, conclusive experimental results about the possible benefits and a deep understanding of the behavior of these alternatives in their different parameter spaces, have caused some controversy about the usefulness of this technique. The contributions of this paper deal with the implementation and evaluation of offloading strategies and with the need of accurate tools for researching the computer system issues that, as networking, require the analysis of interactions among applications, operating system, and hardware. Thus, in this paper, a way to include timing models in a full-system simulator (Simics) to provide a suitable tool for network subsystem simulation is proposed. Moreover, we compare two kinds of simulators, a hardware description language level simulator and a full-system simulator (including our proposed timing models), in the analysis of protocol offloading at different levels. We also explain the results obtained from the perspective of the previously described LAWS model and propose some changes in this model to get a more accurate approach to the experimental results. From these results, it is possible to conclude that offloading allows a relevant throughput improvement in some circumstances that can be qualitatively predicted by the LAWS model.

Grid computing is often regarded as a means for creating inexpensive "super-computing." With grid computing organizations can optimize computing and data resources, pool such resources to support massive, compute intensive loads. This paper aims at demonstrating experiences gained during aggregation of large computational power acquired from idle workstations connected on the campus. The cycle harvesting is attained by integrating and configuring a suite of grid and middleware software technologies anchored by the Globus toolkit, further optimized to extract the large computational capacity in the form of MIPS and GFLOPS. NirmaGrid produced is coordination of available computational efforts by Scavenging of idle CPU cycles, which allows the sharing of a computational task among multiple processors.

Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. On today's architectures a cache miss may cost several hundred CPU cycles. In order to fulfill stringent performance requirements, caches are now also used in hard real-time systems. In such systems, upper and sometimes also lower bounds on the execution times of a task have to be computed. To obtain tight bounds, timing analyses must take into account the cache architecture. However, developing cache analyses -- analyses that determine whether a memory access is a hit or a miss -- is a difficult problem for some cache architectures. In this paper, we present a tool to automatically compute relative competitive ratios for a large class of replacement policies, including LRU, FIFO, and PLRU. Relative competitive ratios bound the performance of one policy relative to the performance of another policy. These performance relations allow us to use cache-performance predictions for one policy to compute predictions for another, including policies that could previously not be dealt with.

In this paper, we consider timeliness and energy optimization in battery-powered dynamic embedded real-time systems, which must remain functional during an operation/mission with a bounded energy budget. We consider application activities that are subject to time/utility function time constraints, statistical assurance requirements on timeliness behavior, and an energy budget which cannot be exceeded at runtime. To account for the inevitable variability in activity arrivals in dynamic systems, we describe arrival behaviors using the unimodal arbitrary arrival model (UAM) [15]. For such a model, we present a dynamic voltage scaling (DVS)-based CPU scheduling algorithm called the energy-bounded utility accrual algorithm (EBUA). Since the scheduling problem is intractable, EBUA allocates CPU cycles, scales clock frequency, and heuristically computes schedules using statistical estimates of cycle demands in polynomial time. We analytically establish EBUA's properties, including satisfaction of energy bounds, statistical assurances on individual activity timeliness behavior, optimal timeliness during underloads, and bounded time for mutually exclusively accessing shared non-CPU resources. Our simulation experiments validate our analytical results and illustrate the algorithm's effectiveness and superiority over past algorithms.

CPU cycle sharing among distributed heterogeneous computers is the key function in large-scale volunteer computing and desktop grid applications. One important problem in large-scale distributed cycle sharing system is how to account for the amount of computation work performed by a CPU cycle provider, in a uniform and portable fashion across heterogeneous hardware and operating system platforms. Such an accounting mechanism is especially desirable when CPU resources are traded and a lack of uniform workload accounting will hinder the enforcement of market-driven CPU pricing/trading policies in distributed cycle sharing systems. Java Virtual Machine (JVM) has proved to be a good match for distributed cycle sharing because of its abilities to run applications on a wide variety of platforms without modification (portability) and to host untrusted applications (safety). In this paper, we present the design, implementation, and evaluation of an efficient, application-transparent virtual cycle accounting scheme integrated into JVM. Our scheme achieves portable workload accounting across heterogeneous computing platforms by accounting for JVM virtual instructions instead of real processor cycles. Different from the existing JVM CPU accounting mechanisms that involve bytecode rewriting, our scheme is transparent to applications and does not require visible changes to application and library code interfaces which would break applications that use Reflection API. Moreover, our scheme is efficient via the use of processor registers for accounting. Our experimental results demonstrate both high accounting accuracy and low runtime overhead of virtual cycle accounting.

CPU Frequency scaling is a common approach used for achieving energy savings in parallel applications. A typical approach for achieving power savings is by reducing the frequency of a processor whenever the invested CPU cycles do not contribute to the progress of an application (e.g. polling for events). Many recent research efforts have been directed towards employing this approach within HPC applications. However, one of the important challenges that have remained unexplored is its potential impact on data transfer operations within communication-intensive applications.This paper presents a detailed analysis of the impact of frequency scaling on the performance and energy efficiency of one-sided point-to-point communication within PGAS models. As an an outcome of this study, we observe that the extent of this impact depends on a number of factors like the implementation approach of a data transfer operation and the number of explicit remote transfers initiated. Besides the characteristics of the software stack, hardware features like the microarchitectural design also impact the performance of such data movement while adopting voltage scaling techniques. These inferences are supplemented with empirical analysis of common approaches of implementing remote write (PUT) operations.The empirical results presented in this paper should act as a guide for future design of software solutions targeting energy efficiency in distributed systems.

Grid computing refers to systems that harness the unused CPU cycles of personal computers connected over a corporate network or the Internet to accelerate application performance. There are some software toolkits used for implementing grid computing. Among them, Alchemi is widely used and open source toolkit that runs on the Windows operating system in the .NET Framework. The node which requests an application to be performed is called the owner. The node that receives the requested application and sends results back to the owner is called Manager. An application is divided into many threads. These threads are submitted to other nodes called Executor. In many cases, the faster one remains idle for a long time after completing the job. Current scheduling algorithm assigns only one thread to one executor. In this paper, we propose a technique to assign more than one thread to execute according the available CPU cycle.

Molecular simulations with quantum chemistry methods consume a large portion of CPU cycles in modern high-performance computing centers. Evolution of modern processors and HPC architectures necessitates adaptation of software to new hardware generations. The present work concentrates on the optimization of the widely used GAMESS code to Intel Xeon Phi architecture and recently devised RSC PetaStream platform. Since improvement in parallelization is required, the most frequently used Hartree-Fock and DFT methods are explored for additional parallelization options. The Xeon Phi requires vectorization that is important for electron-repulsion integrals (ERI) calculations to achieve good performance.

Constant False Alarm Rate (CFAR) algorithm is an important technology of radar system. It can provide optimal signal detection performance via maintaining a constant false alarm rate. However, the computational workload of estimating the clutter power of every data unit can be high. Thus, a software pipeline method for CFAR on the Digital Signal Processor(DSP) of TI's latest series C6000 family is proposed in this paper. Compared with non-optimized CFAR algorithm, software pipeline operation can achieve better performance and 41x improvement on instruction cycle.

Analytic performance models are essential for understanding the performance characteristics of loop kernels, which consume a major part of CPU cycles in computational science. Starting from a validated performance model one can infer the relevant hardware bottlenecks and promising optimization opportunities. Unfortunately, analytic performance modeling is often tedious even for experienced developers since it requires in-depth knowledge about the hardware and how it interacts with the software. We present the "Kerncraft" tool, which eases the construction of analytic performance models for streaming kernels and stencil loop nests. Starting from the loop source code, the problem size, and a description of the underlying hardware, Kerncraft can ideally predict the single-core performance and scaling behavior of loops on multicore processors using the Roofline or the Execution-Cache-Memory (ECM) model. We describe the operating principles of Kerncraft with its capabilities and limitations, and we show how it may be used to quickly gain insights by accelerated analytic modeling., Comment: 11 pages, 4 figures, 8 listings