Search

Ultrathin oxides (UOs) and ultrathin nitrides (UNs) play a crucial role in forming lattice-mismatched semiconductor heterostructures that are fabricated by using semiconducting grafting approach. The grafting approach has shown its great potential to realize GaN-based heterojunction bipolar transistors by fulfilling the missing high-performance p-type nitrides with other p-type semiconductors. A handful of UO and UN dielectrics readily available by atomic layer deposition (ALD) satisfy the requirements of double-sided surface passivation and quantum tunneling for semiconductor grafting. Due to the states existing between the UO or UN conduction band and that of the GaN, the ALD deposited UO or UN layer can generate significant effects on the surface band-bending of GaN. Understanding the band parameters of the interface between UO or UN and c-plane Ga-face GaN can guide the selection of interfacial dielectrics for grafted GaN-based devices. In this study, we performed x-ray photoelectron spectroscopy measurements to obtain the band-bending properties on c-plane, Ga-face GaN samples coated by different ALD cycles of ultrathin-HfO2 or ultrathin AlN. The valence band spectra of GaN coated with ultrathin-ALD–Al2O3, ALD–HfO2, or PEALD–AlN/ALD–Al2O3 were further analyzed to calculate the valence and conduction band offsets between the ALD dielectrics and the Ga-face GaN under different thicknesses and post-deposition annealing conditions of the dielectrics. [ABSTRACT FROM AUTHOR]

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit. [ABSTRACT FROM AUTHOR]

Recently, a GaN reverse-conducting high-electron-mobility transistor (RC-HEMT) has been demonstrated. The RC-HEMT features built-in distributive Schottky contacts, which provide a low-loss freewheeling path. The RC-HEMT offers the same functionality as an HEMT/Schottky barrier diode (SBD) pair, but consumes much less chip area, thus its ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (ON-resistance $\times $ total device width) is significantly reduced. Theoretically, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT can approach that of an HEMT. In practice, due to certain geometry limitations, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of an RC-HEMT lies between an HEMT/SBD pair and a single HEMT. This work investigates the factors that influence ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT using both experimental measurements and numerical simulations. It is found that ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is strongly affected by the geometry of the source and channel regions, where HEMT sections and SBD sections are interdigitally distributed. With coarse patterning of these regions, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is close to the HEMT/SBD pair. Through proper geometry scaling, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of RC-HEMT is reduced and approaches that of HEMT. [ABSTRACT FROM AUTHOR]

A 700-V normally-off ${p}$ -GaN gate power transistor with distributed built-in Schottky barrier diode (SBD) is demonstrated in this work. The transistor cell and diode cell are alternately arrayed along the device width and are locally isolated using ion implantations. The built-in SBD provides a low reverse turn-on voltage which is independent of the threshold voltage and gate bias of the transistor. Compared to the two-device scheme consisting of an anti-parallel ${p}$ -GaN gate HEMT/SBD pair, the proposed transistor exploits the common access region in both forward conduction and reverse conduction, thus a significant reduction in chip area is obtained. [ABSTRACT FROM AUTHOR]

Commercially available normally-off GaN power high-electron-mobility transistor (HEMT) devices have typically adopted a p-GaN gate structure. In the gate region, there exist a Schottky junction (between gate electrode and the p-GaN layer) and a p-GaN/AlGaN/GaN heterojunction. As the p-GaN layer is not directly shorted to the gate electrode and conducting channel, it can be considered as electrically “floating.” With drain voltage changing during a switching process, the variation of net charge in the floating p-GaN layer would cause instability in threshold voltage. Besides, because of the distinctive features of the p-GaN gate HEMT structure under certain gate/drain bias, gate-related junction capacitances would exhibit behavior different from those of a Si mosfet. Consequently, the switching transient performance of a GaN transistor with a p-GaN gate could be significantly influenced by the aforementioned factors. In this work, the threshold voltage instability associated with the drain-to-gate voltage stress is first analyzed. Despite the difficulty in directly performing capacitance measurements inside the device structure, a hybrid physical-behavior modeling method is proposed. The model is capable of extracting the capacitance bias relationships with regard to the gate region from static terminal measurements. In previous works, the advanced analytical model would make modest change on a Si mosfet's model. As a result, without fully considering the specific features of a GaN transistor with the p-GaN gate, the simulated waveforms would exhibit 20–50% discrepancy from the experiment. In contrast, the proposed switching transient analytical approach would exhibit improved accuracy (<10% disparity). Consequently, the switching transient performance of the GaN transistor with the p-GaN gate could be more accurately evaluated. [ABSTRACT FROM AUTHOR]

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminal's safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model. [ABSTRACT FROM AUTHOR]

In addition to surface- and buffer-trapping, interface/border trapping and the consequent VTH shift in insulated-gate GaN power transistors could also cause RON increase, due to the reduced gate overdrive. This work reports on a systematic study of the trapping mechanisms in normally-on/off insulated-gate GaN transistors subjected to dynamic (AC) and static (DC) gate stress. The fast dynamic characterizations featuring an ultrashort measurement delay of 10−7 s minimize the recovery during measurement and enable a quantitative evaluation of VTH shift-induced RON increase. By analyzing the time-resolved instability in normally-on MIS-HEMT and normally-off MIS-FET with fully recessed barrier, we elucidate several key mechanisms including: (i) recessing the polarized III-nitride barrier layer can suppress VTH shift during ON/OFF switching; (ii) AC stress, which has more practical implication for lifetime projection for power switching applications, produces smaller VTH shift and RON increase comparing to DC stress; (iii) Sufficient gate overdrive at ON state and lower channel resistance in normally-on MIS-HEMT allow a better tolerance to VTH shift. Primary trapping effects in an insulated-gate GaN power transistor. [ABSTRACT FROM AUTHOR]

GaN power switching transistors featuring MIS- and MOS-gate structures are highly preferred over the Schottky-gate counterpart, because of suppressed gate leakage, enlarged gate swing, and more scalable threshold voltage. Nevertheless, MIS-/MOS-gate GaN devices are confronted with stability and reliability challenges, which arise from interface traps at the critical dielectric/III-nitride interface, as well as bulk traps inside the gate dielectric including border traps near the critical interface. In this work, we present several key techniques toward reliable MIS-/MOS-gate GaN power devices, including advanced interface engineering technology, gate structure optimizations for high-performance/stability normally-off GaN power transistors, and long-lifetime gate dielectric technology. Schematic cross sections of GaN-based MIS-HEMT and MOS-channel-HEMT. [ABSTRACT FROM AUTHOR]

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with V\mathrm {th} of +0.5 V at I\mathrm {DS}= 10 ~\mu \text{A} /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( \textV\cdot \texts ). The on-resistance is as small as 6.9 \Omega \cdot \text mm for a DC-MOS-HEMT with LG/L\mathrm {GS}/L\mathrm {GD} = 1.5/2/15~\mu \text{m} , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. [ABSTRACT FROM AUTHOR]

Design of power delivery system has great influence on the power management in many-core processor systems. Moving voltage regulators from off-chip to on-chip gains more and more interest in the power delivery system design, because it is able to provide fine-grained dynamic voltage scaling. Previous works are proposed to implement power efficient on-chip voltage regulators. It is important to analyze the characteristics of the entire power delivery system to explore the tradeoff between the promising properties and costs of employing on-chip voltage regulators, especially the on-chip buck converters. In this paper, we present a novel analysis and design optimization platform of power delivery system called power supply on-chip (PowerSoC). It employs an analytical model to provide an accurate and fast evaluation of important characteristics, e.g., power efficiency, output stability, and dynamic voltage scaling, for the entire power delivery system consisting of on-chip/off-chip buck converters and power delivery network. Based on our model, geometric programming is utilized to find the optimal design for different power delivery systems and explore the tradeoff of using on-chip converters. Compared with SPICE simulations, our model achieves a simulation time reduction of six to seven orders of magnitude within 5% model error for the characteristic evaluation of different power delivery systems. By using PowerSoC, various architectures of power delivery systems are optimized for power efficiency under constraints of output stability, area, etc. Simulation results show that the hybrid architecture, consisting of both on-chip and off-chip converters, achieves 1.0% power efficiency improvement and 66.4% area reduction of converters, compared to the conventional design. We conclude the hybrid architecture has potential for efficient dynamic voltage scaling, small area, and the adaptability of the change of power delivery network parasitic, but careful account for the overhead of on-chip converters is needed. [ABSTRACT FROM PUBLISHER]

We report that a simple metal-AlGaN/GaN Schottky diode is capable of producing GaN band-edge ultraviolet emission at 3.4 eV at a small forward bias larger than ~2V at room temperature. Based on the surface states distribution of AlGaN, a mature impact-ionization-induced Fermi-level depinning model is proposed to explain the underlying mechanism of the electroluminescence (EL) process. By experimenting with different Schottky metals, Ni/Au and Pt/Au, we demonstrated that this EL phenomenon is a "universal" property of metal-AlGaN/GaN Schottky diodes. Since this light-emitting Schottky diode shares the same active structure and fabrication processes as the AlGaN/GaN high electron mobility transistors, straight-forward and seamless integration of photonic and electronic functional devices has been demonstrated on doping-free III-nitride heterostructures. Using a semitransparent Schottky drain electrode, an AlGaN/GaN high electron mobility light-emitting transistor is demonstrated. [ABSTRACT FROM AUTHOR]

The threshold voltage ( VT) instability of metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) is investigated. In the enhancement-mode AlGaN/GaN MIS-HEMT fabricated by fluorine plasma implantation technique featuring Al2O3 gate dielectric, a hysteresis of 0.6 V in transfer characteristics is observed by quasi-static I - V (current-voltage) measurement, in which the gate bias is swept at a low rate (0.7 V/s). Pulsed transfer characteristics measurement, however, unveils much larger hysteresis under the same gate voltage swing. The VT-instability is attributed to the traps located at the dielectric/III-nitride interface as well as in the bulk of gate dielectric. It is proposed that pulsed measurement can count for the effect of fast traps (shallow traps) while the quasi-static measurement can only reflect slow traps (deep traps), and is more accurate for VT-instability evaluation. In addition, the existence of bulk traps is implied by a slow time-dependent shift of VT under large gate bias. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron mobility transistor's (HEMT's) off-state breakdown is investigated using drain-current injection techniques with different injection current levels. Competitions between the source leakage and gate leakage, pure leakage and impact ionization, and source- and gate-injection-induced impact ionization during the drain-injection measurement are discussed in detail. It was found that the breakdown originates from the source/gate leakage at low drain injection levels but is dominated by source/gate-induced impact ionization process at high drain injection currents. The source-induced impact ionization usually precedes the gate-induced impact ionization in low-gate leakage devices, resulting in a premature three-terminal off-state breakdown. We also found that the gate-bias value affects the breakdown voltage in the conventional three-terminal off-state breakdown I-V measurement and should be carefully considered. [ABSTRACT FROM AUTHOR]

We demonstrate a single-chip switch-mode boost converter that features a monolithically integrated lateral field- effect rectifier (L-FER) and a normally off transistor switch. The circuit was fabricated on a standard AIGaN/GaN HEMT epitaxial wafer grown with GaN-on-Si technology. The fabricated rectifier with a drift length of 15 μm exhibits a breakdown voltage of 470 V, a turn-on voltage of 0.58 V, and a specific on-resistance of 2.04 mΩ cm². The L-FER exhibits no reverse recovery cur- rent associated with the turn-off transient because of its unipolar nature. A prototype of GaN-based boost converter that includes monolithically integrated rectifiers and transistors is demonstrated using conventional GaN-on-Si wafers for the first time to prove the feasibility of the GaN-based power IC technology. [ABSTRACT FROM AUTHOR]

We report a low-density drain high-electron mobility transistor (LDD-HEMT) that exhibits enhanced breakdown voltage and reduced current collapse. The LDD region is created by introducing negatively charged fluorine ions in the region between the gate and drain electrodes, effectively modifying the surface field distribution on the drain side of the HEMT without using field plate electrodes. Without changing the device physical dimensions, the breakdown voltage can be improved by 50% in LDD-HEMT, and the current collapse can be reduced. No degradation of current cutoff frequency (ft) and slight improvement in power gain cutoff frequency (fmax) are achieved in the LDD-HEMT, owing to the absence of any additional field plate electrode. [ABSTRACT FROM AUTHOR]

A planar-fabrication technology for integrating enhancement/depletion (E/D)-mode AlGaN/GaN high-electron mobility transistors (HEMTs) has been developed. The technology relies heavily on CF4 plasma treatment, which is used in two separate steps to achieve two objectives: 1) active device isolation and 2) threshold-voltage control for the enhancement-mode HEMT formation. Using the planar process, depletion, and enhancement-mode AlGaN/GaN HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter is demonstrated. Compared with the devices fabricated by a standard mesa-etching technique, the HEMTs by a planar process have comparable dc and RF characteristics with no obvious difference in the device isolation. The device isolation by a plasma treatment remains the same after 400 °C annealing, indicating a good thermal stability. At a supply voltage (VDD) of 3.3 V, the E/D-mode inverters show an output swing of 2.85 V, with the logic-low and logic-high noise margins at 0.34 and 1.47 V, respectively. [ABSTRACT FROM AUTHOR]

We report an AlGaN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with high-mobility two-dimensional electron gas (2-DEG) and reduced buffer leakage. The device features a 3-nm thin lnxGa1-xN(x = 0.1) layer inserted into the conventional AlGaN/GaN HEMT structure. Assisted by the InGaN layers polarization field that is opposite to that in the AlGaN layer, an additional potential barrier is introduced between the 2-DEG channel and buffer, leading to enhanced carrier confinement and improved buffer isolation. For a sample grown on sapphire substrate with MOCVD-grown GaN buffer, a 2-DEG mobility of around 1300 cm²/V·s and a sheet resistance of 420 Ω/sq were obtained on this new DH-HEMT structure at room temperature. A peak transconductance of 230 mS/mm, a peak current gain cutoff frequency (fT) of 14.5 GHz, and a peak power gain cutoff frequency (fmax) of 45.4 GHz were achieved on a 1 ⊗ 100 μLm device. The off-state source-drain leakage current is as low ∼ 5 μ A/mm at VDS = 10 V. For the devices on sapphire substrate, maximum power density of 3.4 W/mm and PAE of 41% were obtained at 2 GHz. [ABSTRACT FROM AUTHOR]

We report a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500 °C. Starting with a conventional depletion-mode HEMT sample, we found that fluoride-based plasma treatment can effectively shift the threshold voltage from -4.0 to 0.9 V. Most importantly, a zero transconductance (gin) was obtained at Vgs = 0 V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At Vgs = 0 V, the off-state drain leakage current is 28 μA/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 μm-long gate exhibit a maximum drain current density of 310 mA/mm, a peak gm, of 148 mS/mm, a current gain cutoff frequency fT of 10.1 GHz and a maximum oscillation frequency fmax of 34.3 GHz. [ABSTRACT FROM AUTHOR]

This paper reports a new category of high-Q edgesuspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-µm suspended edge in 25-µm-wide lines. [ABSTRACT FROM AUTHOR]

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region''s volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency (fT) of 21.4 GHz, the maximum frequency of oscillations (fmax) of 32.6 GHz and the collector–emitter breakdown voltage (BVCEO) of 5.6 V, which are the highest fT and the highest fTBVCEO product among the lateral bipolar transistors (LBTs). [Copyright &y& Elsevier]