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This paper presents investigation results of the probe-tip calibration impact on the BiCMOS HBT small-signal parameter measurement accuracy. Popular calibration procedures were applied on the same data set and followed by the two-step de-embedding from the device dedicated Compete-Open and Complete-Short dummy elements. Experimental results showed that the observed difference in cold HBT parameters and parameters of passive devices was minimized by the de-embedding step. The ƒ T and ƒ MAX demonstrated higher sensitivity to the probe-tip calibration residual errors.

In this article, we present and evaluate compact static thermal model parameter extraction techniques for modern silicon germanium heterojunction bipolar transistors (SiGe HBTs). We found that the model implementation of thermal resistance ( ${R}_{\text {th}}$ ) based on only junction temperature is implicit requiring time-consuming iterative procedure which may lead to potential instabilities. Dedicated extraction techniques are proposed for obtaining compact model-specific ${R}_{\text {th}}$ and its temperature coefficient. The proposed method is primarily validated on SPICE generated synthetic data. Next in order to showcase a compact model-independent verification, we also test the method using detailed thermal simulation from TCAD. Finally, we apply our extraction technique on measured data from fabricated transistors. The results are benchmarked to already obtained nominal ${R}_{\text {th}}$ values from the same device family.

International audience; The measurement of the figures of merit (FOMs) of an advanced and miniaturized transistor becomes a challenge when its fMAX goes above many hundreds of GHz. In fact, the quantities to be measured become smaller and smaller and thus the influence of the measurement environment becomes less and less negligible. Indeed, when measuring the same test structures using two different renowned commercial probes having a different topology, a “signature” of each probe can been observed, in particular, when plotting U−−√×freq ( U is the Mason gain) as a function of frequency, which is usually carried out for fMAX estimation. For millimeter wave (mmW) technologies, fMAX is the key FOM for benchmarking technologies, thus it becomes urgent to clarify this measurement. In this work, we give a proof that measurement becomes probe dependent. We constructed an accurate electromagnetic (EM) model of each probe using X-ray tomography and thus simulated the measurement environment at close proximity of the wafer using EM and SPICE simulation. Hence, each signature of the probe is clearly reproduced by the simulation, highlighting that the unexpected result is not due to an inaccuracy done by the user such as probe positioning or to a limitation of the vector network analyzer (VNA) but is the result of the unwanted coupling between the probe and the substrate or between probes and the inability of the short open load thru (SOLT) and on-wafer thru reflect line (TRL) calibration algorithms to completely remove these couplings.

In this work we present high frequency measurement results up to the WR-3 band (220-330 GHz) of test structures and a SiGe HBT calibrated with novel transmission line standards employing a meandering architecture for thru and lines, aiming to keep the inter-probe distance constant by avoiding any sort of probe displacement during measurement of the on-wafer TRL calibration standards. The measurements after TRL calibration using meander lines and straight lines are compared, as well as electromagnetic (EM) simulation.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

A concise overview on the features of the most recently released version 3.0.0 of the industry standard compact bipolar transistor model HICUM/L2 is provided. The focus here is on the development of the model over the past ten years since its detailed description in [1]. The rationales for the various extensions, their physical background and some of the code implementation peculiarities are discussed.

International audience; Terahertz (THz) silicon-based electronics is undergoing rapid developments. In order to keep this momentum high, an accurate and optimized on-wafer characterization procedure needs to be developed. While evaluating passive elements, the measured s-parameter data can be verified by a direct use of EM simulation tools. However, this verification requires to precisely introduce part of the measurement environment such as the probes, pads, and access lines to accurately predict the impact of calibration and layout for on-wafer measurements. Unfortunately, this procedure is limited to passive elements. Hence, in this work, we propose a new procedure to emulate the measurement of active devices using an electromagnetic SPICE cosimulation. By this method, one can clearly highlight that a measurement artifact that was observed for the transistor measurement can be reproduced. One of the most representative examples of measurement artifact involves the measurement and estimation of fMAX which is not constant over all frequency bands. Also, the measurement is difficult to perform above 40 GHz. This typical problem is now undoubtedly attributed to the probe-to-substrate coupling and probe-to-probe coupling which are strongly dependent on the probe geometry. Finally, this cosimulation procedure evidently underlines the need for an optimized deembedding procedure above 200 GHz.

This paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick’s law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.

In this paper, we present an in-situ thru-reflect-line (TRL) calibration and de-embedding kit that sets the reference plane in close proximity to the device under test. This is made possible thanks to the realization of the standards at the metal3 BEOL level, instead of the common meta1-8 solution. This novel calibration kit has been compared to classic TRL, both for parasitics assessment and by direct application on the active device (HBT) measurements.

The undesired behavior of the substrate significantly affects the output impedance of the device; hence degrades circuit performance mainly in the high frequency regime. Therefore, for high-speed and RF circuits, collector-substrate modeling has to be sufficiently accurate. In this paper, an improved collector-substrate equivalent circuit model is proposed. The circuit model elements are physics based and are calculated from technological data. The validity of the equivalent circuit has been verified by on-wafer measurements of an SiGe HBT fabricated in B55 technology up to 330 GHz, the highest frequency reported so far for collector-substrate modeling. The proposed substrate network can be considered as an extension of the latest large-signal HICUM model (L2v2.4).

We present and discuss in this paper the challenges and solutions to calibrate the TCAD of high-speed DPSA-SEG Si/SiGe HBTs in 55-nm BiCMOS (B55) [1]. Both fabrication process and physical device calibration are addressed using the Sprocess and Sdevice modules of Synopsys®. A careful calibration of the fabrication process in 2D-TCAD is mandatory to simulate accurately the SiGe HBT performance. The first step is to reproduce precisely the device geometry captured with TEM pictures (see Fig. 1). Additional TEM analyses performed during the fabrication may also be required to fit perfectly the final transistor. Secondly, the vertical doping profile is calibrated both from SIMS (for As, Ge and B) and EDX (for As and Ge) measurements. EDX measurements in the transistor are increasingly important to capture the variation of the 1D doping profiles with the emitter width (cf. Fig. 2). In order to reproduce this effect, the injection of defects during the SiGe:C epitaxy has been implemented in TCAD simulation. In fact, the injection of interstitials and vacancies, which depends on the silicon area exposed during the growth, influences directly the Ge diffusion of the 2D doping profile. EDX measurements are also helpful to calibrate the lateral diffusions for the 2D doping profile. Even when these vertical profiles are well calibrated, the simulation of f MAX, R BX and C BC for DPSA-SEG architecture is still challenging due to the complexity of the base link formation, which includes the faceting at the edge of SiGe:C intrinsic base and the shallow trench isolation (STI), the boron diffusion through polycrystalline / monocrystalline interface, and hidden defects. Therefore the base link formation is simplified by skipping the faceting effect and the boron diffusion through the base link interface is analyzed through inspection of R BX, C BC and f MAX i.e. by a reverse engineering approach [2]. Resulting (f T, f MAX) performance presented in Fig. 3 match the measurements for the calibrated electrical model (see below). It will be shown in the extended paper that the impact of SiGe:C epitaxy growth temperature on the base thickness is well simulated. Considering now the electrical/physical device calibration, the following physical models are used in the B55 TCAD deck: - HD parameters [3] - Bandgap (BG) of SiGe structure and bandgap narrowing (BGN) [4] - Energy and relaxation time, mobility [5] - Intrinsic carrier densities, saturation velocity [6] - Default SRH, surface SRH and Auger models from Synopsys TCAD [7] - Default Lackner model for impact ionization from Synopsys TCAD [7]. The calibration of these models for each technology node is mandatory to match the electrical measurements. A sensitivity analysis approach has been used to adjust some model parameters in order to figure out which physical model has the largest impact on the different electrical performances. The resulting map of the impacts of the different physical models, which will be presented in the extended paper, provides precious information for TCAD calibration of current and future SiGe HBTs technology at STMicroelectronics. In conclusion, obtained 2D-TCAD electrical results fit well I B, I C, f T, f MAX and BV CEOmeasurements. The accuracy of TCAD simulation will be discussed in more detail in the extended paper. References P. Chevalier et al, IEDM Tech. Dig., pp. 77-79, (2014) T. Rosenbaum, O.Saxod, V. T. Vu, D. Celi, P.Chevalier, M. Schröter and C. Maneux, Proc. IEEE BCTM, 64-67, (2015). G. Wedel and M. Schröter, Proc. IEEE BCTM, 237-244, (2010). D. B. M. Klaassen, J. W. Slotboom, H. C. De Graaff, Solid-state Electronics, 125-129 (1992) M. Michaillat, Ph.D thesis, Université Paris-Sud 11, (2010) G. Sasso, N. Rinaldi, G. Matz, C. Jungemann, Proc. IEEE SISPAD, 279-282, (2010) Sdevice documentation from Synopsis. Figure 1

International audience; This paper presents a physics-based scalable formulation for interface trap generation in the vicinity of the emitter-base spacer oxide interface in advanced SiGe HBTs. Aging tests were performed for various emitter dimensions to investigate the scalability of the dynamics of hot-carrier degradation. An improved formulation of the bond dissociation rate is also proposed incorporating a scaling rule depending on the avalanche current density. The hydrogen diffusion through the EB spacer has been modeled using an RC ladder network and has been scaled according to the hydrogen diffusion volume. Its accuracy has been validated over a wide range of aging tests and various geometry features.

This paper presents a non-destructive method to characterize the SiGe HBTs (heterojunction bipolar transistors) at very high currents/voltages, close to the functional boundaries of the transistor operation. Based on this measurement, a focus is made at high currents where the snapback behavior is observed using IC/VBE measurement setup. This analysis has been carried out for different transistor geometries. The first and second snapback locus in the IC-VCB characteristic has been discussed. A comparison of the measurements with the HICUM model shows accurate simulation results close to and even beyond the second flyback locus.

This paper presents different de-embedding methods applied in semiconductor industry, used to retrieve intrinsic device performances from high frequency S-parameters On-wafer measurement. A de-embedding method with a reduced set of dummies is proposed for conducting accurate on-wafer device measurement in the gigahertz range. The experimental results on a device characteristic up to 110GHz show that it has a comparable accuracy than a more complex one.

In this paper we study and analyze the existing techniques in literature to extract the self-heating thermal resistance from the measured DC electrical behaviour of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) focusing their dependence on device junction temperature and propose a simple extraction technique that shows superior accuracy than the existing extraction methodologies. Our approach is scalable and validated with model card simulations across different emitter geometries for a wide temperature range. We also present the applicability of our approach on measured data of a SiGe HBT fabricated in STMicroelectronics B55 process.

An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon–germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.

The cut-off frequencies of silicon-germanium hetero-junction bipolar transistors (SiGe HBTs) have entered the THz range at the cost of high current density and relatively low breakdown voltages. Typically, the common-emitter breakdown voltage with open base (BVCEO) is used to indicate the allowed breakdown voltage related operation limit. However, an open base (i.e. an infinite source impedance) is rarely encountered in actual circuits, so that BVCEO may be exceeded to a certain extent, maximal up to the open-emitter breakdown voltage BVCBO. Therefore, compact HBT models need to be accurate beyond BVCEO up to BVCBO. In this paper, the enhancement of the avalanche current implemented in the latest version of HICUM/L2 is presented. The model has been validated for different types of advanced SiGe:C HBTs over a wide range of collector-base voltages and temperatures.

In this paper we demonstrate a new and simple approach to obtain isothermal electrical characteristics of metal oxide field effect transistor (MOSFET) from conventional non-isothermal measurements. DC and continuous wave (CW) S -parameter measurements are performed at different chuck temperatures ( T chuck ). Knowing the thermal resistance ( R TH ) of the device the variation of DC and AC characteristic due to self-heating can be de-embedded and all the isothermal DC data and AC data above isothermal frequency can be determined. The method is validated by comparing the results with pulsed DC and pulsed RF measurements and found to be in good agreements.

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.

This paper describes a methodology for extracting and verifying the high-frequency model parameters of the HICUM L0 and L2 models of a silicon-germanium HBT from device and circuit measurements in the 110-325-GHz range. For the first time, the non-quasi-static effects, missing in the HICUM/L0 model, are found to be essential in accurately capturing the frequency dependence of the transistor maximum available power gain beyond the inflection frequency for unconditional stability. Furthermore, it is demonstrated that the optimal partitioning of the area and periphery components of the junction base-emitter, base-collector, and collector-substrate capacitances, and of the internal and external base and collector resistances can only be determined from S -parameter measurements beyond 200 GHz. The extracted models are validated on state-of-the-art linear and nonlinear circuits (amplifier, voltage-controlled oscillator (VCO), and VCO + divider chain) operating at frequencies as high as 240 GHz.

A new compact model approach was suggested in Part I for the low-bias base charge of homo- and heterojunction bipolar transistors. Conventional capacitance-charge formulas with dc extracted parameters were shown to provide accurate description for the Moll-Ross-Gummel charge components. New parameters were introduced to account for BGN effects and Ge doping on the temperature behavior of SiGe transistors. In this part, the implementation of the concept will be detailed for an unnormalized and a normalized heterojunction-bipolar-transistor/bipolar-junction-transistor model. Extraction methodology will be described for the new parameters, and the results will be demonstrated on advanced transistors.

A new compact model approach is suggested for the low-bias base charge of homo- and heterojunction bipolar transistors. It is shown that the junction-related (Early) components of this charge depend on an effective doping density. This concept leads to an accurate description with the conventional capacitance-charge model formulas but using different parameters directly extracted from direct-current measurements instead of the classical parameter values derived from alternating-current measurements. The temperature dependence of the low-bias base charge has also been revised, resulting in a new term added to the currently adopted temperature law. The applied novel analytic technique made it possible to determine the influence of bandgap narrowing (BGN) effects and Ge doping on the temperature behavior of SiGe transistors.

This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBT's base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external base resistance extraction and the effect of parasitic resistances is highlighted. The method has been generalized for an extraction of the base resistance specific parameters using any number of geometries (widths and lengths) and therefore demonstrates the base resistance scalability. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS SiGeC technology, and results are discussed.

Both reduction in device sizes and enhanced increase in current densities lead to concern about the impact of the self-heating effect on device electrical characteristics. Moreover, in power transistors applications, devices are connected in parallel, so thermal interaction between devices also has to be considered. In this paper, a nodal model is proposed in order to take into account temperature variation due to self-heating and thermal coupling. This model associated with the HICUM Level 2 version 2.21 compact model is validated thanks to measurements made on specific test structures.

International audience; This paper presents a novel Fully Self-Aligned (FSA) in [9]). In order to achieve this goal, the architecture is fIrstly Si/SiGe HBT architecture using Selective Epitaxial Growth evaluated and optimized by TCAD simulation before (SEG) and featuring an Epitaxial eXtrinsic Base Isolated from launching the fabrication process trials. the Collector (EXBIC). The one is integrated into the bulk area of the 28-nm FD-SOI CMOS technology developed at The fIrst part of the paper presents the fabrication process STMicroelectronics. All the parameters of the architecture such flow and the key features of the EXBIC architecture. In the as the boron-doped base link, the emitter width and height, the second part, electrical performances of this architecture pedestal oxide and sidewall thicknesses are evaluated by TCAD integrated into the bulk area part (called "NO SO" for No SOl) simulation. A low base-collector capacitance, independent from of the C28FD are systematically evaluated by TCAD the extrinsic base doping is obtained. Optimized architecture simulations. All the technological parameters of the exhibits 420 GHZ/T and 780 GHZ/MAX. architecture such as the boron in-situ doped base link, the emitter width and height, the pedestal oxide and sidewall

Due to the miniaturization in microelectronics and corresponding steep doping profiles, it is increasingly difficult to obtain reliable results from SIMS measurements. This paper aims at providing a guideline for calculating unknown profile information by means of TCAD simulations using electrical reference data. The corresponding procedure has been applied to both measurements and synthetic TCAD reference data of SiGe HBTs. An extensive geometry scalable parameter extraction was performed for obtaining reliable measured reference data of the 1D transistor. The methodology modifies the doping of the space charge regions of a 1D transistor to the extracted area related BE and BC capacitances. To adjust the internal base doping profile, measured sheet resistance, zero-bias hole charge, and area related transit time are used as reference. Furthermore, the transfer current and the normalized transconductance are very sensitive to the shape of the Germanium profile and can serve as reference. The methodology was verified with TCAD data first and then applied to measurements.

The objective of this paper is to predict the main electrical characteristics of SiGe NPN HBTs, like the transit frequency fT, internal capacitances and pinched base sheet resistance for the next CMOS nodes by means of process and hydrodynamic simulations. The as-deposited BiCMOS055 vertical doping profile is exposed to the thermal budgets from existing CMOS040, CMOS028, CMOS028FDSOI and CMOS014FDSOI technologies by TCAD simulation. Obtained results show that, thanks to the reduction of the process thermal budget, the maximum fT could reach 370 GHz with two different assumptions: identical doping level at both BE and BC junctions and identical BE capacitance. Additionally, the evolution of the dopants’ diffusion with ST's fabrication steps is clarified for BiCMOS055 in this study.

A new and simple approach for nonlinear modelling of the dynamic self-heating effect in bulk complementary metal–oxide semiconductor (CMOS) field effect transistors is presented. Low-frequency S-parameter measurements are performed in 28 nm bulk CMOS technology at room temperature between a 10 kHz and 3 GHz frequency range and the thermal impedance (Z TH) of the devices is extracted. The proposed model is validated through the measurements for different bias points. The results obtained demonstrate a reasonable agreement between theoretical prediction and experimental data.

A compact bipolar transistor model was presented in Part I that combines the simplicity of the SPICE Gummel-Poon model (SGPM) with some major features of HICUM. The new model, called HICUM/L0, is more physics-based and accurate than the SGPM but at the same time, from a computational point of view, suitable for simulating large circuits. In Part II, a parameter determination procedure is described and demonstrated for a variety of SiGe process technologies.

This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.

In this work, we present an extended version of a dc method to experimentally evaluate the base resistance R B of bipolar transistors as a function of the biasing conditions. In particular, the approach allows accurately monitoring the R B increase with collector voltage beyond the open-base breakdown voltage BV CEO up to the pinch-in occurrence. The method is successfully applied to state-of-the-art HF SiGe:C heterojunction bipolar transistors (HBTs).

Calibrated 3-D numerical simulations supported by DC experimental data are employed to quantify the impact of the key layout and technology parameters on the thermal resistance of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) so as to define proper optimization criteria. The geometry parameters of a simple scalable model are optimized to describe the thermal resistance dependence upon emitter dimensions for the HBTs under analysis.

International audience; The influence of electrothermal behaviour on radio frequency (RF) performances of 28 nm bulk complementary metal–oxide semiconductor technology is examined. Biased continuous-wave RF and pulsed RF (applying different DC pulse and RF pulse width combinations) characterisations are performed within the 1–30 GHz frequency domain at room temperature and the transit frequency (f T) is extracted at 15 GHz frequency. It has been found that the degradation in f T on I/O devices is about 3 GHz because of the self-heating effect.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz f T and 370 GHz f MAX associated with a CML ring oscillator gate delay τ D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

The accurate determination of the emitter series resistance RE has been topic for numerous investigations throughout the development of modern bipolar device technologies. A good knowledge of the parasitic resistances of the device under test is important due to the apparent voltage drops over these resistors in high current operation. Opposed to the base and collector resistance today there are no appropriate individual test structures that allow for a precise determination of the emitter resistance. In this work we present the application of a new extraction method to a recent SiGeC HBT device technology for mmW applications. The new method allows a precise parameter determination of the desired resistance values without adding additional cost for a dedicated test structure.

In device modelling and simulation the base resistance is a crucial parameter for RF characteristics such as the maximum frequency of oscillation (fmax) and noise figure (NFmin). The robustness and reliability of a well-established extraction procedure is analysed using measurement data from a state-of-the-art SiGeC HBT technology. The influence of variation of key technology parameters on the extraction flow and extracted parameters is evaluated using data from a process split. The sheet resistances obtained from the measured date are used in a simulation trial. The suitability and robustness of the method is further evaluated using synthetic data from numerical device simulation with one-dimensional test structures.

Stress investigations have been carried out on SiGe HBTs from STMicroelectronics BiCMOS9MW technology. The strain created by the stack of metal connections impacts the base bandgap of the transistors: from the reference to the denser dummies structure, a 9.1 meV bandgap energy variation is pointed out. Dummies structures were embedded for both DC and HF characterizations which showed a 25% increase for the collector current, and a 21% and 12% increase for the transit frequencies fT and fMAX respectively.

We present a method for SPICE model parameter extraction for a bipolar transistor in the active and quasisaturation modes. It uses the capabilities of the BIPOLE3 simulator to enhance the optimization procedure. Comparisons are made between the Gummel-Poon, the VBIC95, and the SGS-Thomson Microelectronics SPICE model results for I/sub C/(V/sub BE/), I/sub B/(V/sub BE/), /spl beta/(I/sub C/), f/sub T/(I/sub C/), and I/sub C/(V/sub CE/) characteristics.

The parasitic collector resistance is of high importance for device performance of HBT manufactured in advanced SiGe technologies. The external collector resistance contribution RCx is a critical modeling parameter for AC and transient operation. If the collector resistance is estimated incorrectly, the RF performance of the modeled device may significantly differ from the manufactured HBT. An advanced test structure for resistance extraction is presented and measured in two different ways. The obtained resistance values and extraction results are verified using analytical equations and quasi-three-dimensional device simulations.

This paper summarizes the technological developments carried out in STMicroelectronics to raise the fT / fMAX of SiGe HBTs up to ~ 300 GHz / 400 GHz. The noise and power performance in the W-band of different SiGe HBT generations are compared along with CML ring oscillators and circuit results up to the D band.

The base-emitter (BE) depletion charge weighting factor h jei accounts for the variation of the BE space charge region (SCR) with bias. In former HICUM model releases this weighting factor was a fixed model parameter value independent of device bias or temperature. With recent technology advancements and aggressively scaled vertical profiles incorporating significant germanium fractions a new model formulation was introduced. However the increased model complexity calls for a more sophisticated parameter extraction strategy. A novel extraction method is presented that is based on the solution of the new HICUM L2.30 formulation with the help of the Lambert W function. The extraction flow is presented and validated using a mature BiCMOS process technology available for mass-production.

This paper presents an overview of RF calibration and pad de-embedding techniques, discusses limitations and demonstrates methods for accuracy improvement applicable for the characterization of advanced BiCMOS HBTs. The impact of the reference plane location is discussed. Numerous experiments with different device geometries showed that the in-situ (on-wafer) calibration yields the most accurate results. For a probe-tip calibration, a multiple-dummy de-embedding is crucial to improve measurement accuracy. A comparison with the compact model (HICUM V2.30) confirmed the findings.

This paper describes a methodology for extracting the HICUM/L0 model of a 400-GHz SiGe HBT in the presence of strong self-heating. Good agreement is observed between measurements and simulations for DC characteristics, f T , f MAX , and Y parameters in a wide range of frequencies (DC to 170 GHz) and bias conditions. The low power capability of this process is demonstrated in a fundamental frequency 139–150 GHz VCO+16∶1 prescaler consuming less than 99 mW when operated from a 1.5V supply.

Many of today's high-frequency systems are implemented using heterojunction bipolar transistor (HBT) technology. For efficient circuit design, a compact modeling methodology for HBTs providing models with different complexity is of great interest. In particular for simulating larfe-scale circuits a simplified compact model such as HICUM/Level0 is beneficial and attractive. A methodology for generating the parameters for the simplified model from existing HICUM/Level2 parameters is introduced, and accurate modeling results with respect to experimental data over a wide temperature range are demonstrated.

This paper summarizes the work carried out to improve performances of a conventional double-polysilicon FSA-SEG SiGe:C HBT towards 400 GHz f MAX . The technological optimization strategy is discussed and electrical characteristics are presented. A record peak f MAX of 423 GHz (f T = 273 GHz) is demonstrated in SiGe:C HBT technology.

mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described and HF/DC measurements are presented and analyzed. Based on this limited set of structures a scalable de-embedding approach is described. To account for DC/HF parasitics, a sub-circuit is proposed for modeling purpose.

VDD reduction in advanced CMOS IC's push for reduced temperature stability spread of bipolar based BGR. To achieve this goal, a reliable extraction methodology for IC temperature coefficient is detailed. Based on corner lot measurements, a worst-case bipolar model is built. Bandgap circuit measurements are finally compared to statistical simulations.

This paper deals with HiCUM [1] and BSIM3V3.2.4 [2] large signal validation. On contrary with traditional approach that deals with output signal at fundamental and harmonics frequencies [3], this study focuses on IIP1 and IIP3 figures of merit (FoM). In this way, two input power tones are injected at 2 GHz and 2.1 GHz in respect with the W-CDMA receive band. Thus, not only IIP1 could be compared between simulations and measurements, but also IIP3 due to intermodulations. This analysis is based on BiCMOS SiGeC 0.25μm process for RF bipolar and CMOS transistors measurements. On the one hand, an in-house load pull system based on Maury microwaves tuners is described. This bench is used to measure the DUTs at various bias points with source and load impedances close to 50 Ω. These impedances are characterized at fundamental and at carefully chosen out-of-band frequencies. On the other hand, HiCUM and BSIM3V3.2.4 simulations are compared to measurements. DC parameters and out-of-band impedances importance is highlighted. Accurate DC parameters enable obviously a right gain simulation but above all it leads to a suitable IM3 level, and thus to a precise IIP3. Moreover, it is demonstrated that H2, H3, IM2 and IM3 out-of-band impedances characterization is a necessary and sufficient criterion to validate IIP3 FoM. Finally, it will be shown that HiCUM and BSIM3V3.2.4 models allow an accurate distortion phenomena description in terms of IIP1 and IIP3.