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AS silicon complimentary metal-oxide-semiconductor (CMOS) technology approaches its limits, new device structures and computational paradigms will be required to replace and augment standard CMOS devices for ULSI circuits. These possible emerging technologies span the realm from transistors made from silicon nanowires to heteroepitaxial layers for spin transistors to devices made from nanoscale molecules. One theme that pervades these seemingly disparate emerging technologies is that the electronic properties of these nanodevices are extremely susceptible to small perturbations in structural and material properties such as dimension, structure, roughness, and defects. The extreme sensitivity of the electronic properties of these devices to their nanoscale physical properties defines a significant need for precise accurate metrology. This paper will describe some of the most critical metrology required to characterize materials and devices in the research and exploratory stage and how these requirements would potentially change if these research devices were to start into a technology development effort. Index Terms--CMOSFETs, ferroelectric materials, ferromagnetic materials, molecular electronics, nanotechnology measurement, quantum dots, quantum wires, semiconductor device fabrication.

We demonstrate a bottom-up process for programming the deposition of coaxial thin films aligned to the underlying dopant profile of semiconductor nanowires. Our process synergistically combines three distinct methodsâ€"vaporâ€"liquidâ€"solid nanowire growth, selective coaxial lithography via etching of surfaces (SCALES), and area-selective atomic layer deposition (AS-ALD)â€"into a cohesive whole. Here, we study ZrO2 on Si nanowires as a model system. Si nanowires are first grown with an axially modulated n-Si/i-Si dopant profile. SCALES then yields coaxial poly(methyl methacrylate) (PMMA) masks on the n-Si regions. Subsequent AS-ALD of ZrO2 occurs on the exposed i-Si regions and not on those masked by PMMA. We show the spatial relationship between nanowire dopant profile, PMMA masks, and ZrO2 films, confirming the programmability of the process. The nanoscale resolution of our process coupled with the plethora of available AS-ALD chemistries promises a range of future opportunities to generate structurally complex nanoscale materials and electronic devices using entirely bottom-up methods. [ABSTRACT FROM AUTHOR]

Research describing the relationship between degradation and breakdown of ultrathin silicon dioxide is presented. In particular the effects of substrate hot hole injection are investigated.

Leakage currents and off-state power consumption for CMOS technology in the 100-nm regime are examined.

Ultrathin silicon dioxide was examined for reliability under substrate hot-electron and constant voltage tunneling stresses.

Conductance limitations in measurement of the interface state density of MOS capacitors with tunneling gate dielectrics.

Since the invention of the Esaki diode, resonant tunneling devices have been of interest for applications including multi-valued logic and communication systems. These devices are characterized by the presence of negative differential resistance in the current-voltage characteristic, resulting from lateral momentum conservation during the tunneling process. While a large amount of research has focused on III-V material systems, such as the GaAs/AlGaAs system, for resonant tunneling devices, poor device performance and device-to-device variability have limited widespread adoption. Recently, the symmetric field-effect transistor (symFET) was proposed as a resonant tunneling device incorporating symmetric 2-D materials, such as transition metal dichalcogenides (TMDs), separated by an interlayer barrier, such as hexagonal boron-nitride. The achievable peak-to-valley ratio for TMD symFETs has been predicted to be higher than has been observed for III-V resonant tunneling devices. This work examines the effect that band structure differences between III-V devices and TMDs has on device performance. It is shown that tunneling between the quantized subbands in III-V devices increases the valley current and decreases device performance, while the interlayer barrier height has a negligible impact on performance for barrier heights greater than approximately 0.5 eV. [ABSTRACT FROM AUTHOR]

A research investigating the effects of dielectric constant and barrier height on the WKB modeled tunnel currents of metal oxide semiconductor capacitors with effective oxide thickness of 2.0 mm is presented. Results show that alternative dielectrics with higher dielectric constants demonstrate lower tunneling currents than SiO2 at expected operation voltages. It was also observed that the effect of a thin layer of SiO2 on the current properties of the dielectric stack expands as the dielectric constant of an insulator increases.

The mobility behavior of MOSFET's with oxynitride gate dielectrics results from traps in the films. Gate dielectric fabrication involves the use of low-pressure rapid thermal chemical vapor deposition with SiH4, N2O, and NH3. An increase in nitrogen and hydrogen concentration reduces the peak electron mobility in n- and p-channel MOSFET's. Hole mobility decreases for all electric fields.

The rapid thermal processing, involving pre- and post-oxide deposition, improves the characteristics of composite gate oxides which act as gate dielectrics. The composite structure originating from pre-oxidation before the oxide deposition, and post-deposition oxidation in O2 and N2O, has low defect density and high mobility. N2O annealed oxides have high resistance towards hot carriers, low charge trapping capacity and low interface trap densities. The existence of nitrogen at the interface and the decreased interaction between nitrogen and hydrogen are responsible for the improved properties.

Silicon oxynitride films, formed by a low-pressure rapid thermal chemical vapor deposition (RTCVD) process, are useful as MOS gate dielectrics. The RTCVD uses SiH4, NH3 and N2O as the reactive gases. The deposition is possible at low temperatures and the films are a feasible alternative to a nitrided oxide as a gate dielectric in MOS technology. An analysis of MOS capacitors with n-channel and p-channel MOSFET's indicates an increase in fixed oxide charge with an increase in nitrogen and hydrogen content in the film.

Two-dimensional transition metal carbides are promising materials because of their potential for combining the favorable properties of transition metal carbides with the high aspect ratio of two-dimensional materials. Though commonly produced by top-down wet-chemical synthesis methods, synthesis by chemical vapor deposition is being considered because of its ability to achieve large areas, controlled layer thickness, and reduced defect density. Typically, liquid Cu is used as a synthesis substrate, though the high melting temperature of Cu (1085 °C) requires high synthesis temperatures. Thus, alternative substrates have been studied in order to reduce the necessary melting temperature. This work systematically studies the impact of synthesis parameters and substrate composition on the growth of ultrathin Mo2C (∼4–120 nm thick) by chemical vapor deposition on an In-Cu alloy. Mo2C flake size increases, and graphene/Mo2C heterostructures form with an increase in the methane flow rates. Increasing the In composition slightly decreases surface coverage and coalescence but does not appreciably impact the Mo2C flake size. Increasing In content also decreases the alloy substrate melting temperature so that a lower temperature synthesis (800 °C) can be performed. However, the necessary high temperatures for pyrolysis of methane lead to a lower limit for the synthesis temperature, similar to graphene. [ABSTRACT FROM AUTHOR]

While two-terminal HfOx (x < 2) memristor devices have been studied for ion transport and current evolution, there have been limited reports on the effect of the long-range thermal environment on their performance. In this work, amorphous-HfOx based memristor devices on two different substrates, microscopic glass (∼1 mm) and thin SiO2 (280 nm)/Si, with different thermal conductivities in the range from 1.2 to 138 W m−1 K−1 were fabricated. Devices on glass substrates exhibit lower reset voltage, wider memory window and, in turn, a higher performance window. In addition, the devices on glass show better endurance than the devices on the SiO2/Si substrate. These devices also show non-volatile multi-level resistances at relatively low operating voltages which is critical for neuromorphic computing applications. A multiphysics COMSOL computational model is presented that describes the transport of heat, ions and electrons in these structures. The combined experimental and COMSOL simulation results indicate that the long-range thermal environment can have a significant impact on the operation of HfOx-based memristors and that substrates with low thermal conductivity can enhance switching performance. [ABSTRACT FROM AUTHOR]

A detailed analysis of the extracted back gated FET mobility as a function of channel length, channel width, and underlying oxide thickness for both exfoliated and chemical vapor deposited (CVD) graphene is presented. The mobility increases with increasing channel length eventually saturating at a constant value for channel lengths of several micrometers. The length dependence is consistent with the transition from a ballistic to diffusive transport regime. The mobility as a function of channel width first increases and then decreases. The increase in mobility for very small channel widths is consistent with a reduction in edge scattering. The decrease in mobility for larger channel widths is observed to be strongly dependent on the oxide thickness suggesting that electrostatics associated with fringing fields is an important effect. This effect is further confirmed by a comparative analysis of the measured mobility of graphene devices with similar channel dimensions on oxides of different thicknesses. The observed electrical measurements are in excellent agreement with theoretical studies predicting the width dependence of conductivity and mobility. The mobility of CVD grown graphene is slightly lower than that of exfoliated graphene but shows similar trends with length and width. The mobility values reported in the literature are in agreement with the trend reported here. [ABSTRACT FROM AUTHOR]

Metal-graphene contact is a key interface in graphene-based device applications, and it is known that two types of interfaces are formed between metal and graphene. In this paper, we apply first-principles calculations to twelve metal-graphene interfaces and investigate the detailed interface atomic and electronic structures of physisorption and chemisorption interfaces. For physisorption interfaces (Ag, Al, Cu, Cd, Ir, Pt, and Au), Fermi level pinning and Pauli-exclusion-induced energy-level shifts are shown to be two primary factors determining graphene's doping types and densities. For chemisorption interfaces (Ni, Co, Ru, Pd, and Ti), the combination of Pauli-exclusion-induced energy-level shifts and hybridized states' repulsive interactions lead to a band gap opening with metallic gap states. For practical applications, we show that external electric field can be used to modulate graphene's energy-levels and the corresponding control of doping or energy range of hybridization. [ABSTRACT FROM AUTHOR]