134 results on '"Franco, Jacopo"'
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102. NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack
103. Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs
104. (Late) Essential ingredients for modeling of hot-carrier degradation in ultra-scaled MOSFETs
105. Relevance of non-exponential single-defect-induced threshold voltage shifts for NBTI variability
106. Reliability aware simulation flow: From TCAD calibration to circuit level analysis.
107. (Invited) Reliability of SiGe Channel MOS
108. Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits
109. SiGe Channel Technology: Superior Reliability Toward Ultrathin EOT Devices—Part I: NBTI
110. Toward a streamlined projection of small device bias temperature instability lifetime distributions
111. SiGe Channel Technology: Superior Reliability Toward Ultra-Thin EOT Devices—Part II: Time-Dependent Variability in Nanoscaled Devices and Other Reliability Issues
112. FrontMatter.
113. Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices
114. Impact of Individual Charged Gate-Oxide Defects on the Entire $I_{D}$–$V_{G}$ Characteristic of Nanoscaled FETs
115. The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps
116. Interface Trap Characterization of a 5.8-$\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique
117. A compact NBTI model for accurate analog integrated circuit reliability simulation
118. Off-State Degradation of High-Voltage-Tolerant nLDMOS-SCR ESD Devices
119. Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling
120. Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques
121. High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2Gate Dielectric
122. High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2 Gate Dielectric
123. Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs
124. Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors.
125. Impact of the Substrate Orientation on CHC Reliability in n-FinFETs—Separation of the Various Contributions.
126. Channel Hot Carrier Degradation Mechanism in Long/Short Channel n-FinFETs.
127. NBTI Reliability of SiGe and Ge Channel pMOSFETs With \SiO2/\HfO2 Dielectric Stack.
128. Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
129. Interface Trap Characterization of a 5.8-\\rm \AA EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique.
130. Scaling of BTI reliability in presence of time-zero variability.
131. High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2 Gate Dielectric
132. Development of Reliable Gate Stacks for Stacked MOS Devices in a 3D Sequential Integration : Ontwikkeling van betrouwbare poorten voor gestapelde MOS apparaten in een 3D sequentiële integratie
133. A multi-energy level agnostic simulation approach to defect generation.
134. Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors for BTI reliability
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