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Carbon nanotubes (CNTs) have great potential for future high-performance and energy-efficient transistor technology. To realize this potential, methods to dope the CNTs need to be developed to achieve low parasitic resistance of the transistor. Two key issues present themselves: (a) understanding the doping mechanism of the various methods and (b) stability of the doping method. For instance, although studies on molybdenum oxide (MoOx) demonstrate its ability to heavily dope nanomaterials, the interaction between MoOx and the CNT is unclear. Here, we observe an unstable effect of MoOx on the CNT and demonstrate dielectric passivation as a means to preserve the doping strength. The semiconducting CNTs exhibit greater than 103× reduction in resistance after stably doped with MoOx. By exploiting the instability of MoOx, we delve deeper into clarifying the doping mechanism. The relationship between the time-dependent material property of MoOx and the change in the electrical measurements of CNT devices is investigated to study the role of work function in doping the CNTs. We conclude that the doping mechanism of MoOx on the CNT is due to bandgap modulation by charge transfer, which occurs due to the difference in work function between MoOx and the CNT. [ABSTRACT FROM AUTHOR]

Phase Change Memory (PCM) is a leading candidate for next generation data storage, but it typically suffers from high switching (RESET) current density (20–30 MA/cm2). Interfacial Phase Change Memory (IPCM) is a type of PCM using multilayers of Sb2Te3/GeTe, with up to 100× lower reported RESET current compared to the standard Ge2Sb2Te5-based PCM. Several hypotheses involving fundamentally new switching mechanisms have been proposed to explain the low switching current densities, but consensus is lacking. Here, we investigate IPCM switching by analyzing its thermal, electrical, and fabrication dependencies. First, we measure the effective thermal conductivity (∼0.4 W m−1 K−1) and thermal boundary resistance (∼3.4 m2 K GW−1) of Sb2Te3/GeTe multilayers. Simulations show that IPCM thermal properties account only for an ∼13% reduction of current vs standard PCM and cannot explain previously reported results. Interestingly, electrical measurements reveal that our IPCM RESET indeed occurs by a melt-quench process, similar to PCM. Finally, we find that high deposition temperature causes defects including surface roughness and voids within the multilayer films. Thus, the substantial RESET current reduction of IPCM appears to be caused by voids within the multilayers, which migrate to the bottom electrode interface by thermophoresis, reducing the effective contact area. These results shed light on the IPCM switching mechanism, suggesting that an improved control of layer deposition is necessary to obtain reliable switching. [ABSTRACT FROM AUTHOR]

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energydelay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies (1,2). Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems (3,4)., CNTs are hollow, cylindrical nanostructures composed of a single sheet of carbon atoms, and have exceptional electrical, physical and thermal properties (5-7). They can be used to fabricate CNT field-effect [...]

Ferroelectric switching is demonstrated in CeO2‐doped Hf0.5Zr0.5O2 (HZCO) thin films with application in back‐end‐of‐line compatible embedded memories. At low cerium oxide doping concentrations (2.0–5.6 mol%), the ferroelectric orthorhombic phase is stabilized after annealing at temperatures below 400 °C. HZCO ferroelectrics show reliable switching characteristics beyond 1011 cycles in TiN/HZCO/TiN capacitors, several orders of magnitude greater than identically processed Hf0.5Zr0.5O2 (HZO) capacitors, without sacrificing polarization and retention. Internal photoemission and photoconductivity experiments show that CeO2‐doping introduces in‐gap states in HZCO that are nearly aligned with TiN Fermi level, facilitating electron injection through these states. The enhanced average bulk conduction, which may lead to more uniform thermal dissipation in the HZCO films, delays irreversible degradation via breakdown that leads to device failure after repeated programming cycles. [ABSTRACT FROM AUTHOR]

Several device simulation and circuit analysis approaches are employed to explain the impact of parasitic resistance and capacitance on the performance of the InGaAs high-electron mobility transistor (HEMT) digital logic circuits. The scaled HEMTs are shown to exhibit better performance, as compared to the other experimental devices.

The performance analysis of a prototype 0.25 [mu]m CMOS digital integrated circuit with select horizontal multiwall carbon nanotube (MWCNT) interconnects is presented. The developed framework is found to be powerful nanoelectronic tool that could evaluate various CNT- or nanowire-based interconnects in a realistic integrated-circuit environment.

A novel phase-change memory cell is shown by using a low-temperature in situ doped single crystalline germanium nanowire diode as a bottom electrode as well as memory-cell selection device. The heterojunction formed between in situ doped Ge nanowires and Si substrate has provided 100 * isolation for crosspoint-memory operation.

An analytical electron density of states (DOS) is derived for zigzag and armchair single-wall carbon nanotubes (CNTs). The effective mass and equilibrium carrier densities have enabled an accurate analytical description of transport and electrostatics in nondegenerate CNT devices.

A complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) is presented. Results suggest that the CNFET circuits are faster and the energy consumption per cycle and the energy-delay product is lower as compared to CMOS circuits.

A circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs) is presented. Findings reveal the projection of a 13 times capacitance voltage (CV)/current (I) improvement in the intrinsic CNFET with (19, 0) carbon-nanotube (CNT) over the bulk n-type MOSFET at the 32-nm node.

A general ballistic model was used to examine the theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs). It was observed that despite the short length scales of CNFETs devices, the current is still suppressed noticeably by SBs.

A simple, precise expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking is suggested. It was pointed that the expression includes nFET and pFET effects of an inverter, precisely captures the inverter delay performance in comparison with many CMOS technology nodes, in presence of device nonidealities and that in the circuit environment, the performance enhancement of CNFETs over Si MOSFETs is not large as judged by I sub Dsat due to the nonideal I-V features.