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The Junctionless Double-Gate (JL-DGFET) technology is potentially interesting for future ultra-scaled devices, due to the simplified manufacturing process and reduced leakage currents. In this work, we investigate, for the first time, the sensitivity to radiation of 6T SRAM cells built up of JL-DGFETs. A detailed comparison with SRAMs based on inversion-mode devices (FDSOI and IM-DGFET) is performed. Our simulations indicate that JL-DGFET SRAMs are naturally more immune to radiation than FDSOI SRAMs, but more sensitive to radiation than IM-DGFET SRAMs. [ABSTRACT FROM AUTHOR]

We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques. [ABSTRACT FROM PUBLISHER]

CERN hosts a large number of electronic devices and equipment, functioning over its different particle accelerators. In certain areas, they operate in harsh radiation environments. In order to assure their proper functionality, the equipment or some of their sensitive components undergo several tests in experimental test areas representative of the LHC radiation fields, while specialized monitors constantly record the respective radiation levels. The purpose of this study is to evaluate the use of monitors using recent technology nodes (90 nm) in order to have a better estimation of the expected error rate of the devices. The H4IRRAD experimental test area has been specifically designed to reproduce the radiation field that is present within the LHC tunnel and shielded areas. It has been used to test our custom SRAM based monitors. The monitors have been exposed to a maximum dose and high energy hadron fluence of about 76 Gy and 1.3x10^11~\cm^-2 respectively. The results show that the total ionizing dose (TID) effect does not impact the bit cross section of our devices. Moreover the Single Event occurrence is coherent to the beam intensity fluctuations, proving that these devices are appropriate for SEU monitoring under mixed particle fields. [ABSTRACT FROM PUBLISHER]

As technology scales down to nanometer, the effect of microscopic particles on semiconductor devices becomes more and more influential. In recent years, studies of device reliability gradually attract the attention of people and a lot of researches are carried out. The paper pays attention to the effect of Single Event Upset and uses the simplified RC circuit model to study the application of simplified circuit on the basis of traditional simulation. It also summarizes the law of resistance and capacitance values that changes the electrical properties at the sensitive node electrical properties of the equivalent circuit and explores the accuracy of SEU estimation using curve Id-Vd. A method of predicting the adjacent position upset in single test is proposed. According to the characteristics of experiments' Id-Vd curve, a prediction can be made by classifying them. Simulation results are compared with the prediction results, proving that they are the same and the prediction is accurate and valid. [ABSTRACT FROM AUTHOR]

This paper presents a complete design and implementation of a Single Event Upset (SEU) emulation system that can be used to inject faults Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA). The FPGA is used to implement an avionics system for a small satellite. The fault injector emulates the expected Single Event Upset (SEU) rate as it would be in the Low Earth Orbit (LEO) of the polar orbiting satellites at inclinations close to 98° deg., and altitude of about 670 km. The emulator injects faults in the configuration bit-stream of the FPGA without stopping its operation. It makes use of the partial reconfiguration feature of today's FPGAs. This provides a facility to assess the design performance in space even if radiation testing will not be conducted before launching. Also, it simulates the expected upset rate and hence calculates the corresponding data failure rates for Triple Modular Redundancy (TMR) fault tolerant designs. The system was implemented using the Xilinx Virtex- LX50T FPGA. The FPGA suffered system failures during the fault injection test. It recovered about 50% of the failures. TMR simulation at an upset rate of 0.1 upsets (per bit per second) for a data size of 2048 bits showed that about 33% of the faults will be fully corrected. [ABSTRACT FROM AUTHOR]

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (H PWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (T RA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (V DD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at V DD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (Q C) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at V DD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (T WA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at V DD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell. • This paper proposes a highly reliable radiation-hardened 13T SRAM Cell. • The proposed cell employs a differential read technique to provide a shorter read access time. • It exhibits higher Read Static Noise Margin (RSNM), which makes it read upset tolerant. • It achieves 17.8% improvement in Critical Charge, which proves its robustness against radiation hazard. [ABSTRACT FROM AUTHOR]

The single-event effect sensitivity of fourth-generation, 90 nm SiGe HBTs is investigated. Inverse-mode, \geq 1.0~\Gbps SiGe digital logic using standard, unoptimized, fourth-generation SiGe HBTs is demonstrated and the inverse-mode shift register exhibited a reduction in bit-error cross section across all ion-strike LETs. Ion-strike simulations on dc calibrated, 3-D TCAD SiGe HBT models show a reduction in peak current transient magnitude and a reduction in overall transient duration for bulk SiGe HBTs operating in inverse mode. These improvements in device-level SETs are attributed to the electrical isolation of the physical emitter from the subcollector-substrate junction and the high doping in the SiGe HBT base and emitter, suggesting that SiGe BiCMOS technology scaling will drive further improvements in inverse-mode device and circuit-level SEE. Two-photon absorption experiments at NRL support the transient mechanisms described in the device-level TCAD simulations. Fully-coupled mixed-mode simulations predict large improvements in circuit-level SEU for inverse-mode SiGe HBTs in multi-Gbps, inverse-mode digital logic. [ABSTRACT FROM PUBLISHER]

Capacitive radiation hardening by design (RHBD) techniques to reduce the single-event cross section of flip-flops are shown to be effective at highly scaled technology nodes, especially for the terrestrial environment. Test results for different values of RHBD capacitance for both 40 nm and 28 nm technology node designs show that small values of RHBD capacitance ( < 3~\fF) are effective in reducing the single-event cross section for low LET particles, neutrons, and alpha particles. Reductions of 4x, 2.5x, and 14x respectively were observed for the 28 nm designs for low LET particles, neutrons, and alpha particles, and reductions of 2.4x and 2.1x were observed for the 40 nm designs for low LET particles and alpha particles. Experimental pulse width measurement results for Xenon are used to highlight operating regions where capacitive RHBD techniques are most effective. [ABSTRACT FROM PUBLISHER]

Single Event Upset (SEU) measurements were performed on the ESA SEU Monitor using mono-energetic GeV-energy hadron beams available in the North Experimental Area at CERN. A 400 GeV proton beam in the H4IRRAD test area and a 120 GeV mixed pion and proton beam at the CERN-EU high Energy Reference Field facility (CERF) were used for this purpose. The resulting cross section values are presented and discussed as well as compared to the several hundred MeV case (typical for standard test facilities) from a physical interaction perspective with the intention of providing a more general understanding of the behavior. Moreover, the implications of the cross section dependence with energy above the several hundred MeV range are analyzed for different environments. In addition, analogous measurements are proposed for Single Event Latchup (SEL), motivated by discussed simulation results. Finally, a brief introduction of the future CHARM (CERN High-energy AcceleratoR Mixed facility) test installation is included. [ABSTRACT FROM PUBLISHER]

The aim of the research is to measure student satisfaction in Mexican Higher Education Institution using an instrument customer satisfaction at the university level . It is an exploratory study by a review of the literature about the topic. Through sampling non- probabilistic was recollected 163 data in the engineer industrial career, from which, with a preview demonstration of the adequate sample (Matrix correlation determinant=1.01E-10 and the KMO was of 0.909), was performed an analysis factor. Using a Varimax rotation, six dimensions were identifying which were called: Academic aspects, administrative aspects, complementary aspects, academic offer, environment and empathy, which explain a 67.57% of total variance. The statistical tests performed (Significant at the 5%), the fiability analysis (Cronbach Alpha>0.70), evidence the validity and fiability of the SEU instrument. [ABSTRACT FROM AUTHOR]

The effect of Gate-Source/Drain underlap ( L) on soft error performance in 30 nm common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) have been examined through extensive mixed mode-device and circuit simulations using Sentaurus TCAD. Four different 6T-SRAM topologies, one simultaneously driven double gate-FinFET and three independently driven double gate-FinFETs-based topologies namely Flex- V, Flex-PG, and PG-SN are chosen to study the geometrical parameter L and also to calculate their soft error performance. When L increases, current decreases due to increase in parasitic series resistance. The simulation results reveal that L increase in independently driven double gate-FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the L increase inside the cell, in the inverters, degrade the performance significantly. [ABSTRACT FROM AUTHOR]

SEUs in the configuration memory are the major cause of faults in SRAM-based FPGAs exposed to radiation. Most of the research about this topic focuses on studying the mechanism of random changes in the FPGA resources (logic blocks, flip-flops, IO, and interconnection network) for their impact on the overall device reliability and fault analysis, while much less effort has been spent in evaluating the effects of SEUs on power consumption. In this paper, we present a detailed analysis of the power consumption of a Xilinx Virtex 5 LX50T on the CORE, AUX, MGT and IO domains during irradiation with 62-MeV proton beams. The tests have been performed at the Superconductive Cyclotron of the LNS-INFN facility (Catania, Italy). Changes in power consumption (most notably in the logic core) are experienced. We present an analysis of the current trends and the results of fault injection tests, on the programmable routing resources, aimed at confirming or excluding possible fault mechanisms for the SEU-induced current variations. [ABSTRACT FROM AUTHOR]

The goal of this work is to develop a methodical approach for analytical soft error sensitivity analysis in SRAM-based FPGAs. Compared to other non-destructive techniques, the proposed approach can be applied very early in a design flow. This is achieved by extracting information about an application under development from high level models (e.g. C/C++ descriptions or Matlab Simulink models) and then invoking pre-established libraries where other information related to soft error sensitivity of primitive components are stored beforehand. Our library-based approach is validated by comparing our early estimation results to those obtained through synthesis, placement and routing of complete designs, for two different ways of estimating the number of potentially critical configuration bits. We first explore two different design architectures for implementing Finite Impulse Response filters. The design architectures are explored under two different implementation options, for a Xilinx Virtex-5 FPGA: LUT based and DSP48E block based. Then we apply our estimation technique on a more complex design. namely a GMSK demodulator. Results show that the worst case relative error, caused by our estimation technique with respect to the results obtained after synthesis, placement and routing is 7,2 %, and in most cases, it is less than 5 %. Mean time between failures are provided for the different design architecture and implementation options, to illustrate how our technique can help designers make early choices to build more reliable designs without performing the whole implementation, as our early estimation results are close to those obtained later in the design process. [ABSTRACT FROM AUTHOR]

Single Event Upset (SEU) measurements were performed using the European Space Agency's (ESA) Standard SEU Monitor in the H4 Irradiation mixed-field test area at CERN. The results, tightly correlated with the radiation environment, are compared with those obtained with the CERN Radiation Monitors (RadMons) as well as with the Monte Carlo simulation of the experimental setup using the FLUKA Monte Carlo transport code. In addition, the SEU cross section of the device for particles and energies not available in standard testing (such as charged pions or GeV-energy hadrons) are simulated and discussed, showing an increase of over a factor 2 for nucleons in the 200 MeV–3 GeV range. A monoenergetic SEU cross section measurement at 120 GeV is included in the analysis. [ABSTRACT FROM AUTHOR]

In this work, a method is proposed for obtaining comparable measurements of the SEU sensitivity in reprogrammable devices that present different characteristics like internal architecture, technology, amount of available resources, etc. A specific minority checker is developed for reporting the presence of SEUs or MBUs which will help in this comparing task during dynamic tests. [ABSTRACT FROM AUTHOR]

In this paper are described measurements at high-altitude of both radiation environment and effects. These measurements comprise cosmic ray neutrons and SBU/MCU on nanoscales devices. Results obtained at Pic-du-Midi, France, and in the city of Puno, Peru, are presented and analyzed. Analyses and cross comparisons based-on MUSCA SEP^3 calculations show a good agreement between experimental data and modeling, thus illustrating the importance of the knowledge of the radiation field for a reliable prediction. [ABSTRACT FROM AUTHOR]

Copyright of Historia y Politica: Ideas, Procesos y Movimientos Sociales is the property of Departamento De Historia del Pensamiento y de los Moviemientos Sociales y Politicos (Madrid) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Evaluating the sensibility of a given circuit with respect to soft errors became a main issue especially if it is intended to operate in space or at high altitudes. A hardware/software (HW/SW) approach to study the effects of soft errors by fault injection in the VHDL model of a CPU (Control Processor Unit) is presented and illustrated by results obtained for a LEON3 processor. The LEON3 is set to execute two benchmark algorithms. The first one is a typical 3x3 matrix multiplication, whereas the second one is a self-converging algorithm which is intended to provide correct results even if a failure occurs in the middle of the execution. The results of fault-injection campaigns targeting the register file unit of the processor are compared to those issued from a state-of-the-art method, the C.E.U. (Code Emulated Upset). One of the main advantages of the proposed method is the larger targeted Single Event Upset (SEU) sensitive area leading to improved error rate predictions. [ABSTRACT FROM AUTHOR]

Nowadays, microprocessor-based system's robustness under Single Event Effects (SEEs) represents a very important concern. A widely adopted solution to make a microprocessor-based system robust consists in modifying the application code by adding redundancy and fault tolerance capabilities. In this context, the main idea behind this paper is to evaluate a software-based technique named Optimized Embedded Signature Monitoring (OESM) using an FPGA-based fault injection technique, which is able to inject a high number of Single Event Upsets (SEUs) and Single Event Transients (SETs) in a short period of time. The obtained results demonstrated not only the increase of system's robustness level, but also point out the remaining weak areas in the microprocessor-based system with respect to both types of SEEs. [ABSTRACT FROM AUTHOR]

As technology scales, the protection of Finite State Machines' (FSMs) states against single event upset (SEU) and multiple bit upsets (MBUs) becomes more difficult. In this paper, a self-checking approach to enhance the SEU/MBUs immunity of FSMs' states by replicating One-Hot code M times for state encoding is presented. This approach can correct less than M bit-flip faults in the state register per cycle. Bit-flips are treated as random events and modeled by applying Poisson distribution. Two characteristics of this approach are obtained through probability analysis: first, this approach performs better with the increase of M, whereas worse when an FSM contains more states; second, this approach can offer more enhanced reliability than Binary or One-Hot state encoding with Triple Modular Redundancy (TMR). The former characteristic leads to the further improvement of this approach which is called state-reforming. The reliabilities of this proposed approach and its state-reformed solutions, as well as One \mathchar"702D Hot +TMR are all evaluated through simulations of fault injections. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes. [ABSTRACT FROM AUTHOR]

Through revising the process of charge collection for reversed drain-bulk junction, a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS. The model can capture the plateau effect, and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation. Considering the case of connecting load, it is still valid. For combination and sequential logic circuits, the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations. [ABSTRACT FROM AUTHOR]

A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (t ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab's XLP 0.15 µm fully-depleted SOI CMOS technology--a process optimized for subthreshold operation. At the Cyclotron Institute at Texas A&M University, all four cells were subjected to heavy ion characterization in which the circuits were dynamically updated with alternating data and then checked for SEUs at both subthreshold (450 mV) and superthreshold (1.5 V) levels. The proposed flip-flop never failed, while the traditional and DICE designs did demonstrate faulty behavior. Simulations were conducted with the XLP process and the proposed flip-flop provided an improved energy delay product relative to the other non-faulty rad-hard flip-flop at subthreshold voltage operation. According to the XLP models operating in subthreshold at 250 mV, performance was improved by 31% and energy consumption was reduced by 27%. [ABSTRACT FROM AUTHOR]

Magnetic RAM (MRAM) is considered as a promising nonvolatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. Thanks to its fast speed, easy integration with CMOS and infinite endurance, MRAM has been proposed to build up nonvolatile latches and logic circuits to overcome the power challenge of conventional CMOS circuits. However, they are vulnerable to single event effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are described in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on configurable logic block (CLB) to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness and performance. [ABSTRACT FROM AUTHOR]

This paper reports the effects of Gamma dose irradiation on 25 nm Omega FinFET. Study of multiple gates Omega FinFET that has a good control over body potential is an interesting and motivating structure for analyzing Gamma radiation effects concerning radiation hardened applications. By the virtue of its geometry, it should be less susceptible to the radiations as compared to single gate or double gate technologies. Omega FinFET is three dimensional in nature and therefore any meaningful process or device simulation must be performed in three dimensions. Quantum effects play major role in nano scaled devices. The impact of quantum confinement effects on the response of 25 nm Omega FinFET to Gamma irradiation is investigated using 3D quantum simulations. Results for classical and quantum transport models under low and high drain bias are compared. Gamma irradiation is performed for dose variation from 100 Krad (low injection regime) to 10 Mrad (high injection regime). Effect of irradiation on band structure, electron/hole density, total current density, mobility, fields, potential, electron temperature and generation recombination rate are computed. Disparity among quantum and classical transport results show that it is necessary to include quantum effects. As compared to single gate technologies parameters do not degrade appreciably after irradiation. [ABSTRACT FROM AUTHOR]

Abstract: Particle radiation effects are a fundamental problem in the use of numerous electronic devices for space applications, which is aggravated with the technology shrinking towards smaller and smaller scales. The suitability of low-energy accelerators for irradiation testing is being considered nowadays. Moreover, the possibility to use a nuclear microprobe, with a lateral resolution of a few microns, allows us to evaluate the behavior under ion irradiation of specific elements in an electronic device. The CEICI is the new CEnter for Integrated Circuits Irradiation tests, created into the facilities at the Centro Nacional de Aceleradores (CNA) in Sevilla-Spain. We have verified that our 3MV Tandem accelerator, typically used for ion beam characterization of materials, is also a valuable tool to perform irradiation experiments in the low LET (Linear Energy Transfer) region. [Copyright &y& Elsevier]

This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of a MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions may lead designers into developing more efficient techniques to detect these types of faults. [ABSTRACT FROM AUTHOR]

The thermal neutron SEU cross-section of the Toshiba SRAM memory used in the LHC RadMon system was measured at different voltages. A method using the difference in its response compared to mixed particle energy field is proposed to be used as a discriminator between thermal neutron and high-energy hadron fluences. For test purposes, the proposed method was used at the CNGS and CERF facilities to estimate the field composition by counting SEUs at two different voltages and the results were compared to simulations. [ABSTRACT FROM AUTHOR]

FLUKA Monte Carlo simulations have been performed to identify particle energy spectra and fluences relevant for evaluating the risk of single event effects in electronics installed in critical LHC underground areas. Since these simulations are associated with significant uncertainties, the results will compared with an online monitoring system installed to evaluate radiation levels at the location of the electronics. This comparison approach have been benchmarked in a mixed field reference facility and for a preliminary LHC monitoring case study. [ABSTRACT FROM AUTHOR]

Abstract: In this research paper, a 3D process simulation of 25nm n-channel Ω-FinFET and the effect of Gamma radiation on device characteristics have been studied. Device simulations are carried out under the influence of Gamma radiation under varying does conditions from 100Krad (SiO2) to 10Mrad (SiO2). Effects of Gamma radiation on the threshold voltage, transfer characteristics, drive current, off-state leakage current and subthreshold characteristics have been studied. Extracted parameters for virgin and irradiated devices have been compared in order to understand the degradation in the electrical characteristics of the Ω-FinFET under study. Simulation results under the low drain and high drain bias has been reported and discussed. It is found that Ω-FinFET delivers better performance under irradiation as compared with conventional single gate MOS structures. Ω-FinFET is shown to be significantly tolerant to gamma radiation upto dose of 5Mrad (SiO2). In addition, the influence of quantum effects on this nanoscale device is investigated in detail. Sentaurus simulation results obtained has been compared with the reported experimental data. [ABSTRACT FROM AUTHOR]

This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm^2 die, employing 1.2B transistors in a 45~nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 \mum^2 DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning. [ABSTRACT FROM AUTHOR]

Abstract: The measurement of the neutron fluence produced inside a radiotherapy installation has been a matter of concern specially in the photon high megavoltage modalities. Until now, due to the pulsed nature of the beam and the high photon fluence inside the radiotherapy room, only passive methods were considered reliable. In this work we describe a neutron detector, based on neutron sensitive SRAM devices, that can operate inside the treatment room and is insensitive to the scattered photon fluence. This device has been used to estimate the neutron production and the patient exposure to neutrons in several clinical installations with different linac commercial models. The detection principle is based on the production of Single Event Upset (SEU) of memory states on modern sub-micron technology SRAMs. Spectral sensitivity was initially studied using low energy neutron shielding (boron and cadmium layers) and later using dedicated calibration neutron beams. With a 3mm thick flex–boron shield, the SEU rate was reduced to around 5% of the unshielded rate, demonstrating that the dominant contribution of the SEU cross section of the chosen SRAM was due to low energy neutrons. The total memory size was scaled to obtain a response repeatability with relative typical uncertainty of about 2% for 1000 Monitor Units (MU) in a 15MV accelerator facility with excellent linearity with MU. The sensitivity of this digital detector is around 0.3 μSv H∗(10) per event and considering the signal to fluence ratio around 2×10−4 event cm2. [ABSTRACT FROM AUTHOR]

We investigate the efficacy of mitigating radiation-based single event effects (SEE) within circuits incorporating SiGe heterojunction bipolar transistors (HBTs) built with an N-Ring, a transistor-level layout-based radiation hardened by design (RHBD) technique. Previous work of single-device ion-beam induced charge collection (IBICC) studies has demonstrated significant reductions in peak collector charge collection and sensitive area for charge collection; however, few circuit studies using this technique have been performed. Transient studies performed with Sandia National Laboratory's (SNL) 36 MeV ^16O microbeam on voltage references built with N-Ring SiGe HBTs have shown mixed results, with reductions in the number of large voltage disruptions in addition to new sensitive areas of low-level output voltage disturbances. Similar discrepancies between device-level IBICC results and circuit measurements are found for the case of digital shift registers implemented with N-Ring SiGe HBTs irradiated in a broadbeam environment at Texas A&M's Cyclotron Institute. The error cross-section curve of the N-Ring based register is found to be larger at larger ion LETs than the standard SiGe register, which is clearly counter-intuitive. We have worked to resolve the discrepancy between the measured circuit results and the device-level IBICC measurements, by re-measuring single-device N-Ring SiGe HBTs using a time-resolved ion beam induced charge (TRIBIC) set-up that allows direct capture of nodal transients. Coupling these measurements with full 3-D TCAD simulations provides complete insight into the origin of transient currents in an N-Ring SiGe HBT. The detailed structure of these transients and their bias dependencies are discussed, together with the ramifications for the design of space-borne analog and digital circuits using SiGe HBTs. [ABSTRACT FROM AUTHOR]

In this article, a fault-tolerant network-on-chip (NoC) router architecture is introduced. This article reports a comprehensive fault study of a NoC router through a simulation-based method. The evaluation of single-event transient (SET), crosstalk and single-event upset (SEU) fault injections shows that up to 53% of the injected faults cause a system failure. About 45% of them are replaced by new values before turning into errors and almost 1% of them are treated as latent errors. According to the experimental results, routing units and switch components are known as the two most unstable elements with regard to transient injected faults, with failure rates of 60% and 55%, respectively. Moreover, the effects of SETs are greater in all components. The SEUs also have a tangible effect on the functionality of the routing unit. Using column parity row selection method as an SEU-tolerant one in the routing unit and an innovative SET-crosstalk-tolerant technique in the switch components has mitigated the total failure rate down to 38%. The synthesis of fault-tolerant architecture requires almost 22% more area than the non-tolerant architecture. The proposed fault-tolerant method consumes almost 27% less dynamic power than a Hamming triple modular redundancy method. [ABSTRACT FROM AUTHOR]

This paper presents the SEU& MCU detected by several dedicated memories of the instrument ICARE (on-board the Argentinean satellite SAC-C) from November 2000 to May 2009. The correlation between SEU rate and the space environment is shown along with the evolution of the geomagnetic cutoff, the geographical dependence of the MBU multiplicity inside the SAA is also shown. Moreover, the output of MUSCA SEP³ (SEE prediction code) has been compared with in-flight data obtaining a good match. [ABSTRACT FROM AUTHOR]

A proprietary Monte-Carlo simulation code dedicated to heavy ion cross-section prediction has been developed. The code is based on diffusion-collection equations, takes into account recombination processes, uses an improved drain strike model, and includes new upset analysis algorithms for different circuit architectures. Simulated cross-sections are compared to heavy ion experimental characterizations for commercial bulk 65-nm single- and dual-port SRAMs. Simulation capabilities of much more complex circuits are demonstrated considering a 65-nm radiation-hardened-by-design (RHBD) Flip-Flop (FF). [ABSTRACT FROM AUTHOR]

In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to locate weak areas. autonomous emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to a PIC18 microprocessor, while executing three different workloads. A 80 million fault campaign has been performed, and results show that a failure rate lower than 1% can be obtained by hardening a 24% of the circuit flip-flops, for the given applications. [ABSTRACT FROM AUTHOR]

Copyright of Spagna Contemporanea is the property of Viella Editrice srl and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

We investigate, for the first time, the potential for SEE mitigation of a newly-developed device architecture in a 3rd generation high-speed SiGe platform. This new device architecture is termed the "inverse-mode cascode SiGe HBT" and is comprised of two standard devices sharing a buried subcollector and operated in a cascode configuration. Verification of the TID immunity is demonstrated using 10 keV X-rays, while an investigation of the SEE susceptibility is performed using a 36 MeV16O ion. IBICC results show strong sensitivities to device bias with only marginal improvement when compared to a standard device; however, by providing a conductive path from the buried subcollector (C-Tap) to a voltage potential, almost all collected charge is induced on the C-Tap terminal instead of the collector terminal. These results are confirmed using full 3-D TCAD simulations which also provides insight into the physics of this new RHBD device architecture. The implications of biasing the C-Tap terminal in a circuit context are also addressed. [ABSTRACT FROM AUTHOR]