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This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption., This research was funded by the Spanish Ministerio de Economía y Competitividad (MINECO), Grant TEC2015-66002-R (MINECO/FEDER). We also acknowledge financial support from the State Agency for Research of the Spanish Ministry of Science and Innovation through the “Unit of Excellence María de Maeztu 2020-2023” award to the Institute of Cosmos Sciences (CEX2019-000918-M).

We present an array of $16 \times 16$ single-photon avalanche diodes (SPADs) with 16 shared 6 ps time-to-digital converters (TDCs), designed for non-line-of-sight imaging. It features a timing jitter of 60 ps (FWHM), fast-gated capabilities and up to 1.6·108 photon time-tagging measurements per second.

Indolamines are tryptophan-derived specialized metabolites that belong to the huge and ubiquitous indole alkaloids group. Serotonin and melatonin are the best-characterized members of this family, given their many hormonal and physiological roles in animals. Following their discovery in several plant families, the study of plant indolamines has flourished over the last few decades and their involvement in many important processes has been proposed, including stress responses, growth and development, and reproduction, leading to their classification by some authors as a new category of phytohormones. However, the complex puzzle of the indolamines is far from resolved, particularly the biological roles of tryptamine, the early tryptophan-derived serotonin precursor representing the central hub of downstream plant indolamines and many specialized indole alkaloids. Tryptophan decarboxylase, which catalyzes the synthesis of tryptamine, appears to strictly regulate the flux of carbon and nitrogen from the tryptophan pool into the indolamine pathway. Furthermore, tryptamine accumulates to high levels in the reproductive organs of many plant species, and therefore cannot be classed as a mere intermediate but rather as an end product with potentially important functions in fruits and seeds. This review summarizes current knowledge on the role of tryptamine and its close relative serotonin, emphasizing the need for a clear understanding of the functions of, and mutual relations between, these two indolamines and their biosynthesis pathways in plants.

Phase-locked loops are one of the most significant modules that are used not only for communication circuits but also in other fields like biomedical and computer sciences. There are many types of PLLs such as Analog, Digital, and Software-based ones. However, they have advantages and disadvantages among each other, and All-Digital PLLs have many significant features like programmability and cost efficiency that make them stand out from the rest. Independent from the topology, all PLLs synthesize an output signal whose frequency is proportional to the phase or time difference between input signals. When the alignment between phases is achieved, PLL enters the "locked state". In other words, the frequency of the output signal becomes the same as the input signal. The first step of the phase-locking process is measuring the time distance between incoming signals which are known as Reference and Feedback signals. Different PLL types employ different subblocks to measure phase difference. Due to taking advantages of the digital domain extensively, All-Digital Phase-Locked Loops converts phases of the incoming signals to time and computes the difference between arrival times in terms of known reference. In this thesis, a hybrid time to digital converter with 22.18 ps resolution was designed in 180 nm XFAB technology. The overall working principle was divided into two parts as fine and coarse measurement. Then the top module was verified in Verilog first, and subsequently, behavioral Verilog codes were transformed to gate level ones by RC synthesis. After taking preliminary results in ModelSim, the schematic level of the prototype was synthesized in Cadence Virtuoso software with a pre-designed Standard Cell library. The average current consumption during the error measurement was obtained as 3.9 mA from a 1.8 V supply. After functional and periodic tests, the proposed TDC was tested across corners with ±10% supply voltage variation. Moreover, the same tests were performed for different temperatures from -200 oC to 85 oC degrees. When all tests were completed successfully, the layout of the proposed TDC was done in a 0.057 mm2 area and verified with Mentor Calibre. As the last step, parasitic extraction was performed from layout to observe the effects of parasitics in post-layout simulations. Faz kilitli döngüler (çevrimler), sadece iletişim devreleri için değil, biyomedikal ve bilgisayar bilimleri gibi diğer alanlarda da kullanılan en önemli modüllerden biridir. Analog, Dijital ve Yazılım tabanlı gibi birçok faz kilitli döngü türü mevcuttur ve bu türlerin birbirlerine göre avantaj ve dezavantajları vardır. Tüm Dijital faz kilitli döngüler, programlanabilirlik ve maliyet verimliliği gibi onları diğerlerinden ayıran birçok önemli özelliğe sahiptir. Topolojiden bağımsız olarak, tüm FKÇ' ler, frekansı giriş sinyalleri arasındaki faz veya zaman farkıyla orantılı olan bir çıkış sinyali sentezlemektedir. Fazlar arası uyum sağlandığında FKÇ "kilitli duruma" girer. Başka bir deyişle, çıkış sinyalinin frekansı giriş sinyali ile aynı olur. Faz kilitleme işleminin ilk adımı, Referans ve Geri Besleme sinyalleri olarak bilinen gelen sinyaller arasındaki zaman mesafesini ölçmektir. Farklı FKÇ türleri, faz farkını ölçmek için farklı alt bloklar kullanır. Dijital alanın avantajlarından kapsamlı bir şekilde yararlanmak için Tüm Dijital Faz Kilitli Döngüler, gelen sinyallerin fazlarını zamana dönüştürür ve bilinen referans açısından varış süreleri arasındaki farkı hesaplar. Bu tezde, 180nm XFAB teknolojisinde 22.18 ps çözünürlüğe sahip hibrit bir zamandan dijitale dönüştürücü tasarlanmıştır. Genel çalışma prensibi, ince ve kaba ölçüm olarak iki kısma ayrılmıştır. Daha sonra Verilog 'da ilk önce üst modül doğrulanmış ve ardından davranışsal Verilog kodları, RC sentez aracı ile "kapı düzeyi" kodlara dönüştürülmüştür. Model Sim'de öncü sonuçlar alındıktan sonra, prototipin şematik seviyesi, önceden tasarlanmış bir Standart Hücre kütüphanesi ile Cadence Virtuoso yazılımında sentezlenmiştir. Hata ölçümü sırasında 1,8 V besleme gerilimi kullanılarak, ortalama akım tüketimi 3.9 mA olarak elde edilmiştir. Fonksiyonel ve periyodik testlerden sonra, önerilen dönüştürücü, ±%10 besleme gerilimi değişimi ile köşe simülasyonlarında test edilmiştir. Ayrıca -200 oC 'den 85 oC 'ye kadar farklı sıcaklıklar için aynı testler tekrar edilmiştir. Tüm bu simülasyonlar başarıyla tamamlandığında, önerilen TDC'nin serimi 0.057 mm2 alan kapsayacak şekilde tasarlanmış ve sonuç Mentor Calibre ile doğrulanmıştır. Son adım olarak, parazitlerin etkilerini gözlemlemek için serim-sonrası parazitik ekstraksiyon simülasyonu koşturulmuştur.

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall. A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL$\leq$1.3 LSB, an INL$\leq$2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.

Nowadays, many applications require the measurement of a time interval: while a coarse timing information down to the nanoseconds range can be easily obtained with a counter, achieving a precision in the order of few picoseconds require more complex circuits, especially if high linearity and operating rates up to tens of Mcps are also necessary. In this paper, we show preliminary results on a new fully integrated time to amplitude converter designed in 350nm Si-Ge technology. The circuit is able to provide a timing precision as low as 4.3ps rms on a 12.5ns full scale range and a linearity better than 1% rms.

This research paper proposes a critical approach to learning a musical instrument in people with dyspraxia. It discusses various questions such as decryption and memorization of score, the teacher’s role, the need or not for adequate education material or even the omnipresence of imitation learning in the teaching of instrumental practices. Furthermore, this research highlights the significant differences that exist between persons with developmental coordination disorder (DCD) and people with typical brain development during learning a piece of music.; Le présent mémoire propose une approche critique de l’apprentissage d’un instrument de musique chez des personnes dyspraxiques. Il aborde différentes problématiques comme le déchiffrage et la mémorisation de partition, le rôle de l’enseignant, la nécessité ou non de supports pédagogiques adaptés ou encore l’omniprésence des apprentissages par imitation dans la transmission des pratiques instrumentales. Par ailleurs, ce travail de recherche souligne les différences significatives qui existent entre les personnes atteintes d’un trouble développemental des coordinations (TDC) et les individus à développement « typique » lors de l’apprentissage d’une pièce musicale.

This research paper proposes a critical approach to learning a musical instrument in people with dyspraxia. It discusses various questions such as decryption and memorization of score, the teacher’s role, the need or not for adequate education material or even the omnipresence of imitation learning in the teaching of instrumental practices. Furthermore, this research highlights the significant differences that exist between persons with developmental coordination disorder (DCD) and people with typical brain development during learning a piece of music.; Le présent mémoire propose une approche critique de l’apprentissage d’un instrument de musique chez des personnes dyspraxiques. Il aborde différentes problématiques comme le déchiffrage et la mémorisation de partition, le rôle de l’enseignant, la nécessité ou non de supports pédagogiques adaptés ou encore l’omniprésence des apprentissages par imitation dans la transmission des pratiques instrumentales. Par ailleurs, ce travail de recherche souligne les différences significatives qui existent entre les personnes atteintes d’un trouble développemental des coordinations (TDC) et les individus à développement « typique » lors de l’apprentissage d’une pièce musicale.

A pulse width-controlled CMOS pulser for a semiconductor laser diode (LD) and a time-gated time-resolved 8×4 single-photon avalanche diode array with a time-to-digital converter (TDC) were designed on a single integrated circuit and simulated by using a 150 nm technology. The pulse width of the driving current can be adjusted from 0.5 ns to 2.5 ns with a resolution of 100 ps. The start time of the time-gating can be adjusted over a dynamic range of 4.8 ns with a resolution of 100 ps and, furthermore, a 121 ps time-gating can be achieved. The returning photons are detected by the TDC with a resolution of 50 ps and stored to the 128 14-bit counters for merging to the distribution time-of-flight histogram. The average power consumption of the whole system was 377 mW at a repetition rate of 10 MHz.

V sklopu tega magistrskega dela smo se lotili izdelave hitrega časovno-digitalnega pretvornika visoke ločljivosti na cenovno dostopni plošči Red Pitaya, ki temelji na zmogljivem polno programirljivem čipu Xilinx Zynq 7010. Časovno-digitalni pretvornik (TDC) je popolnoma digitalen in v celoti implementiran na programirljivem polju vrat (FPGA) v ravnokar omenjenem čipu, tako da za opravljanje meritev ne potrebujemo nobenih dodatnih zunanjih komponent. TDC je bil zasnovan po principu časovne interpolacije, kjer čas štejemo z uporabo sinhronega binarnega števca, za zelo natančno določitev časa prihoda med urinimi cikli pa skrbi integrirana zakasnilna linija. Posamezen kanal TDC je na voljo v obliki strojne komponente intelektualne lastnine (jedra IP) z vmesnikom AXI, kar je zelo priročno za gradnjo večkanalnih sistemov. Procesni sistem Zynq bere časovne značke aktivnih časovno-digitalnih pretvornikov in jih preko omrežja Ethernet pošilja odjemalcu, recimo osebnemu računalniku, kjer jih lahko ustrezno obdelamo in prikažemo v grafičnem uporabniškem vmesniku. V sklopu tega magisterija smo implementirali dva kanala TDC in ju podrobno okarakterizirali. Posamezen časovno-digitalni pretvornik teče na frekvenci 350~MHz in je ob mrtvem času $sim$14~ns sposoben vzorčiti do 70 milijonov značk na sekundo. Časovna ločljivost posameznega kanala dosega odličnih 11~ps in ostane zelo visoka tudi pri večjih časovnih intervalih, vsaj nekje do 100~ns. Izkazalo se je, da lahko tudi s povsem običajnimi signali s hitrostjo naraščanja 10~ns opravljamo meritve visoke ločljivosti, prav tako pa je meritev robustna na spremembe temperature. Izdelani TDC je zelo natančen in periodo zunanjega signala izmeri z relativno natančnostjo $10^{-5}$ v 60 stopinj širokem temperaturnem intervalu. Nazadnje smo inštrument preizkusili še v realistični postavitvi s pulznim laserjem in hitro silicijevo fotopomnoževalko (SiPM), kjer se je novi TDC odlično obnesel. Vse to dokazuje, da se da z izbiro primerne arhitekture in modernega čipa FPGA tudi na cenovno zelo dostopnih platformah, kot je Red Pitaya, implementirati izredno zmogljiv časovni merilni inštrument, ki je uporaben tako za študente kot profesionalne raziskovalce. This Master’s Thesis presents an implementation of a fast high-resolution time-to-digital converter (TDC) on the affordable Red Pitaya board, featuring a powerful all programmable Xilinx Zynq 7010 SoC. The design is fully digital, enabling the TDC to be implemented entirely within the Zynq FPGA, thus requiring no additional external components. The architecture of the TDC is based on the time interpolation technique which employs a coarse binary counter and a tapped delay line for fine time measurements between adjacent clock cycles. A TDC channel is packaged into an AXI-interfaced IP core, making it easy to build multichannel systems. Produced timestamps from active TDC channels are read by the Zynq processing system and sent via Ethernet to a client, for example a PC which can process and display them with a graphical user interface. A two-channel TDC system has been implemented and thoroughly characterized during this Thesis work. An individual channel runs at 350~MHz and has a dead time of $sim$14~ns, sampling up to 70 million timestamps per second. Its time resolution can reach an astounding 11~ps and remains very high even at larger time intervals of up to 100~ns. It turned out that high-resolution measurements can also be done with standard 10~ns rise time signals and with widely varying temperatures. The implemented TDC is very accurate and can measure the period of an externally applied signal with relative accuracy of $10^{-5}$ over a 60 degree temperature swing. Finally, the instrument was put to the test in a realistic setup with a pulsed laser and a fast silicon photomultiplier (SiPM), where the new TDC performed exceedingly well. This concludes that by choosing the right architecture and a modern FPGA, a very powerful time measurement instrument, useful both for students and professionals, can be implemented on perfectly affordable hardware platforms such as the Red Pitaya.

Pancreatic ductal adenocarcinoma (PDAC) is characterized by an infiltrative growth pattern with intense desmoplastic stroma comprised of cancer-associated fibroblasts (CAFs). Additionally, the histological characteristics are considered to play a vital role in the poor prognosis of PDAC. However, the density of cancer cells, degree of desmoplasia and vascular proliferation varies in individual cases. We hypothesized that preoperative radiological images would reflect histological characteristics, such as cancer cell density, CAF density and microvessel density. To clarify the association between the histological characteristics and radiological images of PDAC, the cancer cell density, CAF density and microvessel density from surgical specimens were measured with immunostaining, and the time density curve of dynamic contrast-enhanced computed tomography (CECT) was analyzed. Overall, the initial slope between non-enhanced and arterial phases was correlated with microvessel density, and the second slope between arterial and portal phases was correlated with CAF and cancer cell densities. In conclusion, the present study suggested the possibility of estimating cancer cell, CAF and microvessel densities using the TDC of dynamic CECT.

Melatonin improves the tolerance of plants to various environmental stresses by protecting plant cells against oxidative stress damage. The objective of the current study was to determine whether exogenous melatonin (MT) treatments could help protecting peanut (Arachis hypogaea) seedlings against salinity stress. This was achieved by investigating enzymatic and non-enzymatic antioxidant systems and the expression of melatonin biosynthesis related genes in response to salinity stress with or without exogenous MT. The results showed a significant increase in the concentrations of reactive oxygen species (ROS) in peanut seedlings under salinity stress. The exogenous application of melatonin decreased the levels of ROS through the activation of antioxidant enzymes in peanut seedlings under salinity stress. Transcription levels of melatonin biosynthesis related genes such as N‐acetylserotonin methyltransferase (ASMT1, ASMT2, ASMT3), tryptophan decarboxylase (TDC), and tryptamine 5‐hydroxylase (T5H) were up-regulated with a 150 &micro, M melatonin treatment under salinity stress. The results indicated that melatonin regulated the redox homeostasis by its ability to induce either enzymatic or non-enzymatic antioxidant systems. In addition, phylogenetic analysis of melatonin biosynthesis genes (ASMT1, ASMT2, ASMT3, TDC, T5H) were performed on a total of 56 sequences belonging to various plant species including five new sequences extracted from Arachis hypogaea (A. hypogaea). This was based on pairwise comparison among aligned nucleotides and predicted amino acids as well as on substitution rates, and phylogenetic inference. The analyzed sequences were heterogeneous and the A. hypogaea accessions were primarily closest to those of Manihot esculenta, but this needs further clarification.

In this thesis, a solid-state 3D imager receiver architecture based on the direct time-of-flight (dTOF) technique is discussed, implemented and tested. The distinctive feature of this work is the combination of a unique laser diode (LD) transmitter operating in enhanced gain-switching mode and a highly integrated single-chip SPAD/TDC array receiver. The LD transmitter is capable of producing short/energetic (~100–200 ps FWHM/~1–5 nJ) laser pulses at pulsing frequencies of some hundreds of kHz with a rather simple driver structure and small size. Another distinction of this work is the receiver IC architecture strategy of separating the SPAD array from all the on-chip electronics in a dedicated chip area, with the aim of achieving a high fill factor. To evaluate the above-mentioned architecture, a receiver IC based on SPAD/TDC arrays was developed in a 0.35 μm HVCMOS technology. This IC, which included 9×9 SPADs and 9+1 TDCs, was paired with an LD transmitter and tested in a 3D imager prototype. The verification measurements of circuit/system-level performance confirmed the possibility of a compact low-cost solid-state 3D imager with spatial resolution of a few kilo pixels, cm-level depth precision and a frame rate of tens of fps based on the given architecture. Working from the results obtained with the first prototype, a second IC was designed and manufactured in the same HVCMOS technology, which was a combination of a 128×32 SPAD array and a 256+1 TDC array. Two ICs were used to form a receiver with 8-kilo pixel spatial resolution and combined with a LD transmitter into a compact USB-powered 3D imager (total size 5×7×4 cm3). The LD transmitter provided an average optical power of 1 mW at a wavelength of 810 nm, producing 150 ps pulses at a pulsing frequency of 250 kHz and targeting a field-of-view of ~42°×21° with flood-pulsed illumination by means of simple optics. The 3D imager demonstrated frame rates of 5–10 fps with cm-level precision in the case of Lambertian targets within a range of 5 m. Tiivistelmä Työssä on suunniteltu, toteutettu ja testattu vastaanotinarkkitehtuuri 3D etäisyyskuvantamiseen. Mittaus perustuu tietyssä toimintamuodossa olevan, tarkoitusta varten suunnitellun laserdiodin tuottamien pulssien kulkuaikojen mittaamiseen korkean integraatioasteen omaavalla, yksittäisiä fotoneja ilmaisemaan kykenevällä SPAD/TDC IC-piirillä. Laserdiodilähetin tuottaa lyhyitä ja energisiä (~100–200 ps FWHM/~1–5 nJ) laserpulsseja satojen kHz:n pulssitaajuudella pieneen tilaan toteutetun elektroniikan ohjaamana. Eräs työn tärkeä piirre on valittu vastaanotinarkkitehtuuri, jossa fotoni-ilmaisinmatriisi (SPAD-matriisi) on erotettu muusta vastaanotinelektroniikasta korkean ilmaisuhyötysuhteen aikaansaamiseksi. Arkkitehtuurievaluaatiota varten työn alussa kehitettiin 0,35 μm:n HVCMOS-teknologiassa toteutettu vastaanotin IC-piiri, joka sisältää 9×9 fotoni-ilmaisinta ja 9+1 aika-digitaali-muunninta samalla sirulla. 3D testimittaukset varmensivat arkkitehtuurin toimivuuden ja osoittivat, että siihen perustuen on mahdollista kehittää edullinen, ilman liikkuvia osia toimiva 3D kuvanninteknologia, jolla voidaan saavuttaa cm-luokan etäisyysmittaustarkkuus ja muutaman kilopikselin spatiaalinen resoluutio sekunnin murto-osien mittausnopeudella. Näihin tuloksiin perustuen työn seuraavassa vaiheessa suunniteltiin laajempi vastaanotin IC, jossa on 32×128 pikseliä sisältävä fotoni-ilmaisinmatriisi ja 256+1 aika-digitaali -muunninta samalla sirulla. Piiri toteutettiin 0,35 µm:n HVCMOS teknologiassa. Kahta tällaista vastanotinta käyttäen toteutettiin kompakti (koko 5×7×4 cm3 laserlähettimen kanssa), USB-väylästä virroitettu 8 kilopikselin 3D etäisyyskuvannin. Laserdiodilähettimen keskimääräinen optinen teho on n. 1 mW ja se toimii 810 nm:n aallonpituudella. Lähetin tuottaa 150 ps:n pulsseja 250 kHz:n pulssitaajuudella kuvantimen ~42°×21° mittausavaruuteen. Toteutettu 3D kuvannin tuottaa etäisyyskuvia n. 5 m:n etäisyydellä olevista kohteista cm-luokan tarkkuudella 5–10 kuvaa sekunnissa mittausnopeudella.

[ES] El objetivo final de éste TFM consiste en realizar un diseño de test de un front end integrado para grandes arrays de SiPM. Como una primera aproximación se implementará el front end de un sólo canal en una tecnología típica (0.35um) para evaluar el diseño y localizar los puntos críticos de la cadena de señal analógica. En paralelo se evaluarán las topologías de TDC (Convertidore de tiempo a digital) así como los convertidores analógico digitales multicanal para proponer una combinación TDC+ADC que sea capaz de generar los valores de marca de tiempos y carga digitales asociados a cada evento detectado. El TFM tendrá dos fases: 1) Revisión de las arquitecturas TDC y propuesta de una estructura multicanal. El TDC proporcionará una marca de tiempos digital para canal disparado con una resoluciónd e 15 ps y una ventana gruesa temporal de 1s. Las señales de entrada al TDC multicanal serán las salidas "Fast" de los preamplificadores de la etapa de entrada. Será necesaria la implementación de un comparador de alta velocidad para mejorar el comportamiento de los TDC 2) Revisión de arquitecturas ADC multicanal de baja complejidad y propuesta de una estructura ADC para conversión de carga. El QDC debe proporcionar una resolución efectiva de 9 bits para cada canal disparado. El tiempo de conversión no debe exceder de 1 us, tomando en cuenta las limitaciones de la tecnología de 0.35u, [EN] The final goal of these master thesis proposals aims at carrying out a test design of an integrated front end for large arrays of SiPM. As a first approach, a single front end channel will be implemented in a 0.35um technology node to check for the feasibility of this design and locate the key points of the analog signal chain. In a parallel thread, a survey on Time to Digital Converter (TDC) topologies as well as multichannel Analog to Digital Converters will be done in order to propose an optimal set of TDC + ADC elements which will translate front end channels outputs to timestamp and charge digital data. The Master Thesis will cover two phases: 1) Review of Time to Digital Converters architectures and proposal of a multichannel input structure. The TDC must provide a digital timestamp for each triggering channel with a 15 ps resolution and a coarse timing window of 1 s. The input signals to the multichannel TDC will be that of the Fast Branches of the preamplifiers (a fast comparator will be required to enhance TDC behavior). 2) Review of medium precision lightweight multichannel ADC converters and proposal of an ADC structure for Charge Branch conversion. The QDC must provide a 9 effective bits output for each triggering channel. The conversion time must not exceed 1 us taking into account frequency limitations in the 0.35 technology kit being used in this test design.

Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB., FRCT - Fundo Regional para a Ciência e Tecnologia(PDE/BDE/114562/2016)

Accurate and rapid measuring methods for displacement of nano-scale is necessary for manipulation. Self-sensing and time-digit-conversion(TDC) are two applicable measuring methods especially suitable for room-limited workspaces and vacuum-compliance required applications, thanks to their space-saving advantage and slight thermal impact on system. The self-sensing method gives measurements in high resolution at high sampling rate but its accuracy suffers from nonlinearity, while TDC has better linearity which causes less deviation to results but has a much lower sampling rate. A Kalman filter based fusion approach with dual estimation modes and self-adaptive parameters is designed to fuse the two measurements with different sampling rates at a higher frequency. Modifications to error covariance parameters are applied to traditional Kalman filter so that sensors’ generalized errors rather than their Gaussian noises are taken into consideration, and corresponding derivation is given. A series of experiments are conducted to evaluate the performance of the fused measurement.

In this paper, we propose a new calibration system of Time-to-Digital Converter (TDC) using delta sigma structure. This circuit is equipped with a new foreground calibration unit, and by detecting the manufacturing error information of the delay element with high accuracy, highly accurate outgoing correction is possible. We performed simulation by MATLAB / Simulink and measurement by programmable system-on-chip (PSoC).

Successive approximation (SAR) type Analog to Digital Conveter (ADC) is a Nyquist Rate ADC which has acquired tremendous pupularity recently due to its digital nature , minimal complexity and tiny foot print .These merits make them the most energy ecient topology for analog to digital conversion available today well suited for battery powered applications like touch screen controllers , wireless communication systems , Motion detectors etc. Enhancements in these domains is greatly linked to breakthroughs improving speed as well as performance of SAR type ADCs . In this Work we tried to understand SAR topology in depth therby opening up a new 'time' dimesion to harness more information during the SAR conversion process. A new architecture is proposed in which this auxilliary dimension is employed to signicantly improve eciency and throughput over existing SAR ADC implementations .

This dissertation contains three parts. In the first part, the analysis and circuits of a jittercleaning fractional-N frequency synthesizer is presented. In the second part, a low phase noise and low I/Q mismatch quadrature VCO is presented. In the third part, a low phase noise digital PLL is presented.For the first part, the design utilizes a dual-loop architecture, which is suitable for integration in an SoC environment. The primary loop is a digital PLL with a second-order noise shaping phase-error ADC. The secondary loop is a fractional-N PLL implementing the digitally controlled oscillator inside the primary loop, and it locks to an external clean reference clock to reduce the phase noise and to improve the frequency stability of the on-chip oscillator. For the second part, a tail-tank coupling technique that combines two complementary differential LC-VCOs to form a quadrature LC-VCO is presented. This technique reduces phase noise by providing additional energy storages for noise redistribution and by canceling out most of the noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum value.For the third part, a 2.8 to 3.2 GHz fractional-N digital PLL is presented. A divider with two-stage retiming improves linearity to reduce fractional spurs without increasing the in-band noise floor. An ADC is employed to boost TDC resolution by five times to achieve 2 ps effective resolution. A dither-less DCO with an inductively coupled fine-tune varactor bank improves tuning step-size to 20 kHz. With a 52 MHz reference clock and a loop-bandwidth of 950 kHz, this prototype achieves 230 fs rms jitter integrated from 1 kHz to 40 MHz offset while drawing 17 mW from a 1.8V supply. A FOM of -240.4 dB is achieved.