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Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds) in real-time for standard PAL (720 × 576) size color video.

The design of smart video surveillance systems is an active research field among the computer vision community because of their ability to perform automatic scene analysis by selecting and tracking the objects of interest. In this paper, we present the design and implementation of an FPGA-based standalone working prototype system for real-time tracking of an object of interest in live video streams for such systems. In addition to real-time tracking of the object of interest, the implemented system is also capable of providing purposive automatic camera movement (pan-tilt) in the direction determined by movement of the tracked object. The complete system, including camera interface, DDR2 external memory interface controller, designed object tracking VLSI architecture, camera movement controller and display interface, has been implemented on the Xilinx ML510 (Virtex-5 FX130T) FPGA Board. Our proposed, designed and implemented system robustly tracks the target object present in the scene in real time for standard PAL (720 × 576) resolution color video and automatically controls camera movement in the direction determined by the movement of the tracked object.

Improved video coding techniques introduced in the H.265/High Efficiency Video Coding (HEVC) standard allow video encoders to achieve better compression efficiencies. On the other hand, the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions. This paper presents a computationally scalable algorithm and its hardware architecture able to support intra encoding up to 2160p@30 frames/s resolution. The scalability allows a tradeoff between the throughput and the compression efficiency. In particular, the encoder is able to check a variable number of candidate modes. The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate–distortion analysis and enable the evaluation of a great number of candidate intra modes. The encoder preselects candidate modes by the processing of $8\times 8$ predictions computed from original samples. The preselection shares hardware resources used for the processing of predictions generated from reconstructed samples. To support intra $4\times 4$ modes for the 2160p@30 frames/s resolution, the encoder incorporates a separate reconstruction loop. The processing of blocks with different sizes is interleaved to compensate for the delay of reconstruction loops. Implementation results show that the encoder utilizes 1086k gates and 52-kB on-chip memories for TSMC 90 nm. The main reconstruction loop can operate at 400 MHz, whereas the remaining modules work at 200 MHz. For 2160p@30 frames/s videos, the average BD-rate is 5.46% compared with that of the HM software. [ABSTRACT FROM PUBLISHER]

In this paper, an efficient VLSI architecture of a hierarchical block matching algorithm has been proposed for motion estimation. At the lowest resolution level, two motion vector (MV) candidates are selected to get better performance. In the next search level, these two candidates provide the center points for local searches to get one MV candidate. Then, at next level and the finest level, one MV candidate is chosen from one local search area (LSA), defined by the MV candidate, obtained from lower resolution level. This architecture requires nine processing elements and data are processed in such a way that calculation to obtain frames of different resolution is overlapped with the MV calculation. Simulation results indicate that this architecture is more area-efficient and faster than many full-search, three-step-search and multiresolution architectures which makes it suitable for SD and HD video. To avoid the delay due to pipelining, the MVs of all the macro-blocks are calculated for one resolution level and stored in RAM to get LSA for next resolution level. This architecture with about 16 K gates is implemented for a search range of [−15, +15]. As this architecture requires only two-port memory, which is very common in most consumer electronics systems, it can be integrated easily in any existing system at the expense of a very small area. [ABSTRACT FROM AUTHOR]

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and lowcomplexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance. [ABSTRACT FROM AUTHOR]

Scaling is a key important arithmetic operation and is difficult to perform in Residue Number Systems (RNS). This paper proposes a comprehensive approach for designing efficient and accurate 2^n RNS scalers for important classes of moduli sets that have large dynamic ranges. These classes include the traditional 3-moduli set, but the exponent of the power of two modulo is augmented by a variable value x ( \lbrace 2^n-1, 2^n\underline+x, 2^n+1 \rbrace ), and any extended set with an additional modulo m_4 ( \lbrace 2^n-1, 2^n\underline+x, 2^n+1[,\underlinem_4]\rbrace ). The proposed approach embeds scaling into the formulation of the Chinese remainder theorem and the mixed radix system, and it exploits the properties of the target moduli sets to perform scaling explicitly in the RNS domain. This is accomplished by operating hierarchically on each channel without requiring reverse and forward conversions. Simple memoryless VLSI architectures are proposed based on the obtained formulations. The relative assessment indicates that not only are these architectures comprehensive and suitable for configurable systems, but they are also more efficient than the related state of the art in terms of both performance and energy. The experimental results obtained for a 90 nm CMOS ASIC technology show improvements in the area-delay product, normalized with respect to the dynamic range, of up to $57$ and $146$ percent with the proposed scalers for the augmented 3-moduli set (dynamic range of $4n-1$ bits) and an extended 4-moduli set (dynamic range of $6n$ bits), respectively. These improvements increase to $64.9$ and $263$ percent when the energy required per scaling is measured. The proposed scalers are not only flexible and cost-effective, but they are also suitable for designing and implementing energy-constrained devices, particularly mobile systems. [ABSTRACT FROM PUBLISHER]

Fractional motion estimation (FME) significantly enhances video compression efficiency, but its high computational complexity also limits the real-time processing capability. In this brief, we present a VLSI implementation of FME design in High Efficiency Video Coding for ultrahigh definition video applications. We first propose a bilinear quarter pixel approximation, together with a search pattern based on it to reduce the complexity of interpolation and fractional search process. Furthermore, a data reuse strategy is exploited to reduce the hardware cost of transform. In addition, using the considered pixel parallelism and dedicated access pattern for memory, we fully pipeline the computation and achieve high hardware utilization. This design has been implemented as a 65-nm CMOS chip and verified. The measured throughput reaches 995 Mpixels/s for $7680\,\times \,4320~30$ frames/s at 188 MHz, at least 4.7 times faster than prior arts. The corresponding power dissipation is 198.6 mW, with a power efficiency of 0.2 nJ/pixel. Due to the optimization, our work achieves more than 52% improvement on power efficiency, relative to previous works in H.264. [ABSTRACT FROM AUTHOR]

Motion estimation (ME) in the latest High Efficiency Video Coding standard adopts the quadtree coding structure and up to a $64\times 64$ prediction unit (PU) size to improve the coding gain. However, these techniques also have serious design problems regarding the complexity, data dependency, external memory bandwidth, and on-chip buffer size compared with previous standards, especially for real-time ultrahigh-definition video coding. To solve these problems, this paper proposes an efficient ME design with a joint algorithm and architecture optimization. To reduce complexity, we propose a predictive integer ME (IME) algorithm that selects the most probable search directions and steps through a statistical analysis to reduce the number of search points by 90.5%. We also employ a PU size-dependent fractional ME (FME) algorithm to reduce the interpolation filtering by 62.4% compared with the reference software. To resolve the corresponding dependency, we cascade the IME and FME computations via interlaced scheduling and propose an early motion vector prediction candidate approach. We use this scheduling with a 16\times 16$ processing unit to compute the partial matching cost of all PUs with the same 16\times 16$ current block in an interlaced order and share their common reference block to reduce the on-chip buffer size and off-chip memory bandwidth. The bandwidth is further reduced by a cache with double Z scan indexed addressing to simplify the cache controller. Implementation with a Taiwan Semiconductor Manufacturing Company 90-nm CMOS process supports the real-time encoding of at 60 frames/s operated at 270 MHz with 778.7k logic gates and 17.4 KB of on-chip memory. [ABSTRACT FROM PUBLISHER]

H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual‐standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 × 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 × 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 × 4320) frame in HEVC standard. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new hardware-efficient adaptive binary range coder (ABRC) and its very-large-scale integration (VLSI) architecture. To achieve this, we follow an approach that allows to reduce the bit capacity of the multiplication needed in the interval division part and shows how to avoid the need to use a loop in the renormalization part of ABRC. The probability estimation in the proposed ABRC is based on a lookup table free virtual sliding window. To obtain a higher compression performance, we propose a new adaptive window size selection algorithm. In comparison with an ABRC with a single window, the proposed system provides a faster probability adaptation at the initial encoding/decoding stage, and more accurate probability estimation for very low entropy binary sources. We show that the VLSI architecture of the proposed ABRC attains a throughput of 105.92 MSymbols/s on the FPGA platform, and consumes 18.15 mW for the dynamic part power. In comparison with the state-of-the-art MQ-coder (used in JPEG2000 standard) and the M-coder (used in H.264/Advanced Video Coding and H.265/High Efficiency Video Coding standards), the proposed ABRC architecture provides comparable throughput, reduced memory, and power consumption. Experimental results obtained for a wavelet video codec with JPEG2000-like bit-plane entropy coder show that the proposed ABRC allows to reduce the bit rate by 0.8%–8% in comparison with the MQ-coder and from 1.0%–24.2% in comparison with the M-coder. [ABSTRACT FROM PUBLISHER]

Motion estimation (ME) consumes large hardware cost and power (50 %-90 %) in most video encoders. Thus reducing the power consumption of ME is a major concern of low power video encoder design. A lot of fast ME approaches have been proposed but many of them focus on algorithm speed up rather than power consumption. Pixel truncation can effectively reduce the hardware cost and the power consumption. Classical pixel truncation is usually performed uniformly within the search window. However, it suffers great compression efficiency degradation when high power reduction ratio is required. This paper proposes a low power motion estimation scheme based on non-uniform pixel truncation. By observing the unequal distribution of motion vectors, we divide the search window into different sub-regions and employ different numbers of truncated bits (NTB) in these sub-regions. NTB pairs are appropriately examined to achieve a better tradeoff between the compression efficiency and the hardware cost. Then hardware architecture is designed to evaluate the hardware cost of the algorithm and a carefully designed threshold parameter is introduced to make the algorithm more hardware-friendly. Test results demonstrate that the proposed hardware-friendly algorithm achieves 21 % and 49 % power saving in the 2D and 1D ME architecture, respectively, both with negligible compression efficiency degradation. [ABSTRACT FROM AUTHOR]

This paper presents efficient VLSI architecture for fast Motion Estimation (ME) using Adaptive Rood Pattern Search (ARPS) technique. The proposed architecture uses a single processing element (PE) and simplified memory addressing to reduce the hardware complexity. The addressing logic, which is presently applied to 352 × 288 CIF frames, can be easily extended to frames of higher resolutions. The proposed architecture uses optimum area while satisfying speed requirements for real-time video processing. Implemented in Verilog HDL and mapped to Virtex 6 (XC6VLX75T-3) FPGA, the architecture uses only 165 slice registers and 273 slice LUTs. The architecture can process 240 frames per second while operating at a maximum frequency of 320 MHz. [ABSTRACT FROM AUTHOR]

Motion estimation is the most computationally intensive part of any video coding standard. The three-step search algorithm is a popular fast search technique to reduce complexity in motion estimation. In this paper, we propose a novel architecture for the three-step search technique that simplifies memory addressing and reduces hardware complexity. The proposed architecture minimizes the area while maintaining the speed requirements for real-time video processing. Implemented in Verilog HDL on Virtex-5 technology and synthesized using Xilinx ISE Design Suite 14.1, the critical path in the hardware is 6.536 ns and the equivalent area is calculated to be 2.3 K gate equivalent. [ABSTRACT FROM AUTHOR]

Search range (SR) is a key parameter on the search quality control for motion estimation (ME) of a real-time video encoder. Dynamic search range (DSR) is a commonly employed algorithm to reduce the computational complexity of ME in a video encoder. In this paper, we model an effective predicted motion vector (PMV) deviation metric to predict the relationship between SR and motion vector difference (MVD), according to the prediction differences of both temporal and spatial motions of neighboring blocks. In addition, a computation-constrained DSR (CDSR) control algorithm is proposed to manage the computational complexity while maximizing video coding quality in a real-time computational constrained scenario. The SR is dynamically determined by three factors: motion complexity, user-defined probability and computation budget. Compared to the conventional DSR algorithms, the proposed CDSR is an effective and quantifiable algorithm to allocate more computation budget to the blocks with high PMV deviations (such as motion object boundary), and less computation budget to the well-matched motion predicted blocks, while maintaining a constrained computation requirement. Experimental results show that the proposed CDSR control algorithm is an effective method to manage the computation consumption of the DSR algorithm while keeping similar rate–distortion (RD) performance. It can achieve about 0.1–0.3 dB average PSNR improvement when the computation consumption is restricted to a specific level as compared with its equivalent Fixed SR algorithm and can achieve about 50–90% computation savings when compared to the benchmarks. For ME with high performance Processing Element (PE) engine, the quality degradation caused by the proposed CDSR algorithm can be ignored. [ABSTRACT FROM AUTHOR]

Fast Fourier transformation (FFT) is widely used in modern wireless communication and digital signal processing. Because memory access is a major cause of power dissipated by the long-length FFT architecture, this paper explores the design space expanded by FFT size and radix number in detail and presents a novel low-memory-access length-adaptive architecture for computing any long-length 2 $$^n$$ -point FFT. The proposed hardware solution possesses the following three attractive features to reflect its novelty as compared to the existing designs. First, the authors identified that memory consumes major energy dissipation of a FFT processor and proposed to reduce memory access through decreasing the number of FFT butterfly stages. The second one is that we adopt the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware for computing variable-length FFT without sacrificing the hardware utilization as contrary to the feed-forward architecture. Finally, a 16-bank memory organization is proposed to achieve conflict-free FFT operations for various radixes. Such low-memory-access length-adaptive architecture can reduce almost 70 % memory access or 30 % power consumption for FFT computation. After being implemented through 1P6M TSMC 0.18- $$\upmu $$ m CMOS technology, this work costs a core area of only 4.49 mm $$^{2}$$ and meets the FFT real-time performance requirements of DVB-T2 systems when operated at 20 MHz frequency. The proposed design consumes only 1.44 nJ of energy per sample for computing FFTs. Through adopting the proposed low-memory-access algorithm, flexible length-adaptive architecture, and efficient 16-bank memory organization, 56 % power dissipation of the whole FFT chip can be saved. [ABSTRACT FROM AUTHOR]

The H.264/AVC is the Standard Video Format used by the SBTVD (Sistema Brasileiro de Televisão Digital), with presence in almost all the countries in South America, that allows transmissions in Full High Definition (Full HD) video quality. So this work presents a hardware architecture design of the Motion Estimation algorithm used in the Standard, as the higher computational processing is located in this part, so we take advantage of the high parallelism characteristics of the designs made in hardware to achieve faster processing and hence real-time broadcasts. The design was described using VHDL and synthesized to the Altera Cyclone II FPGA being able to process Full HD video (1920x1080 pixels) in real-time. The results establish a maximum operation frequency of 183.55 MHz, and at this speed it can process 35 frames per second. [ABSTRACT FROM AUTHOR]

VLSI architecture for face recognition system based on Local Gabor XOR Pattern (LGXP) feature extraction method is presented in this paper. LGXP is utilized to encode Gabor phase variations and to extract feature with the help of Gabor filter and Local XOR Pattern (LXP) operator. VLSI architecture for Gabor Filter and a Behavioral model for LXP operator for feature extraction are investigated. Also a behavioral model for Similarity matching is designed using Verilog language. The similarity matching for face recognition is executed by L1 distance measure. Therefore our approach explores the effectiveness of Gabor phase information on FPGA platform by addressing the drawbacks like computational complexity and hardware complexity by mapping the algorithms. The proposed approach is designed on virtex-5 device using Veriolg HDL in Xilinx ISE tool and the logic utilization results will be generated using synthesis tool while the power consumption report will be analyzed using Xpower analysis tool. Also the effectiveness of our design is evaluated with FAR, FRR and accuracy plot in Matlab simulation environment. Research outcome of our proposed face recognition system over UPC face database is 72.225% Accuracy for distance matching threshold of '5'. [ABSTRACT FROM AUTHOR]

A new resource efficient FPGA-based hardware architecture for real-time edge detection using Sobel operator for video surveillance applications has been proposed. The choice of Sobel operator is due to its property to counteract the noise sensitivity of the simple gradient operator. FPGA is chosen for this implementation due to its flexibility to provide the possibility to perform algorithmic changes in later stage of the system development and its capability to provide real-time performance, hard to achieve with general purpose processor or digital signal processor, while limiting the extensive design work, time and cost required for application specific integrated circuit. The proposed architecture uses single processing element for both horizontal and vertical gradient computation for Sobel operator and utilised approximately 38% less FPGA resources as compared to standard Sobel edge detection architecture while maintaining real-time frame rates for high definition videos (1920 × 1080 image sizes). The complete system is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board. [ABSTRACT FROM AUTHOR]

This paper presents the compute voltage regulator module (C-VRM), an architecture that embeds the information processing subsystem into the energy delivery subsystem for ultra-low power (ULP) platforms. The C-VRM employs multiple voltage domain stacking and core swapping to achieve high total system energy efficiency in near/sub-threshold region. Energy models for the C-VRM are derived, and employed in system simulations to compare the energy efficiency benefits of the C-VRM over a switched capacitor VRM (SC-VRM). A prototype IC incorporating a C-VRM and a SC-VRM supplying energy to an 8-tap fully folded FIR filter core is implemented in a 1.2 V, 130 nm CMOS process. Measured results indicate that the C-VRM has up to 44.8% savings in system-level energy per operation (Eop) compared to the SC-VRM system, and an efficiency \eta ranging from 79% to 83% over an output voltage range of 0.52 V to 0.6 V. Measured values of the Eop and \eta match those predicted by system simulations thereby validating the energy models. [ABSTRACT FROM AUTHOR]

Motion vector (MV) prediction and residue coding technique is adopted to fully utilize the motion field redundancy in the prevailing video standards, and MV prediction is desired in both video encoder and decoder. The computation burden for MV prediction is not very high. However, there is high irregularity in raw MV prediction algorithm with two-stage and four-level hierarchical tree control flows. It makes efficient VLSI architecture implementation challenging. The high irregularity is mainly derived from the abundant inter prediction modes including variable block size partition and temporal prediction direction, as well as the irregular control flow of the MV prediction algorithm. This paper proposes a highly regular architecture to implement MV prediction for multi-standard video codec. Complex control logic is simplified by regularly table look-up of the control parameters predefined and stored in on-chip tables. The parameters of the current macroblock (MB) and its neighboring blocks are initialized and refreshed in a regular manner. Moreover, pipelining and parallelism are employed in the proposed architecture to improve throughput efficiency and tradeoff between hardware cost and efficiency. Simulation results verify the effectiveness of the proposed design. [ABSTRACT FROM AUTHOR]

In this paper, we characterize the performance of datapath architectures of the Advanced Encryption Standard (AES). These architectures are parameterized by a datapath width of 8, 16, 32, 64, or 128 bits and, for the 128-bit width, an unrolling factor of 1, 2, 5 or 10. Composite field S-boxes are adopted for all the architectures and shift registers based ShiftRows and MixColumns components are used for architectures with datapath widths of less than 128 bits. Their performance in terms of area, peak power and average energy is benchmarked using a 90-nm standard cell CMOS technology under a variety of throughput requirements. Through this characterization, the performance trade-offs affected by the architecture parameters are extensively explored. The parameters leading to the best performance are identified. It is found that the 8-bit width datapath, which is conventionally adopted for resource efficient purposes, has the worst energy efficiency and does not result in the minimal peak power among the architectures. As well, the 16, 32 and 64-bit width AES datapath architectures are newly considered or represent improvements over previous work. [ABSTRACT FROM AUTHOR]

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human–computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience. [ABSTRACT FROM PUBLISHER]