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This paper shows that a typical algorithm for finding the optimal route based on each vehicle focuses on the total distance of the shortest path, and that the algorithm can be modified to achieve the desired result if other factors other than the shortest distance should be targeted. We then explain that when applying the algorithm to multiple vehicles, the complexity of the system makes it difficult to describe it on an individual vehicle basis, and the greedy characteristics of the algorithm can be costly in terms of time. To minimize this damage, we also consider the impact of other vehicles and modify the algorithm to avoid congested areas. To test this, we use the microtraffic simulations SUMO and TraCI to measure the Mean Time and Total Distance for multiple vehicles to all reach their destination in a scenario on a specific Net, and show that we can reduce the Mean Time by up to 22.8% for multiple traffic scenarios. [ABSTRACT FROM AUTHOR]

If various behaviors based on driver habits are directly reflected in parking situations, it can cause damage to other drivers, such as blocking the path of other vehicles or parking without enough space for the next vehicle to park, which can lead to accidents. For this reason, this research proposes an automatic parking assistance control system that applies an adaptive algorithm that changes the control sensitivity of the vehicle controlled by the driver in real-time based on information about the parking environment that changes in real-time. Based on the information obtained while controlling a vehicle in a virtual parking lot, it was confirmed that the control sensitivity was appropriately changed depending on the parking situation based on a settling time of approximately 1 second. As a result, it is expected to assist drivers in efficient and standard parking in various parking situations. [ABSTRACT FROM AUTHOR]

Cache memory is controlled by hardware, resulting in significant hardware overhead and power consumption. This situation necessitated the use of scratchpad memory as an alternative. Specifically, for utilizing scratchpad memory in multi-core systems, a Local Memory Storage (LMStr) structure has been proposed. However, the LMStr structure must address fragmentation issues caused by the use of variable-sized data blocks. In this paper, we propose a new structure called 'Paging LMStr' that applies paging to solve this problem. We implement a system capable of simulating it in gem5 and evaluate its performance through a comprehensive testbench. The results demonstrate that the proposed structure improves the hit rate by 3.6% and reduces system ticks by approximately 10.68%, leading to a significant overall performance improvement compared to the existing structure. This indicates that Paging LMStr can effectively enhance memory management efficiency in multi-core systems, providing a viable solution to the challenges posed by traditional cache memory systems. [ABSTRACT FROM AUTHOR]

In recent years, there has been a trend towards integrating functions using a small number of microcontrollers instead of employing multiple microcontrollers across various environments. This shift underscores the need for a hypervisor capable of efficiently utilizing resources while imposing minimal overhead. Addressing this demand, this paper introduces a hypervisor employing dynamic round-robin scheduling, which flexibly adjusts time quantum allocation based on the urgency of each OS. Furthermore, a monitor mode is devised to oversee resource allocation among multiple OSs. To enhance responsiveness while managing these OSs, ultra-light context-switching is implemented within the monitor mode. The proposed system demonstrates a notable reduction in execution time, approximately 19% compared to traditional round-robin scheduling. Additionally, in terms of energy efficiency, the proposed system yields a 34% reduction in energy consumption compared to existing methods. Notably, the ultra-light context-switching mechanism consumes only about 5% of the processing cycle when compared to FreeRTOS. [ABSTRACT FROM AUTHOR]

This study aims to enhance the accuracy and reliability of low-cost sensors for measuring fine dust concentrations. Sensors used to measure the concentration of fine dust particles are expensive and the transfer function that adjusts the number of dust particles to dust concentration is complex and not well-known. Previous research has utilized singular-value-decomposition to obtain effective transfer matrices, but noise information measured by low-cost sensors is also transmitted. In this study, by using long short-term memory as filter for noise suppression, we effectively mimicking the data flow measured by expensive reference device. Experimental results show that existing filters suppress noise by approximately 20%, while the proposed long short-term memory filter achieves around 50% noise suppression. Furthermore, in discontinuous operations, five times repetitive learning of initial data reduced the relative error in initial data to within 10%, significantly reducing the initial delay. [ABSTRACT FROM AUTHOR]

This paper proposed a code reconfiguration platform for embedded devices that abstracts link layer to enable intelligent services. Due to their limited resources, embedded devices are inefficient to execute programs that require fast computation and are large in scale. The proposed platform uses remote code execution to cloudify server resources and provide them to the edge device. In an experimental environment, we implemented a square matrix multiplication program with 1000 rows and found that the code memory size of the embedded device was reduced by 8.88% and the program execution time was reduced by 96.7%. By using an abstracted link layer, our platform allows embedded devices to provide intelligent services by changing the number of accelerator processes without changing the edge code. [ABSTRACT FROM AUTHOR]

Issues of system protection and safety from system malfunction by software errors are increasing because the expansion of industrial fields requiring high precision and high specifications of embedded systems and the increase in the complexity of embedded software. This paper proposes efficient ways to detect and defend against malfunctions in the run-time system by automatically generating codes to compare with the malfunction patterns of a target system using normal current/voltage patterns. The proposed monitoring system is controlled using (1) a recovery algorithm that initializes the malfunctioning system and (2) a shutdown algorithm that stops the system for continuous malfunctions. The normal system, which consumes up to 95 mA, (1) consumes more than 114 mA by applying an error detection rate of 20 % or (2) when the voltage drops below 4.3 V, is detected as malfunctions and the algorithms are verified. [ABSTRACT FROM AUTHOR]

The verification complexity is becoming more complex, for the hardware-software tightly-coupled embedded processors in intelligent smart home appliances and automotives. Software-embedded processors require more verification overhead in time-dimension simulation for the long-term state transitions. Designers may not have enough time to perform all tests due to the repeated simulation. This paper presents an existing simulation method of implemented with Verilog digital design and propose a new method to reduce simulation run-time. To shorten simulation time, the compilation and common simulation run-time that are repeatedly performed were saved as snapshot file. The development tun-around time was reduced by performing the simulation using Tcl-based verification code for dynamically reloading from the stored simulation snapshot. The DSP block embedding in 8051 MCU is used as a demonstration. Despite the additional time of storing simulation snapshot and Tcl based verification code, simulation time was reduced by 53% compared to the traditional method. [ABSTRACT FROM AUTHOR]

The digital twin makes optimistic results by simulating the interactions between modeled data from the physical object in reality and getting the parameter to the reality, with minimizing physical cost. However, it is a challenge to ideally implement the process of modeling physical objects to data. Also, the simulation of interactions between modeled objects becomes more complicated, requiring a lot of arithmetic operations which makes it difficult to understand results and parameters. In this paper, we suggest a model, which combines the digital twin and virtual simulation. The combination model visualizes the simulation and makes the user involved in the process of simulation. Through the user’s process intervention and visualization, our model presents feedback on modeling, which presents highly understandable results and shows accurate parameters results. Also, we verify the 57% reduction in simulation time with iterations reduction of simulation with 3D-Unity in proposed environment. [ABSTRACT FROM AUTHOR]

As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms. [ABSTRACT FROM AUTHOR]

As the interest in the 4th industrial revolution and metaverse increases, metaverse with multi edge structure is proposed and noted. Metaverse is a structure that can create digital doctor-like system through a large amount of image processing and data transmission in a multi edge system. Since metaverse application requires calculating performance, which can reconstruct 3-D space, edge hardware’s insufficient calculating performance has been a problem. To provide streamable AI software in runtime, image processing, and data transmission, which is edge’s loads, needs to be lightweight. Also lightweight at the edge leads to power consumption reduction of the entire metaverse application system. In this paper, we propose collaborative edge-cloud image processing with remote image processing method and Region of Interest (ROI) to overcome edge’s power performance and build streamable and runtime executable AI software. The proposed structure was implemented using a PC and an embedded board, and the reduction of time, power, and network communications were verified. [ABSTRACT FROM AUTHOR]

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool. [ABSTRACT FROM AUTHOR]

The accuracy of peripheral object recognition algorithms using 3D data sensors such as LiDAR in autonomous vehicles has been increasing through many studies, but this requires high performance hardware and complex structures. This object recognition algorithm acts as a large load on the main processor of an autonomous vehicle that requires performing and managing many processors while driving. To reduce this load and simultaneously exploit the advantages of 3D sensor data, we propose 2D data-based recognition using the ROI generated by extracting physical properties from 3D sensor data. In the environment where the brightness value was reduced by 50% in the basic image, it showed 5.3% higher accuracy and 28.57% lower performance time than the existing 2D-based model. Instead of having a 2.46 percent lower accuracy than the 3D-based model in the base image, it has a 6.25 percent reduction in performance time. [ABSTRACT FROM AUTHOR]

Power management is still an important issue in embedded environments as hardware advances like high-performance processors. Power management methods such as DVFS control CPU frequencies in an adaptive manner for efficient power management in polling-based I/O programs such as network communication. This paper presents the problems of the existing power management method and proposes a new power management method. Through this, it is possible to reduce electric consumption by increasing the polling cycle in situations where the frequency of data reception is low, and on the contrary, in situations where data reception is frequent, it can operate at the maximum frequency without performance degradation. After implementing this as a code layer on the embedded board and observing it through Atmel's Power Debugger, the proposed method showed a performance improvement of up to 30% in energy consumption compared to the existing power management method. [ABSTRACT FROM AUTHOR]

AI-based image processing technologies in various fields have been widely studied. However, the lighter the board, the more difficult it is to reduce the weight of image processing algorithm due to a lot of computation. In this paper, we propose a method using deep learning for object recognition algorithm in lightweight embedded boards. We can determine the area using a deep neural network architecture algorithm that processes semantic segmentation with a relatively small amount of computation. After masking the area, by using more accurate deep learning algorithm we could operate object detection with improved accuracy for efficient neural network (ENet) and You Only Look Once (YOLO) toward executing object recognition in real time for lightweighted embedded boards. This research is expected to be used for autonomous driving applications, which have to be much lighter and cheaper than the existing approaches used for object recognition. [ABSTRACT FROM AUTHOR]

Electrocardiogram (ECG) signal's shape and characteristic varies through each individual, so it is difficult to classify with one neural network. It is difficult to classify the given data directly, but if corresponding normal beat is given, it is relatively easy and accurate to classify the beat by comparing two beats. In this study, we classify the ECG signal by generating the reference normal beat through the template cluster, and combining with the input ECG signal. It is possible to detect abnormal beats of various individual's records with one neural network by learning and classifying with the imaged ECG beats which are combined with corresponding reference normal beat. Especially, various neural networks, such as GoogLeNet, ResNet, and DarkNet, showed excellent performance when using the comparative learning. Also, we can confirmed that GoogLeNet has 99.72% sensitivity, which is the highest performance of the three neural networks. [ABSTRACT FROM AUTHOR]

Portable systems with built-in active noise control is required low power operation. Excessive anti noise search operation can lead to rapid battery consumption. A method that can adaptively cancel noise according to the operating conditions of the system is required and the methods of reducing power are becoming very important key feature in today's portable systems. In this paper, we propose the method of active noise control(ANC) using binary search algorithm in noisy systems. The implemented architecture detects a frequency component considered as noise from the input signal and by using the binary search algorithm, the system find out an appropriate amplitude value for anti-noise in a much faster time than the general linear search algorithm. Through the experimental results, it was confirmed that the proposed algorithm performs a successful functional operation. [ABSTRACT FROM AUTHOR]

As embedded system are used widely and variously, multi-edge system, which multiple edges gather and perform complex operations together, is actively operating. In a multi-edge system, it often occurs that an abnormal operation at one edge is transferred to another edge or the entire system goes down. It is necessary to determine and control edge anomalies in order to prevent system down, but this can be a heavy burden on the resource-limited edge. As a solution to this, we use power consumption data to check the state of the edge device and transmit it based on a QRcode to check and control errors at the server. The architecture proposed in this paper is implemented using 'chip-whisperer' to measure the power consumption of the edge and 'Raspberry Pi 3' to implement the server. As a result, the proposed architecture server showed successful data transmission and error determination without additional load appearing at the edge. [ABSTRACT FROM AUTHOR]

In the case of a scanning type multi-channel LiDAR sensor, the distance error called a walk error may occur due to a difference in received signal power. This work error causes different distance values to be output for the same object when scanning the surrounding environment based on multiple LiDAR sensors. For minimizing walk error in overlapping regions when scanning all directions using multiple sensors, to calibrate distance for each channels using convolution on external system. Four sensors were placed in the center of 6×6 m environment and scanned around. As a result of applying the proposed filtering method, the distance error could be improved by about 68% from average of 0.5125 m to 0.16 m, and the standard deviation could be improved by about 48% from average of 0.0591 to 0.030675. [ABSTRACT FROM AUTHOR]

The electrocardiogram (ECG) signal is a good indicator for early diagnosis of heart abnormalities. The ECG signal has a different reference normal signal for each person. And it requires lots of data to diagnosis. In this paper, we propose an adaptive OpenCL-based FPGA-GPU hybrid-layer platform to efficiently accelerate ECG signal diagnosis. As a result of diagnosing 19870 number of ECG signals of MIT-BIH arrhythmia database on the platform, the FPGA accelerator takes 1.15s, that the execution time was reduced by 89.94% and the power consumption was reduced by 84.0% compared to the software execution. The GPU accelerator takes 1.87s, that the execution time was reduced by 83.56% and the power consumption was reduced by 62.3% compared to the software execution. Although the proposed FPGA-GPU hybrid platform has a slower diagnostic speed than the FPGA accelerator, it can operate a flexible algorithm according to the situation by using the GPU. [ABSTRACT FROM AUTHOR]

The LiDAR sensor is attracting attention as a key sensor for autonomous driving vehicle. LiDAR sensor provides measured three-dimensional lengths within range using LASER. However, as much data is provided to the external system, it is difficult to process such data in an external system or processor of the vehicle. To resolve these issues, we develop integrated processing system for LiDAR sensor. The system is configured that client receives data from LiDAR sensor and processes data, server gathers data from clients and transmits integrated data in real-time. The test was carried out to ensure real-time processing of the system by changing the data acquisition, processing method and process driving method of process. As a result of the experiment, when receiving data from four LiDAR sensors, client and server process was operated using background or multi-core processing, the system response time of each client was about 13.2 ms and the server was about 12.6 ms. [ABSTRACT FROM AUTHOR]

In addition to the revival of the Internet of Things, embedded systems, which are at the core of the Internet of Things, require intelligent control as things change. Embedded systems, however, are heavily constrained by resources such as hardware, memory, time and power. When changes are needed to firmware in an embedded system, flash Memory must be initialized and the entire firmware must be uploaded again. Therefore, it is time- and energy-efficient in that areas that do not need to be modified must also be initialized and rewritten. In this paper, we propose how to upload firmware in installments to each sector of flash memory so that only firmware can be replace the firmware in the parts that need to be modified when the firmware needs to be modified. In this paper, the proposed method was evaluated using real target board, and as a result, the time was reduced by about half. [ABSTRACT FROM AUTHOR]

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer’s empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%. [ABSTRACT FROM AUTHOR]

Sensor nodes that directly collect data from the surrounding environment have many constraints, such as power supply and memory size, thus efficient use of resources is required. In this paper, in a sensor node that receives location data of a vehicle on a lane, the data reception period is changed by the target’s speed estimated by the Kalman filter and distance weight. For a slower speed of the vehicle, the longer data reception interval of the sensor node can reduce the processing time performed in the entire sensor network. The proposed method was verified through a traffic simulator implemented as MATLAB, and the results achieved that the processing time was reduced in the entire sensor network using the proposed method compared to the baseline method that receives all data from the vehicle. [ABSTRACT FROM AUTHOR]

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server. [ABSTRACT FROM AUTHOR]

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately. [ABSTRACT FROM AUTHOR]

Recently, as the size of data used in an embedded system increases, the need for an ECC decoding operation to robustly receive a massive data is emphasized. In this paper, we propose a method to accelerate the execution of computations that derive syndrome vectors when ECC decoding is performed using Hamming code in an embedded system with a built-in GPU. The proposed acceleration method uses the matrix-vector multiplication of the decoding operation using the CSR format, one of the data structures representing sparse matrix, and is performed in parallel in the CUDA kernel of the GPU. We evaluated the proposed method using a target embedded board with a GPU, and the result shows that the execution time is reduced when ECC decoding operation accelerated based on the GPU than used only CPU. [ABSTRACT FROM AUTHOR]