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Summary: In this paper, an ultra‐low‐power and area‐efficient demodulator circuit for wireless downlink SCM/CWM modulation schemes is proposed. The proposed demodulator offers high performances and allows simultaneous power and downlink data transmission over a single 13.56‐MHz inductive link. The proposed method requires only two carrier cycles per data bit period, and also, a power index of 75% is obtained. Although the proposed demodulator can be applicable to other wireless systems, here, it is intended for implantable medical devices. To prove the performance of the proposed demodulator circuit, it has been designed and post‐layout simulations are provided using a standard 65‐nm CMOS technology and occupies 27 × 32 μm2 of active area. Post‐layout simulation results indicate that with a 1‐V power supply, the proposed circuit achieves an ultra‐low‐power consumption of 8.51 μW at a data rate of 6.78 Mb/s corresponding to an energy efficiency of 1.25 pJ/bit. [ABSTRACT FROM AUTHOR]

Considering the trend of scaling down conventional technologies toward next-generation devices and the importance of new practical and efficient procedures in increasing the efficiency of digital computing circuits, this paper presents three full adder circuits. Suggested circuits, named Design-1 to Design-3, are proposed based on FinFET technology with channel length of 11 nm. In order to optimize energy consumption and area occupation, they have been implemented based on approximate computing with 4, 10, and 12 transistors, respectively. The main characteristics of the presented circuits lie in their utilization of the gate diffusion input technique, which has resulted in the generation of only three errors in their output. Diverse objectives for error generation have been incorporated into these circuits, positioning them as highly accurate competitors when compared to the most state-of-the-art designs. Also, due to the use of low number of transistors, which has led to low internal nodes, these circuits are in a favorable position in terms of power consumption and speed. To evaluate these circuits, extensive simulations are conducted considering various implementations, including single-bit configurations and integration within 4-bit ripple carry adders with 2 and 4 approximate bits. Based on the figure of merits used consist of diverse design parameters, Design-1 with the least number of transistors has a difference of about 85% improvement compared to the nearest competitor, while design-2 and design-3 circuits are also placed in desirable rankings. [ABSTRACT FROM AUTHOR]

The article presents two multipliers equipped with error compensation techniques, utilizing approximate 4:2 compressors to minimize energy consumption. Compared to previous approximate multipliers with error compensation circuit, the proposed designs named, "M00" and "M01", strike a good balance between accuracy and energy consumption. Although the reduction in the number of transistors has significantly decreased the energy consumption of M00, the accuracy of this design is still more than adequate for real-world applications such as image processing and neural networks. On the other hand, M01 attains high precision while consuming less energy than other multipliers. This article compares the proposed designs with existing multipliers using HSPICE tool in 7 nm FinFET technology. Moreover, the accuracy and quality of the proposed multipliers are evaluated using MATLAB. The results reveal that both proposed designs are very efficient in image processing. According to the results, M00 has the lowest energy consumption among the considered designs. M00 is about 7% better than its counterpart in terms of the power-delay-product parameter (5% Pdynamic and 48% Pstatic). M01 presents favorable results in the sharpening, smoothing, and Discrete Cosine Transform processes. [ABSTRACT FROM AUTHOR]

Multipliers are one of the most commonly used parts in a system, responsible for performing computations, while significantly contributing to power consumption. In this article, by removing the least significant bits, a new architecture is presented to implement 3 multipliers (Mul-1, Mul-2 and Mul-3), in order to reduce complexity and power consumption. Compared to the previous works, Mul-1 has the most accuracy in addition to its low energy consumption, therefore, it has been able to deliver a good trade-off between accuracy and energy consumption. All proposed designs and existing multipliers have been simulated and compared in 7 nm FinFET technology using Hspice tool. Moreover, the accuracy and quality of the proposed approximate multipliers are also evaluated using MATLAB. The results show that Mul-1 and Mul-3 are very efficient in image processing applications. According to the results, Mul-1 outperforms its counterpart by 10%, 50% and 50% in PDP, NMED and MRED, respectively. Furthermore, Mul-3 has satisfactory MSSIM in DSP applications and is better than its counterpart by 23% and 16% in PDP and MRED. Meanwhile, Mul-2 improves PDP by nearly 53% compared to Mul-1 and has the lowest power consumption. [Display omitted] • To reduce power consumption, some least significant bits are set to zero. • To ensure accuracy in multipliers, compressors have been employed as exact. • The error compensation circuit is presented to enhance precision in the second stage. • The use of multipliers in real applications that have high computational volume. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a low‐power transconductor‐capacitor (Gm‐C) filter with programmable cutoff frequency is designed for electroencephalogram (EEG), electrocardiogram (ECG), and surface electromyography (sEMG) biosignals. The second‐order Butterworth low pass filter (LPF) is designed as an interface between an instrumentation amplifier (IA) and an analog‐to‐digital converter (ADC). The proposed Gm‐C filter suppresses out‐of‐band components and also plays an anti‐aliasing role. With the variable transconductance based on flipped voltage follower (FVF), the cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz are obtained for EEG, ECG, and sEMG, respectively. This structure is highly accurate by using a robust and low‐power common mode feedback (CMFB). With 0.8 V supply voltage, the total power consumption of the filter is only 56 nW, 100 nW, and 221 nW for cutoff frequencies of 100 Hz, 560 Hz, and 1.5 kHz, respectively. The proposed Gm‐C filter is simulated in TSMC 65 nm CMOS technology and occupies an area of 0.12 mm2. The figure of merit (FOM) of the proposed filter is equal to 1.9 pW/pole. [ABSTRACT FROM AUTHOR]

In this study, a three-level static RAM cell with a single BL based on 16 nm BWG CNFET technology is proposed for use in high-performance IoT platforms. The proposed memory structure in a bit-interleaved architecture compatible design consists of a standard triple buffer gate (STB) based on the BWG CN-TGDI method and a pair of transmission gates as an access network. In the STB cell structure, the threshold voltage calibration by the flat band voltage parameter of the CNTs has been used to improve the static noise margin at logic level '1'. In addition, pseudo-resistor and stacked transistor structures have been used to control the single static current path during logic level '1' generation and cell leakage current, respectively. The simulation results based on the Monte Carlo method show that the hardware performance parameters PDP and EDP for the proposed design have been improved by 38.8% and 31%, respectively, compared to the counterpart structure. Moreover, the proposed architecture has shown a more reasonable result in terms of noise immunity than the best-performing design by 1.93 times. Finally, to investigate a real-world application, the triple memory structure has been used to store the colored QR code image with the data content of three values using the proposed hardware algorithm. The obtained results for the quality evaluation metrics, PSNR and MSSIM, emphasize the suitability of the proposed memory architecture for the development of next-generation SoCs. [ABSTRACT FROM AUTHOR]

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers. [ABSTRACT FROM AUTHOR]

In this paper a full wave rectifier is presented for RFID passive tags working at 960 MHz frequency. For designing the rectifier multi-stage structure, which has high sensitivity and efficiency, is used for the low amplitude input voltage. In order to eliminate the effect of pass transistors threshold voltage, bootstrap circuit which has cross coupled structure is utilized. For optimizing power conversion efficiency (PCE) and gaining high output voltage from the low input voltage the size of the elements and number of stages are modeled and optimized with neural network and TLBO algorithm, respectively. Due to the achieved results from the TLBO algorithm 6 stages are considered for the rectifier designing. For the low input voltage 0.6 V, the power conversion efficiency and the output DC voltage are achieved 50.8% and 1.52 V, respectively. The simulation of the proposed rectifier is done with Cadence software in 0.18μm CMOS technology and its layout equals to 0.00525mm2. [ABSTRACT FROM AUTHOR]

In this work, CNTFET-based GDI (CNT-GDI) and QCA-based GDI (QCA-GDI) methods (CNT/QCA-GDI) for designing unique ultra-efficient analogue and logical blocks in voltage-mode fuzzy and quantum systems are presented. Extensive Monte-Carlo simulations by using Synopsys H-SPICE simulator at 16 nm technology demonstrate that the analogue blocks improve considerably in term of performance, absolute error and energy consumption in the presence of compact variations in compared to their counterparts. Also, the logical blocks have advantages including fast response, high polarity and lower power-consumption achieved by the QCADesigner and QCAPro tools at 18 nm in contrast to the similar designs. As applications, the half wave rectifier (HWR) and full-wave rectifier (FWR) by employing the proposed methods in two technologies are implemented. The results show improvement for the proposed circuits with correct function and very high robustness under major variations in contrast to state-of-the art rectifier architectures at similar conditions. Consequently, the proposed methods are appropriate for designing integrated circuits (ICs) with higher capacity and energy-efficient for the emerging nano-technologies. [ABSTRACT FROM AUTHOR]

In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte–Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates. [ABSTRACT FROM AUTHOR]

In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product ( PDP ) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency ( f max . ) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance. [ABSTRACT FROM AUTHOR]

A compact and low-voltage CMOS exponential function generator circuit based on a new pseudo-approximation method is designed in 180-nm CMOS standard technology. The proposed approximation method is based on the TLBO evolutionary algorithm and shows a close characteristic to the ideal exponential function behavior over wide input range. Simulation results using HSPICE validate the theoretical analysis and verify the efficiency of proposed circuit which shows more than 66 dB output dynamic voltage range while the error is less than ±0.5dB. The total power consumption is below 0.17 mW with a ±0.75V power supply. [ABSTRACT FROM AUTHOR]

The memory includes flip flap cells which can store binary information. Therefore by designing the binary storing cell, which has the low chip area and power consumption, the high capacity memories with high performance can be presented. The gate diffusion input (GDI) method employed in designing low power logic gates can decrease the chip area and parasitic and interconnection capacitors. In this paper, the modified-GDI (m-GDI) method is used based on a basic GDI method in order to design master-slave D-Flip Flap (M/S-DFF) circuit. By employing the presented M/S-DFF circuit and the Boolean functions of m-GDI method, Random Access Memory (RAM) cell is designed. For optimizing the performance of the proposed memory cell and gaining the minimum power and propagation delay, the transistors size is adjusted with non-dominated sorting genetic algorithm-II (NSGA-II) in MATLAB software. Finally, the 4-words×4-bits RAM (4×4 RAM) cell is designed and evaluated by employing optimized RAM cell with algorithm. Due to the achieved results, the power consumption of the 4×4 RAM cell is 72.3%, while its propagation delay and Power-Delay Product (PDP) criterion are decreased 75.9% and 93%, respectively, in compare with similar cells which aren't optimized. The circuit simulation is done with Synopsys H-SPICE simulator in 32 nm CNTFET technology. For ensuring the accurate function of this algorithm, it is experimented on memory cell and decoder. By comparing NSGA-II algorithm with Multiple Objective Particle Swarm Optimization (MOPSO) algorithm, it can be observed that this method has good ability in multi-objective optimization. [ABSTRACT FROM AUTHOR]

The conventional complementary metal-oxide semiconductor (CMOS) design techniques confront to the limitation of designing the integrated circuits (ICs), especially memories, with multiple-valued logic (MVL) in nanotechnology. Gate diffusion input (GDI) technique, provides the possibility to design low power logic gates with small chip area and interconnection capacitors while the number of transistors is diminished. In this paper first ternary GDI (t-GDI) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is designed. Then, by using the standard ternary inverter (STI) gate implemented based on the proposed t-GDI cell with better noise margins and also small standard deviation of results, first novel design of a ternary SRAM (T-SRAM) cell is presented for nano process, which has smaller standby power dissipation and standard deviation for delay of writing and reading cycles, better read static noise margin (RSNM) and lower signal control complexity. The design of specific structure of 4-words×4-bits, ternary SRAM (4×4 T-SRAM) shows that the number of connections, chip area is decreased and power-delay product (PDP) criterion is improved for writing and reading cycles with significant small standard deviation in compare with the other similar T-SRAMs designed. The effects of different process variations such as density, number of CNTs and temperature variations are extensively evaluated by Monte-Carlo simulation, with respect to performance metrics such as delay, power dissipation and PDP of writing and reading cycles, also RSNM parameter for SRAM cells. The comparison exhibits that in all cases the proposed T-SRAM cell showing a substantial small standard deviation and considerable lower variability percentage than state-of-the art SRAM cells. So, the proposed T-SRAM cell design has the lowest sensitivity variations, thus it is an attractive choice for nano technology application in the presence of impact process and temperature variations. The simulation is done with Synopsys H-SPICE simulator in 32 nm technology under the condition of variations. [ABSTRACT FROM AUTHOR]

In this paper a DC-DC converter with high voltage conversion ratio and low chip area, which is useful for RFID tag chip, is presented. DC-DC converter is modeled with neural network while TLBO algorithm is used to optimize it. In each stage of the converter the charge transfer switch is used for increasing the voltage gain. Each charge transfer switch is dynamically controlled with the inverter and the charge transfer switch is completely becomes on and off. By using the achieved results of the TLBO algorithm, the output voltage and voltage conversion ratio of DC-DC converter are 7.741V and 86%, respectively, while the input voltage is considered 1.8V. The layout of the DC-DC converter chip area drawn in Cadence software is 60 µm*60µm. The neural network and TLBO algorithm are programed with Matlab software and the Cadence software is used for extracting the circuit primary samples and simulating the final design of DC-DC converter in 0.18 µm CMOS technology. [ABSTRACT FROM AUTHOR]

SRAM designing with greater storage capacity and lower power dissipation with desired stability by employing conventional CMOS technology seems to be impossible due to enhancement of short channel effect and leakage current due to increasing the number of the transistors. Up to now a lot of methods have been proposed in order to improve the performance of the logical circuits based on the CMOS technology, among of them the Gate-Diffusion Input (GDI) technique is an efficient method. In this paper the modified GDI cell (m-GDI) based on the basic GDI cell is proposed and then SRAM cell memory with 8 transistors (8T-SRAM) which uses the proposed GDI cell is presented. Due to the achieved results the stability-power dissipation ratio (SPR), the evaluation parameter in SRAM memories, is improved about 7 for 8T-SRAM which is implemented with a stack forcing method in similar carbon nanotube field-effect transistor (CNTFET) technology. Finally the 4×4 SRAM memory is proposed based on 1×1 SRAM with the help of 8T-SRAM. This memory is presented with array structures for reading and writing blocks. The simulation results reveal that the Power-Delay Product (PDP) term decreases 18% and 36% in the reading and writing cycles respectively for the stack forcing SRAM with the same array. The simulation is done with H-SPICE software in 32 nm technology under the condition of 0.9 V supply voltage, 500 MHz frequency and room temperature. [ABSTRACT FROM AUTHOR]

This paper proposes a low power and low output ripple regulator for radio frequency identification tags. The inner blocks of regulator is supplied from elementary stages output of rectifier. The proposed operational amplifier works on AB class and its bias is in adaptive biasing form. The bandgap reference and sampling voltage resistors used in this paper are completely designed with transistors which culminate in low power dissipation. The regulator output voltage is 1.07 V, while the output ripple is ±1.1 mV. The value of line regulation, power supply rejection ratio, and regulator efficiency are 5.5 mV/V, 45.2 dB, and 71.3%, respectively. A 111 µW power consumption has been calculated with 20 KΩ load. The simulation is done with the help of Cadence software in 0.18 µm CMOS technology, while its operational frequency is 960 MHz. The layout of the proposed regulator is 0.00125 mm2. [ABSTRACT FROM AUTHOR]

In this paper a backscatter modulator of passive tags used for RFID applications is proposed. For designing this backscatter modulator, QPSK modulation is utilized for transferring data from the tag to the reader. This modulator working in UHF frequency has high data rate and low power consumption. This circuit is simulated in 0.18μm CMOS technology with 1.8V supply voltage with the help of Cadence software. TLBO algorithm is applied in order to evaluate the optimized transistors sizes for maximizing the difference between various values of varactor in modulation states. The DC power dissipation and the chip area of the proposed modulator equal to 15.57nW and 5767μm², respectively. [ABSTRACT FROM AUTHOR]

In optimal PMU placement problem, a common assumption is that each PMU installed at a bus can measure the voltage phasor of the installed bus and the current phasors of all lines incident to the bus. However, available PMUs have limited number of channels and cannot measure the current phasors of all their incident lines. The aim of this paper is to recognize the effect of channel capacity of PMUs on their optimal placement for complete power system observability. Initially, the conventional full observability of power networks is formulated. Next, a modified algorithm based on integer linear programming model for the optimal placement of these types of PMUs is presented. The proposed formulation is also extended for assuring complete observability under different contingencies such as single PMU loss and single line outage. Moreover, the problem of combination of PMUs with different number of channels and varying costs in optimal PMU placement is investigated. Since the proposed optimization formulation is regarded to be a multiple-solution one, total measurement redundancy index is evaluated and the solution with the highest redundancy index is selected as the optimal solution. The proposed formulation is applied to several IEEE standard test systems and compared with the existing techniques. [ABSTRACT FROM AUTHOR]

Parameter estimation and dynamic modelling of power systems and their components are basis of design, planning and stability or security assessment in power systems. This study considers the estimation of power system model parameters by a global identification framework based on the maximum‐likelihood principle. The proposed framework is formulated as a non‐linear optimisation problem, which is solved by a hybrid method based on the bat‐inspired algorithm and differential evolution method. The combination of these algorithms makes the hybrid method faster and it obtains closer to the global minimum than a pure global method. Since noise and model uncertainties are inherent parts of system identification, the effect of these factors on the performance of the proposed identification framework are studied. Results based on synthetic data in frequency domain show that the estimated parameters are close to the correct values even in the presence of significant measurement noise and considerable uncertainties. [ABSTRACT FROM AUTHOR]

In this paper, an efficient and comprehensive formulation for the optimal placement of phasor measurement units (PMUs) is proposed to minimize the number of PMU installation subject to full network observability. Moreover, the formulation is extended for assuring complete observability under single PMU loss or single line outage cases. Since the proposed optimization formulation is regarded to be a multiple-solution one, both the installation cost and measurement redundancy are employed to differentiate the solutions with the same number of PMUs to be installed. In all of the investigations, the effect of zero-injection buses in the power system is considered. The effectiveness of the proposed method is verified via some IEEE standard systems and compared with some newly reported methods. Results show that the proposed method is simple to implement and more accurate compared to other existing methods. Moreover, by considering the presented method, the minimum number of required PMUs is decreased in some cases. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid modified binary particle swarm optimization and fuzzy system for obtaining the optimal number of PMUs which makes the power system completely observable. Observability assessment is done by means of topological observability rules. Moreover a new rule is employed which can decrease the number of required PMUs for full network observability. In all of the investigations, the effect of zero-injection buses in the power system is considered. Developed PMU placement method is illustrated using IEEE standard systems to demonstrate the effectiveness of the proposed algorithm. The results show that the whole system can be observable with installing PMUs on less than 20% of system buses. [ABSTRACT FROM AUTHOR]

Highlights: [•] The effect of channel capacity of PMUs on their optimal placement is investigated. [•] A method for optimal placement of PMUs with limited number of channels is proposed. [•] The method is extended for assuring full observability under various contingencies. [•] The scalability of the method is demonstrated on several IEEE test systems. [•] The results show that the proposed method can be applied to real-world network. [Copyright &y& Elsevier]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

Abstract: A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18µm CMOS technology while it works at 1.8V supply voltage. The VCO has a phase noise of −136dBc/Hz at 1MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4mW and the chip area is 10,400µm2. [Copyright &y& Elsevier]

Abstract: This paper seeks to investigate an approach of photonic reservoir computing for optical speech recognition on an examination isolated digit recognition task. An analytical approach in photonic reservoir computing is further drawn on to decrease time consumption, compared to numerical methods; which is very important in processing large signals such as speech recognition. It is also observed that adjusting reservoir parameters along with a good nonlinear mapping of the input signal into the reservoir, analytical approach, would boost recognition accuracy performance. Perfect recognition accuracy (i.e. 100%) can be achieved for noiseless speech signals. For noisy signals with 0–10db of signal to noise ratios, however, the accuracy ranges observed varied between 92% and 98%. In fact, photonic reservoir application demonstrated 9–18% improvement compared to classical reservoir networks with hyperbolic tangent nodes. [Copyright &y& Elsevier]

In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to reduce power consumption for low power applications, that in addition to reducing power consumption can perform well at high frequencies and remain stable. For the write operation, a new method has been used that removes the write bit line and uses the supply voltage in each cell for this operation and only by applying control signals. Also, the embedded bit line is used only for read operations and reduces the activity of the bit line, and due to being floating and the way of writing, eliminates the Precharge and Write Driver circuits, so, part of the power and area consumption has been reduced. According to the techniques used, the write and read noise margin is significantly improved and the write operation become easier to perform. Also due to the existence of a separate path for the read operation, RSNM is equaled to the HSNM. The average cell power at the frequency of 100 MHz for low power applications and 0.2V supply voltage, as compared to the best previous designs, has been improved by 34.9% and the leakage power of the hold state has been reduced by 27.6% and PDP has been improved by more than 35.2%, further, the maximum operating frequency of the cell has been increased by 39.1%, while it operates with the sub-threshold voltage of 0.2V to the frequency of 2.173 GHz. [ABSTRACT FROM AUTHOR]

A 3.1 to 10.6 GHz low-noise amplifier (LNA) in 0.18 μm technology is presented in this paper. The proposed LNA is implemented in a three-stage structure, including a current reusing cascode structure, a middle stage which compensates gain roll off in middle band and a buffer stage. The low-power dissipation of the design along with the high and flat gain provides a very appropriate combination in ultrawideband frequency design. The designed LNA achieves an average gain of 20 dB and a noise figure less than 2. The power consumption of the design is 3.7 mw. [ABSTRACT FROM AUTHOR]

This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms. [ABSTRACT FROM AUTHOR]

In this paper, the limitations in the Versatile Video Coding (H.266/VVC)-based communication systems are overcome through a bit rate controller. The limitations include the bandwidth and the buffer size. The proposed controller is of the variable bit rate type. It controls the bit rate fluctuation and maintains the buffer fullness within the admissible boundaries. These are performed by manipulating the quantization parameter. The proportional-integral (PI) controllers are more accurate than the proportional ones. Hence, a PI scheme is employed in the design process. The encoder shows stochastic and non-linear behavior. Moreover, the analytical model of its behavior is unavailable. These challenges are tackled via dynamic programming. The control criterion is developed using the Q-learning algorithm. Experimental results show the proposed method controls the bit rate with an average error equal to 1.4%. It is worthy of noting that the proposed method satisfies the buffering constraints. The average provided quality level in the proposed method is 36.47 dB. This amount is higher than those of the conventional methods. The performance analysis shows the proposed scheme has the bit rate saving capability compared with other methods. [ABSTRACT FROM AUTHOR]

In this paper, we propose an ultra-fast and adjustable optoelectronic converter over a wide wavelength range. The proposed structure includes a triplexer and an optical encoder. In this design, graphene nanoshells are coated on silicon photonic crystal rods in a ring resonator configuration. Adjustment of the triplexer is achieved by changing the chemical potential of the graphene nanoshells by applying an electrical voltage. This tuned triplexer extracts three quantized discrete levels from the continuous input signal, whereas the optical encoder provides 2-bit binary codes. According to plane wave expansion and finite difference time domain methods, the proposed device's maximum response time is about 2.2 ps, with a sampling rate of 454 GS/s while its footprint is as small as 818 μm2. [ABSTRACT FROM AUTHOR]

Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is presented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbitrary number of bit levels for processing at nano-scales. In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with other designs. The simulation results show the improvement of the evaluation parameters of the proposed RMC in compare with the other similar basic GDI-based comparators. Also, according to the simulation results, presented comparator is capable to work at extensive frequency ranges with higher maximum operating frequency (f max.). The effects of different process, voltage and the temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed circuit is robust against PVT variations and also noise-tolerable parameter. Moreover, the proposed RMC architecture is used in images applications. The results show that output images of the proposed inexact RMC have a very high quality and resemblance to the images generated by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for applications such as: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power charge pump (CP) is presented, which includes a switched-capacitor CP (SC-CP) as the main CP and an auxiliary current-steering CP (ACS-CP) to accelerate the lock process. By using a pulse width controller unit, the ACS-CP activates in predefined phase differences and turns off near the lock region. By utilizing the proposed CP, the issue of traditional current-mismatch error is removed. Also, a new glitch-free phase frequency detector (PFD) with removed reset feedback path to drive the proposed charge pump is presented. Post-layout simulation results in TSMC 65 nm CMOS technology with a 1.2 V supply voltage indicate that the proposed CP consumes 5.4 µW at 125 MHz in the lock state. Also, the proposed PFD illustrates ± 2π detection range and consumes 26.33 µW at 125 MHz. When the proposed CP and PFD are applied to a PLL system, settling time is decreased by more than 50 percent. Also, reference spur at 125 MHz frequency offset and at 8 GHz output frequency is −69 dB. The proposed PFD and CP together occupy an area of 0.0058 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we report a new design of a two-bit all-optical analog-to-digital converter (ADC) based on photonic crystal ring resonators. The photonic crystal structure has a square lattice of silicon rods, and four ring resonators carry out sampling and quantizing with linear and nonlinear rods at a wavelength of 1550 nm. Our calculations reveal that the proposed ADC has a maximum response time of about 4 ps and a sampling rate of 125 GS/s that is much faster than the ADC in previous studies. The proposed ADC also has a small area (called footprint) with a minimum leakage loss, considered the most suitable device in photonic integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for implementing an analog fully programmable membership function generator (MFG) with twin-cell topology which can operate in Transconductance-mode. The proposed multi-shaped MFG circuit is capable of generating the trapezoidal, triangular, S- and Z-shaped membership functions. Also, a full programmability disposition in all parameters of height, position and width is achievable. To make this purpose, a simple structure of complementary differential pairs is utilized which changing of their applied input constant voltages and bias current led into programming, independently. Moreover, the proposed MFG architecture has a stellar functionality which makes it suitable for implementing as a general-purpose fuzzy logic controller. Since in this proposed MFG approach, only 26 transistors are used, the chip area and total power dissipation can be decreased to 552 µm2 and 83.8 µW, respectively, which is reduced in comparison with the other works. The proposed MFG circuit is simulated in 65 nm standard CMOS technology with a single supply voltage of 1.2 V. The post-layout simulation results show that the proposed twin-cell MFG circuit is in great collusion which indicates a high delicacy of the proposed design, and the circuit presents the profit of negligible linearity error less than 5.2%. Furthermore, this proposed circuit is compared with a simulated MFG circuit named the comparative MFG, and the exported results show the improved functionality of the proposed twin-cell MFG, specifically. [ABSTRACT FROM AUTHOR]

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively. [ABSTRACT FROM AUTHOR]

In this paper, two low phase noise and power consumption VCO circuits, which are suitable for Internet of things (IoT) applications, are proposed. In the first structure, in order to have more control of the current consumption, the current shaping technique is used in the PMOS and NMOS biasing circuit. In the second structure, for increasing the oscillation amplitude and reducing the phase noise, independent biasing for the NMOS section is used. In both structures, to increase the frequency tuning range (FTR), without using a capacitor bank, the varactor is used in the biasing structure. In the first structure the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.37 mW, and -117.5 dBc/Hz, respectively, but in the second structure, the supply voltage, output frequency, power consumption, and phase noise are 0.8 V, 2.44 GHz, 0.62 mW, and -120 dBc/Hz, respectively. It should be noted that the two structures are designed and simulated in 65-nm CMOS technology. Finally, the results show that the figure-of-merit for the first and second structures is -190 dBc/Hz and -190.2 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a novel design of an 11-transistor SRAM bit-cell with a single-ended structure and memory mini-array with the bit-interleaving architecture support using the gate-diffusion input (GDI) method based on the gate-wrap-around (GWA) CNTFETs technology. The cell core of the suggested design is composed of a robust cross-coupled structure of two asymmetric inverters based on circuit-level methodologies. The proposed bit-cell scheme exhibits significant features such as improved write-ability, read data stability, and reduced leakage/short-circuit power due to the asymmetric write-assist method and inverter gates with stacked transistors, respectively. The simulation analysis has been done based on criteria such as static noise margins (SNMs), power-delay product (PDP), and the electrical quality/yield-based figure of merits (FoMs) in write/hold/read operation cycles. The suggested SRAM bit-cell demonstrates the best results with an average of 9.36 %, 48.53 %, and 22.82 %, respectively, for FoMs against other SRAM bit-cell schemes. The Monte-Carlo simulations in the 16-nm node show better results for the proposed bit-cell in the energy and failure probability per operation cycles than similar designs, with the best performance on average of 27 % and 8 %, respectively. Finally, to investigate the effectiveness of the suggested memory cell in the real application domain, an on-chip scaled power supply memory architecture for storing digital data based on quick response (QR) code using the proposed hardware algorithm is evaluated. Our results certify that the suggested memory array configuration in comprehensive FoMs based on quality and hardware efficiency metrics shows better results than the counterpart memory architecture. [ABSTRACT FROM AUTHOR]

In this paper, a novel dual-output switched-capacitor (SC) regulator is designed for EEG acquisition. At first, an efficient reconfigurable SC is designed with conversion ratios of 2/3 and 1/4 from 1.3 V input voltage. Reconfigurable SC with pulse frequency modulation (PFM) technique produces two single output voltages of 0.8 V and 0.2 V by changing the digital bit S. Then, a novel algorithm is proposed to produce two output voltages simultaneously and reduce voltage ripple. This SC regulator is self-controlled, and its control digital bits are entirely generated by the control logic circuit. Load current range is proportional to the EEG acquisition, in the range of 5 nA-1 μA and 500 nA-260 μA, for output voltages of 0.2 V and 0.8 V, respectively. The proposed dual-output SC is simulated in TSMC 65 nm CMOS technology and occupies an area of 2.09 mm2. The proposed SC regulator achieves a maximum power efficiency and output power of 92.8% and 193 μW, respectively. [ABSTRACT FROM AUTHOR]

The spatial distribution of nanoparticles and optical clearing can improve laser hyperthermia treatment. This article addresses an effective Three-dimensional model of tissue with/without optical clearing, based on the laser intensity and GNR concentration evaluation to prevent tumor regrowth within the tissue. Two different distribution methods of plasmatic nanoparticles are analyzed during irradiation. Numerical simulation of laser hyperthermia for ellipsoidal skin tumors allows the determination of therapeutic temperature and tissue thermal damage. The results confirm that optical clearing along with accurate nanoparticle distribution increases laser absorption and tumor degradation compared to non-optical clearing methods. Preventing healthy tissue damage is essential and a challenging factor in laser hyperthermia. Results show that the methods with optical clearing in desirable temperature between (50–60 °C) can damage the tumor by a high percentage in comparison to the methods without optical clearing and also, can save the healthy tissue. Using these technic in addition to the setting of laser parameters resulted in 93.58% of tumor damage versus 6.41% of healthy tissue damage. [ABSTRACT FROM AUTHOR]

In this paper, an analytical approach based on transmission line equivalent circuit (TLEC) is used to model planar solar cells. The proposed method has been applied to the all-dielectric planar solar cells with multilayer anti-reflection coating (ARC) and non-periodic distributed Bragg reflector (DBR) nanolayers. This analytical approach is very efficient and easy to be implemented. Consequently, it is straightforward to employ several optimization procedures to determine the optimum thickness for different layers. In this paper, optimization process according to the Fuzzy adaptive modified particle swarm optimization (FAMPSO) algorithm is utilized to maximize the absorption enhancement of these types of solar cells. Results demonstrate the possibility of wideband absorption in all-dielectric planar solar cells and comparable to the conventional light trapping structures. [ABSTRACT FROM AUTHOR]

In this paper, effects of geometry and spatial placement of quadrangle silicon nanowires (NWs) on the performance of laterally assembled NW solar cells are investigated. Two different approaches are proposed to reach the broadband absorption enhancement in these types of solar cells. In the first method, a semi-periodic array is used to have a better utilization of the optical antenna effect. The current density can be enhanced as a result of a compromise between the diffraction and optical antenna effects. In the second approach, multiple NWs with different geometries are employed to use the cavity modes of the various NWs. The best current density is achieved for the combination of both of these methods. The different parameters in each structure are selected using the optimization algorithm. Finally, a multilayer structure with the optimized dimensions is proposed to obtain the maximum achievable current density in ultrathin solar cells. The broadband absorption enhancement in the proposed structure is preserved for a wide range of incident angles. Using the multilayer NW arrays, it is possible to improve the absorption enhancement of solar cells without introducing more absorbing material. [ABSTRACT FROM AUTHOR]

In this paper, a subsystem consisting of a microstrip bandpass filter and a microstrip low noise amplifier (LNA) is designed for WLAN applications. The proposed filter has a small implementation area (49 mm2), small insertion loss (0.08 dB) and wide fractional bandwidth (FBW) (61%). To design the proposed LNA, the compact microstrip cells, an field effect transistor, and only a lumped capacitor are used. It has a low supply voltage and a low return loss (–40 dB) at the operation frequency. The matching condition of the proposed subsystem is predicted using subsystem analysis, artificial neural network (ANN) and adaptive neuro-fuzzy inference system (ANFIS). To design the proposed filter, the transmission matrix of the proposed resonator is obtained and analysed. The performance of the proposed ANN and ANFIS models is tested using the numerical data by four performance measures, namely the correlation coefficient (CC), the mean absolute error (MAE), the average percentage error (APE) and the root mean square error (RMSE). The obtained results show that these models are in good agreement with the numerical data, and a small error between the predicted values and numerical solution is obtained. [ABSTRACT FROM PUBLISHER]

A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. [ABSTRACT FROM AUTHOR]

• A hollow-core PCF composed of magnesium fluoride was proposed to identify toxic and hazardous gases. • The structure is based on the quasi-crystal arrangement of air holes. • Numerical simulation results showed that the fiber proposed in this study has a sensitivity coefficient above 50%, relatively low loss, and low dispersion. • The device is suitable for identifying toxic and dangerous gases. • The detection of which using this tool prevents combustion and explosion in the drilling process. In this paper, a hollow-core photonic crystal fiber (PCF) composed of magnesium fluoride is designed to identify toxic and hazardous gases. Its band structure is calculated using the well-known plane wave expansion method. The numerical results show that the proposed structure has a relatively wide photonic bandgap (PBG) in the wavelength range of 1 to 3.3 μm covering the near- and mid-infrared wavelength ranges. Then, by applying optical pulses with a wavelength in the range of the PBG to the proposed PCF, its propagation behavior is calculated by solving the nonlinear Schrödinger equation using the split-step Fourier method. The type of gas can be identified by observing and comparing the frequency responses of the gas-filled PCF with the absence of gas injection. Simulation results show that the fiber proposed in this study has a sensitivity coefficient of more than 50%. The low loss, low dispersion, and high accuracy of the proposed fiber make it a suitable tool for identifying toxic and dangerous gases such as methane and hydrogen sulfide in the drilling and oil exploration industry. Identifying them using this tool prevents combustion and explosion in the drilling process. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

A compact microstrip diplexer for 4G wireless communication systems is proposed in this paper. This diplexer consists of two bandpass filters based on the triangular open loop asymmetric stepped impedance resonator in order to have a small size as well as simple structure. The T-shaped open stub is used for attenuating the undesired modes. Attenuation level for the proposed diplexer is less than 21 dB in the range of 0–10 GHz owing to using this T-shaped open stub. The center frequency of each filter can easily change in the range of 20 MHz through varying the gap length of the resonator without any changes in the whole structure of the diplexer. The result of this is the stability of other parameters like insertion loss, return loss and isolation. This diplexer has a narrow band frequency response that makes it suitable for modern wireless communication systems. Finally, the diplexer is fabricated at 2.30 and 2.55 GHz and measurements demonstrate a good agreement between simulated and fabricated diplexer. [ABSTRACT FROM AUTHOR]

Design approaches to carry out broadband absorption in laterally assembled hexagonal silicon nanowire (NW) solar cells are investigated. Two different methods are proposed to improve the current density of silicon NW solar cells. It is observed that the key to the broadband absorption is disorder and irregularity. The first approach to reach the broadband absorption is using multiple NWs with different geometries. Nevertheless, the maximum enhancement is obtained by introducing irregular NWs. They can support more cavity modes, while scattering by NWs leads to broadening of the absorption spectra. An array of optimized irregular NWs also has preferable features compared to other broadband structures. Using irregular NW arrays, it is possible to improve the absorption enhancement of solar cells without introducing more absorbing material. [ABSTRACT FROM AUTHOR]

ABSTRACT In this article, a tunable branch-line coupler with a novel structure is designed to operate at 5.7GHz. A design method is based on miniaturization method with adjusting the resonance frequency. The proposed coupler without taped line feed structures operated at 5.62 GHz, and it has a size of 55.8 mm2 while its performance is reasonable. To improve the performance, the taped line feed structures are added. The wideband response exhibits that the proposed coupler acts properly with the spurious harmonics up to 11.4 GHz. In addition, at 5.7 GHz, the good insertion loss (2.3 dB) and coupling factor (2.6 dB) are obtained. The proposed coupler is simulated, fabricated, and measured. The results show that there is a good agreement between the simulation and measurement results. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1081-1084, 2015 [ABSTRACT FROM AUTHOR]