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With decreasing dimensions and increasing complexity, semiconductor devices are getting more difficult to fabricate. In particular the allowed deposition temperature becomes lower. Amorphous materials, which do not require annealing steps, are therefore becoming more interesting. First principles modelling of amorphous materials is, however, way more complex than modelling crystalline ones. Especially to screen for new materials, a fully ab initio approach is hence too expensive. We take on this challenge by employing a combination of high throughput first principles calculations and artificial intelligence (AI). We construct 4500 atomistic models, each containing 200-atoms, to capture the properties of amorphous phases of primary, X-O, and binary, X-Y-O, metal oxides. For these models, we calculate the relevant properties for a transistor channel. Expanding this exercise to more complex metal oxides would lead to a prohibitively large number of options. We solve this problem by training support vector regression models based on the data generated for the primary and binary oxides to predict the properties of ternary and more complex oxides. By combining the trained models, we construct an objective function that, at its minimum, points to the optimal composition in terms of electronic performances and material stability. After screening a series of objective functions, we identify the Zn-Mg-Al-O metal oxide (Zn and Mg around 40-50 at%, Al below 10 at%) as being the most interesting improvement to the current industry standard a-IGZO for the development of a high charge carrier mobility layer of a thin film transistor compatible with low deposition temperature requirements. It is predicted to combine an improvement in terms of electron mobility and chemical stability with respect to a-IGZO. This method, combining first principles calculated data with AI, is however not restricted to finding new materials for the active layer in a thin film transistor. From a general perspective, this approach can be used for any alloy or compound discovery problem, in which the pivotal material properties can be calculated for, in the order of a thousand, relevant one- and two-element materials.

In this work, IGZO device integration is reported leveraging our 300mm-fab facilities. Our objective is mainly to gain insights into the process and material elements which drive the control of the performance parameters of IGZO nFETs. To control the final doping of the IGZO channel, it is well reported in literature that a final oxygen anneal can be applied to passivate the oxygen vacancies which are formed during the device fabrication. This technique is also used in our 300mm flow. As it might be expected, in front gate IGZO nFETs, the passivation efficiency is limited by the presence of the top metal gate stack. Therefore, it seems important to limit the formation of the oxygen vacancies during the deposition of the gate dielectrics. Three oxides were studied: SiO2, Al2O3 and HfO2 on top of the IGZO channel. After oxygen annealing, only PECVD-SiO2 shows a large recovery while for Al2O3 and HfO2, it remains low. This result challenges the implementation of conventional water-based high-K materials in gate first IGZO integration. Contrary to the use of undoped IGZO in the channel for IOFF control, contacts can rely on maximizing the oxygen vacancies to increase the dopant concentration in the S/D regions. When not done locally, it could be an extra source of variability. This doping is made through oxygen scavenging from IGZO by a thin metal contact barrier. Low specific contact resistivity down to 1x107 Ohm.cm2 is demonstrated when Ti is thinner than 5nm. With thicker barrier, the formation of TiO2 and specific alloys is taking place at the IGZO/Contact barrier interface. This is both confirmed by ab initio simulations and by advanced physical characterization techniques. Regarding the channel, X-ray diffraction techniques are extensively here since this is a nondestructive in-fab technique that provides detailed information about the crystallographic structure of the IGZO material. We show a typical spectrum where clear peaks/humps are seen and attributed to: 1. amorphous IGZO, 2. CAAC-IGZO and 3. a previously not reported, to the best of our knowledge, phase called here s-IGZO. The s-phase is only formed under certain conditions of power, temperature and oxygen flow during material deposition. Thick IGZO (>12nm) back-gated nFETs with active layers submitted to final O2 anneal are used to study the different phases of IGZO and their electrical impact on device parameters. In this configuration, the carrier transport preferentially occurs in the bottom half of the IGZO channel while the top half (SiO2/IGZO interface) mostly drives the electrostatic control of BG transistors. The amorphous IGZO has much reduced spread in VTH-ON and higher ID,LIN (~mobility) than that of CAAC-IGZO. Reliability tests have also been carried out to compare the two phases and the results show the existence of two competing PBTI degradation mechanisms for CAAC-IGZO. It is important to report the degradation over time and different VG stress because a cut line at a specific value could have shown no BTI degradation of CAAC-IGZO and then attributing an unfair benefit of this phase over the a-IGZO phase. Combining these findings to some other results where the sheet resistance of IGZO under hydrogen exposure depends on the phases, we can reasonably conclude that CAAC owns different doping levels in comparison to a-IGZO. Based on the previous learning about n-type dopant location in IGZO, we show that the performance of transistors keeps increasing when the channel length is reduced and scales with the channel width. A measure of the VTH-ON variation has been performed at the 300mm wafer scale from long to ~120nm LCH and down to 200nm WCH dimensions. The figure in attachement shows the Id-Vg curves of >100 Back Gated IGZO-nFETs with no failed devices detected. The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV. In conclusion, we have demonstrated in this study scaled IGZO nFETs with excellent VTH_ON control using an industry compatible 300mm process flow. This has been achieved thanks to a careful mapping of n-type doping in the three dimensions of the IGZO channel. While semi-crystalline IGZO seems to be more robust against hydrogen than that of amorphous-IGZO, a new IGZO phase is found to help boost ION at short channel. The demonstration of back-gate IGZO nFETs with low variability and relatively high drive will benefit to the top-gate architecture development. This will provide new opportunities for the IGZO-based devices like an “on-the-fly” VTH setting for the performance control of advanced applications. Figure 1

As conventional CMOS scaling is reaching its physical limits with ever more constraining design restrictions, new device architectures are being explored as potential fin-field-effect-transistor (finFET) replacements for future technology nodes. Among the various options, vertically stacked lateral nanosheet (NS) FETs with a gate-all-around (GAA) configuration are considered the most promising and mature candidates to use next to help preserve the overall power-performance logic roadmap [1-5]. These devices offer improved electrostatics control and allow additional design flexibility for applications-driven power and performance tuning. Indeed, the possibility to fabricate on the same wafer varying NS widths, enabling devices with a wide range of effective widths (Weff), is one of their key attractive features. Wider GAA NS FETs enable higher drive current (ION) gains. However, as shown in ref. [2], these can be compromised for shrinking gate length (Lgate) due to degraded electrostatics, e.g., worst subthreshold slope (SS) values. As for narrower NS FETs, despite their lower ION, they also correspond to decreased channel, overlap and fringe capacitance values. In addition, as extension and contact resistances can also depend substantially on the NS cross-sectional areas [2], several trade-offs will ultimately determine the NS device configuration that best fulfills the requirements for a given application. Fabrication-wise, GAA lateral NS FET devices can be regarded as a natural extension of finFETs sharing many of their building blocks. Some of the key process steps are illustrated in Fig. 1, wherein Si/SiGe multi-layers are epitaxially grown prior to fin patterning to form vertically stacked silicon lateral NS. At replacement metal gate (RMG) module, prior to gate stack deposition, NS are released by implementing a selective removal of the SiGe from the Si/SiGe multi-layer fins. This is a key step, critical for preserving the integrity of the Si channels in terms of shape, dimensions and quality of the NS surfaces. Another crucial step occurs earlier on in the flow at STI module, where insertion of a thin nitride liner prior to STI oxide fill and densification anneal can prevent Si/SiGe fin oxidation and Ge diffusion. Such processing helps preserving the fins profile while also protecting them from irreversible strain modifications [4]. Fig. 2 shows an example of a TEM image from a device built with two vertically stacked NS. The well-preserved shape of the NS also enables implementation of a highly uniform and scaled gate stack on all NS surfaces with smooth interfaces [6]. This is of increased importance for scaled GAA NS FETs where reduced vertical distance between the stacked NS is required to minimize device parasitics. Another type of GAA NS transistors are the vertical NS (VNS) FETs for which Lgate is defined vertically and hence can be relaxed without impacting the device footprint. Representing a more disruptive technological transition, both in terms of device fabrication and circuit layout design, these devices have nevertheless the potential to open up new scaling paths and enable denser, better performing circuits, e.g., for SRAM (as the cell transistors) or MRAM (as the cell selector) memories [7,8]. Fig. 3 illustrates some of the key steps followed to implement an RMG module in GAA vertical nanowire (VNW) or VNS FETs. A layout dependence for some of the processes used in this block can be seen to impact DC characteristics such as VT, ION. The VNW/VNS doping vs. wire/sheet dimensions also needs to be accounted for in case of junctionless devices [8, 9]. RMG can also be used to enable a scheme that boosts the mobility in vertical channels via process-induced stress as described in Fig. 4 for NMOS. Here, a SiGe stressor is epitaxially grown around the Si channel after spacers formation. This stressor is removed at RMG module, after dummy gate removal, with stress memorization into its surroundings enabled by the fact that the layer encapsulating the top of the pillars remains connected (at some places) to the bottom isolation layer. Stress and ballistic current simulations indicate that up to ~19% higher ION can hence be obtained [8]. References [1] H. Mertens et al., VLSI Tech. Dig., 158 (2016). [2] D. Jang et al., IEEE Trans. Elec. Dev., 64(6), 2707 (2017). [3] N. Loubet et al., VLSI Tech. Dig., 230 (2017). [4] H. Mertens et al., IEDM Tech. Dig., 828 (2017). [5] P. Weckx et al., IEDM Tech. Dig., 505 (2017). [6] A. Veloso et al., SSDM Tech. Dig., 559 (2019). [7] T. Huynh-Bao et al., SPIE Proc., 978102 (2016). [8] A. Veloso et al., IEDM 2019 (in press). [9] A. Veloso et al., SSDM Tech. Dig., 221 (2017). Figure 1

Introduction. The Gate-All-Around (GAA) Nanowire (NW) or nanosheet (NS) architecture provides superior short-channel effects control and is widely considered as one of the most promising candidates to replace finFETs in advanced Logic technology nodes. Compared with their horizontal implementation, vertical NWs (or NSs) FETs [1] offer some clear advantages, appearing promising devices to overcome some of the limitations encountered by conventional CMOS scaling as it reaches its physical limits and faces interconnect routing congestion. They have the potential to yield smaller circuits with reduced power consumption [2], allowing relaxed Lgate without impacting the device footprint. While their fabrication is challenging, several schemes have been proposed for improved process control and device performance [1]. In this work, the static parameters of vertical NW junctionless (JL) nMOSFETs have been studied for devices with two different Replacement Metal Gate (RMG) cap layer widths (see schematics in figure 1), encapsulating the top part of the pillars during processing at the RMG module. It will be shown that this strongly impacts the static device parameters: the threshold voltage (VT), the maximum transconductance (gmmax) and the dynamic output resistance (rout). Moreover, a correlation is shown with the input-referred voltage noise Power Spectral Density (PSD) SVG at 10 Hz, which could be explained in terms of a process-induced variation in the diameter D of the NWs. Experimental. A detailed process description has been recently reported [1]. A 55 nm in situ P-doped n+ layer is deposited by CVD on a low-resistivity silicon substrate (source contact), followed by 90 nm undoped silicon and again 55 nm n+ Si. The RMG stack consists of IL-SiO2/HfO2/TiN/W. An RMG cap consisting of SiO2 is used to encapsulate the top of the pillars. Here, devices with two different cap widths and 100 wires in parallel are compared. On-wafer DC and low-frequency noise measurements have been performed using a BT1500 Parameter Analyzer and an E4727A Advanced Low-Frequency Noise Analyzer from Keysight, respectively. Measurements have been performed in linear operation at a drain voltage VDS=50 mV, while the gate voltage VGS is stepped from weak to strong inversion. Results and Discussion. Figure 1 and 2 compares the linear input ID-VGS characteristics of a set of narrow and wide cap vertical NW nFETs. While there is obvious device-to-device variability, the wide-gap devices (Fig. 2) clearly exhibit a lower VT than their narrow-gap counterparts in Fig. 1. The transconductance (gm) plots of Figs 3 and 4 reveal another trend: devices with a high VT generally exhibit a lower gmmax and vice versa. This is even so within each flavour of devices in Figs 3 and 4. As will be shown, nFETs with a high(er) VT and lower gmmax also tend to exhibit a higher rout. Finally, Figs 5 and 6 demonstrate that the corresponding SVG at f=10 Hz is smaller for the wide-cap devices, especially around VT, where the minimum noise PSD is found. As will be shown, the noise spectra are dominated by 1/f-like noise (fVG could suggest a difference in oxide/interface trap density, but this is not reflected in the subthreshold swing nor in the PBTI behaviour [1]. On the other hand, it has been reported before that the VT of NW transistors increases for reduce D [3]. This could well explain also the lower gmmax (scales with D) and the higher SVG (scales with 1/D). The different NW diameter could result from the different dummy dielectric removal [1]. References [1] A. Veloso et al., to be published in the Proc. of IEDM 2019. [2] T. Huyng-Bao et al., SPIE 2016, 978102 [3] A. Veloso et al., J. Phys: Condens. Matter, 30, 384002 (2018). Figure 1

Using the deterministic version of our hot-carrier degradation (HCD) model, we perform a statistical analysis of the impact of random dopants (RDs) on the HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime, the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To this end, a model is used, in which three subproblems constituting the physical phenomenon of HCD are considered: carrier transport in semiconductor structures, description of microscopic defect formation mechanisms, and simulation of degraded device characteristics. An analysis is performed by varying the gate length, fin width and height. It is shown that HCD becomes stronger under fixed stress conditions in transistors with shorter channels or wider fins, while the channel height does not substantially affect HCD. This information can be important for optimizing the architecture of transistors with the fin-shaped channel to suppress degradation effects.

We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HCD), with exponential- and step-like shapes. First, we analyze how these localized DPs affect the transistor I-V and model the complex relation between DP and FET degradation by considering the degraded FET as a series circuit of an undegraded transistor (the source side) and a degraded one (the drain side). We also compare how the same DP causes different degradation for changes in the device structure. Second, we use the DP simulations to qualitatively understand the DP dependence on stress voltages in measured FETs and assess how uniquely a DP can be extracted from degraded I-V metrics. The results are of interest for HCD modeling.

In this study, high-performance few-layered ReS2 field-effect transistors (FETs), fabricated with hexagonal boron nitride (h-BN) as top/bottom dual gate dielectrics, are presented. The performance of h-BN dual gated ReS2 FET having a trade-off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h-BN dielectric has almost no defects and provides a physical distance between the traps in the SiO2 and the carriers in the ReS2 channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h-BN dual-gated ReS2 with a high mobility of 46.1 cm2 V−1 s−1, a high current on/off ratio of ≈106, a subthreshold swing of 2.7 V dec−1, and a low effective interface trap density (Nt,eff) of 7.85 × 1010 cm−2 eV−1 at a small operating voltage (2 channel through Y-function method as a function of constant top gate bias.

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single-and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: ( $i$ ) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-R bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond-breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

We report on vertically stacked lateral nanowires (NW) / nanosheets (NS) FETs with a gate-all-around (GAA) configuration as promising candidates to replace finFETs for advanced sub-5nm technology nodes, as they offer higher flexibility to obtain a better power-performance metric for logic applications. Moreover, these devices can be fabricated in a cost effective, co-integration scheme with vertical NW/NS GAA FETs for increased on-chip memory content, thanks to the latter's potential for enabling highly scaled, more energy efficient memory cells, e.g., as the SRAM cell transistors or as the selector for MRAM. Key features and technological challenges for both types of NW/NS FETs will therefore be presented and discussed in this paper.

For the first time at our knowledge, we demonstrate a sub-µm indium-gallium-zinc oxide (a-IGZO) (vertical) Schottky diodes on a 300mm platform. We demonstrate that the choice of a suitable Al2O3-based encapsulation layer is critical in order to achieve near-ideal diode parameters (n, φSBH) and uniform wafer-level behavior. We show, for the smallest devices of 0.5µm x 0.5µm, an ideality factor n of 1.5 and Schottky barrier height (φSBH) of 0.7 eV while simultaneously achieving a peak current density of 0.1 MA/cm2.

In this work, we address two open issues of HotCarrier Degradation (HCD) on n-type FinFET devices. Firstly, the controversial impact of fin width is studied in terms of exact {V OV ,V D } stress conditions and taking in account the impact of external parasitic series resistance and Self-Heating Effects (SHE). Secondly, the impact of Hydrogen/Deuterium High-Pressure Anneal (HPA) on both time-0 and reliability is evaluated.

To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO 2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO 2 and SiN thicknesses, but -β is mainly dependent on the SiO 2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.

For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.

We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs which offer attractive opportunities for ultra-scaled circuits. An in-depth evaluation is presented on the impact of doping and key device dimensions to improve the performance, variability, noise and reliability behavior for junctionless (JL) vs. inversion-mode (IM) vertical FETs built with an RMG scheme. The latter enables a novel concept to introduce stress in VFETs for enhanced mobility with up to a19% higher I ON predicted. SiGe/Si pillars and self-aligned spacers offer a solution to gate vertical (mis)alignment towards the S/D. As MRAM selector, VNS FETs can allow substantial area reduction (64% for 2VNS per cell; 3nm node design rules) vs. finFET based cells, with smaller read/write energy consumption and latency times.

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH3/NF3remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si0.75Ge0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.

While it is proven that horizontal cylindrical Gate-All-Around (GAA) transistors can enable ultimate MOSFET scaling without the need of disruptive technology changes, the reliability aspects of such devices are still barely characterized and understood. In this work, we will describe the main reliability concerns of these novel devices, comparing their BTI performance with standard FinFETs. Moreover, instead of focusing only on specific reliability issues (e.g. BTI, hot-carrier, TDDB, etc) that are often treated separately, we also assess the degradation of stacked GAA nanowire nFETs in the full {V g , V d } bias space, which allows to identify all the degradation modes and how they interact with each other. The empirical modelling of the degradation includes various channel hot-carrier (CHC) modes as well as BTI and allows an extrapolation to 10-years lifetime in the full bias space.

A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with confined architectures, such as fin and nanowire (NW) FETs. Although the view on whether SH accelerates or inhibits HCD in n-channel devices is controversial, it is commonly accepted that in p-channel FETs HCD becomes more pronounced due to SH. Therefore, we develop a framework for modeling coupled HCD and SH and validate it against experimental data acquired in p-channel Si NWFETs. This framework incorporates a carrier transport solver linked to a solver for the lattice heat flow equation; the latter solver allows one to evaluate a non-uniform lattice temperature distribution in the device. Carrier energy distribution functions obtained considering coordinate-dependent lattice temperature are used to calculate the rates of the multiple- and single-carrier processes of Si H bond dissociation. In addition to perturbation of carrier transport by SH, elevated lattice temperature results in enhancement of the thermal contribution to the bond rupture rate and shortens vibrational lifetime of the Si H bond, thereby reducing the multiple-carrier process rate. All these three aspects are captured by our framework, importance of each of them is analyzed, and our approach was shown to accurately reproduce experimental data.

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1

We present the first physics-based approach to modeling the effect of random dopants on hot-carrier degradation (HCD) in FinFETs, which is based on a statistical analysis of HCD performed over an ensemble of 200 transistors with different random dopant configurations. As a reference, the results obtained with the deterministic version of our HCD model are used. The statistical analysis shows that degradation traces and device lifetimes have quite broad distributions and that the deterministic model tends to overestimate HCD and makes pessimistic predictions on device lifetime. Moreover, lifetime distributions evaluated for high stress voltages and for biases close to the operating regimes have different shapes which makes backward lifetime extrapolation challenging, thereby demonstrating that full physics-based HCD treatment is of crucial importance.

MIM planar capacitors with different spacer dielectrics (SiN, SiCO and SiCBN) of varying thickness deposited on a 2nm Hf02 gate dielectric, were fabricated to investigate the gate/spacer stack intrinsic electrical reliability performance. The polarity dependent leakage current of gate/spacer dielectric stacks is understood by employing band diagram analyses and simulations using the Ginestra™ software. The asymmetrical J-E characteristic of the Hf02/SiN dielectric stack is attributed to the presence of a high defect density in the Hf02/SiN interface region originating from the deposition process. On the other hand, the higher as-grown defect density in SiCO and SiCBN results in a symmetrical J-E characteristic. A low defect generation efficiency in the thin SiN stacks has been demonstrated using stress induced leakage current and charge to breakdown studies. The underlying mechanisms can be linked to a change in degradation mechanism from electronic excitation to electron induced vibrational excitation, which is valid for low defect density dielectric systems. To ensure low leakage currents and robust dielectric breakdown characteristics for ultra-thin spacer layers below 5nm, it is important to control defect densities below 1019cm−3ev−1in the film.

Degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), as well as the associated time-dependent variability, dictate the limit on the acceptable operating voltage conditions in modern deeply-scaled VLSI devices. Based on large statistical datasets, acquired using specifically designed on-chip arrays, we experimentally obtain DC degradation maps for both $\boldsymbol{n}$ - and $\boldsymbol{p}$ -type FETs. Defect-centric based analysis of the statistical parameters at every $\boldsymbol{V_{G}}, \boldsymbol{V_{D}}$ bias point provides physical insights in the underlying single- and multi-carrier degradation processes. As a result, we can separate the defect charging contributions of each degradation mechanism and describe to which extent these mechanisms co-interact. We finally present a simplified model (the “3-bucket” model) that is able to describe the degradation statistics up to $3\boldsymbol{\sigma}$ of a device population subject to an arbitrary combination of BTI and HCD stress.

We present a stochastic description of hot-carrier degradation (HCD) which captures the impact of random traps (RTs) and random dopants (RDs) using our deterministic physical model for HCD. For each combination of stress voltages and stress time we generate 10,000 different samples with each of them having a unique configuration of RTs and RDs. Our analysis shows that both RTs and RDs broaden the set of degradation traces and device lifetimes, herewith resulting in average (over the sample ensemble) changes in the linear drain current lower than the nominal values from the deterministic model. Although at higher stress voltages device lifetimes follow bimodal normal distributions, at stress biases close to the operating regime the distributions are substantially different. Therefore, a proper modeling of HCD should be based on a full statistical description.

Simulations of hot-carrier degradation of nanowire field-effect transistors are reported. The simulations rely on the carrier energy distribution function, obtained by solving the Boltzmann transport equation. To model the contribution of impact ionization, the hydrodynamic scheme is employed. A range of pertinent physical mechanisms is invoked and discussed to adequately reproduce HCD measurements in the full ( $V_{\mathrm{g}}, V_{\mathrm{d}}$ ) bias space. Impact ionization is discussed as an important ingredient of HCD at low gate, high drain voltages.

We report on vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs, integrated in a CMOS dual Work Function Metal Replacement Metal Gate (RMG) flow. The integration of a lower temperature STI module and a SiN liner, designed to mitigate the oxidation-induced NW size loss and improve the width/height aspect ratio and NW controllability, is validated electrically. Additionally, Si GAA devices with reduced vertical nanowire spacing are demonstrated. The challenges in terms of Work Function Metal thickness scaling are highlighted, and a thinner nMetal process with low V TH capability and no J G /PBTI lifetime penalty is proposed. Electrically, these process innovations lead to a large improvement of I ON /I OFF performance and short channel margin. Finally, a ring oscillator circuit demonstration is shown, with a improvement of gate delay from 24ps down to 10ps at matched V DD demonstrated.

We compare and model the main reliability limitations of stacked Gate-All-Around (GAA) $n$ -/ $p$ -channel Silicon and strained $p$ -channel Germanium Nanowire (NW) transistors. Stress measurements in the entire $\{V_{G},\ V_{D}\}$ space allow to separate the different degradation modes and how they interact with each other. We show that these degradation modes are not universal, as they have a different relative weight depending on the considered technology, and that they can show different acceleration mechanisms. Moreover, we also discuss the impact of self-heating effects (SHE) by means of activation energy extraction in the entire $\{V_{G},\ V_{D}\}$ map.

In modern VLSI devices, a multitude of degradation mechanisms dictates limits on the tolerable voltage conditions to guarantee reliable operation for extended times. The most critical degradation mechanisms such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD) are mostly studied in terms of their mean degradation. By obtaining large statistical datasets, covering a multitude of conditions in the {V G ,V D } bias space, typically obtained by measurements on dedicated on-chip FET arrays, we show that we can identify the active degradation mechanisms and understand their impact on both FET time-zero metrics, as well as on the time-dependent variability.

As two-dimensional CMOS scaling is reaching its physical limits, maintaining profitable node-to-node cost-per-transistor gains requires increasingly constraining design restrictions. To help preserve the power, performance, area, and cost (PPAC) logic roadmap several innovations are being explored, such as cell height reduction by decreasing the number of metal tracks. This allows compensating for the recent trend of a more modest pitch scaling, but it also requires fin depopulation from two fins to one fin per finFET transistor for ultra-scaled cells with reduced number of metal tracks [1,2], which impacts the device performance. As such, in order to keep the scaling gains, introduction of novel device architectures is needed, with gate-all-around (GAA) nanowire (NW) or nanosheet (NS) FETs [2-8] being regarded as the most promising finFET replacements for advanced nodes (Fig. 1). These devices provide better electrostatics allowing further gate length (Lgate) scaling, with NS offering higher current drivability (ION) per layout footprint than NW thanks to larger effective widths (Weff). Furthermore, by having the option to vary the NS Weff on the same chip/wafer, this enables additional design flexibility, typically targeting wider NS for high performance computing and narrower NS for low power applications [5,7,8]. At the same time, vertically stacking several NS enables further boosting ION at the expense of an increase in parasitic capacitance. Minimizing the latter is crucial for delivering both optimal performance and power efficiency. That can be achieved by reducing the vertical distance between the stacked lateral NS as demonstrated in Fig. 2 and via the implementation of inner spacers in-between them [2,6]. Both features introduce considerable challenges for device fabrication. However, it still shares many of the building blocks of a finFET flow thus allowing a smoother technological transition for manufacturing as compared to other device architectures. In the case of the NS vertical pitch, its shrinkage requires scaled Si/SiGe-multilayer stacks growth and thinner gate stacks that can be implemented with the guarantee of similar gate control on all NS surfaces. That has been demonstrated for a stack with an alternative, thinner (T < 0.2V - NMOS), while showing improved noise and reliability behavior [9]. Another GAA device architecture, with vertical NW or NS (VNW/VNS) and vertically defined Lgate, has been shown to have the potential to enable denser and more energy efficient SRAMs and MRAMs when used as the cell transistors or selector, respectively [10-13]. In the overall scaling roadmap, the latter type of memory has been gaining increased momentum as an alternative for enabling large, ultra-high-density last-level caches for systems with reduced area and energy. Overall, GAA VNW/VNS FETs represent a more disruptive technological transition, moving from 2D to 3D layouts. Nevertheless, they can also open new scaling paths in the third dimension. In this context, the feasibility of co-integrating on the same wafer and in a cost-effective way finFETs (or GAA lateral NS FETs) for high performance logic and GAA VNS FETs as MRAM selector is evaluated by process simulations, experimentally validated for each type of devices (Fig. 3). In this scheme, cost adders were minimized by sharing the maximum number of critical process steps for both FETs. A replacement metal gate process, standardly used in finFETs and lateral NS FETs can be also advantageous for VNS FETs as it can allow shrinkage of the channel cross-section for improved electrostatics (without impacting the bottom/top S/D [14]), while also enabling new techniques for stress-induced mobility enhancement [12]. Specific for VNS FETs, a self-aligned gate electrode can be easily implemented by relying on the different oxidation kinetics of Si and SiGe and using SiGe/Si/SiGe instead of Si-only pillars. References [1] M. Garcia Bardon et al., IEDM Tech. Dig., 687 (2016). [2] H. Mertens et al., IEDM Tech. Dig., 828 (2017). [3] A. Veloso et al., VLSI Tech. Dig., 138 (2015). [4] H. Mertens et al., VLSI Tech. Dig., 158 (2016). [5] D. Jang et al., IEEE Trans. Elec. Dev., 64(6), 2707 (2017). [6] N. Loubet et al., VLSI Tech. Dig., 230 (2017). [7] S. Barraud et al., IEDM Tech. Dig., 677 (2017). [8] C. W. Yeung et al., IEDM Tech. Dig., 652 (2018). [9] A. Veloso et al., SSDM Tech. Dig., 559 (2019). [10] T. Huynh-Bao et al., SPIE Proc., 978102 (2016). [11] T. Huynh-Bao et al., DAC, 267-TY328, s13p1 (2019). [12] A. Veloso et al., IEDM 2019 (in press). [13] A. Veloso et al., SSDM Tech. Dig., 221 (2017). [14] A. Veloso et al., ECS Trans., 72(4), 31 (2016). Figure 1

We report a novel time-dependent dielectric breakdown (TDDB) lifetime model which accounts for the impact of various sources of variability. We prove that the standard Weibull and Lognormal distributions normally used for FEOL and BEOL TDDB lifetime predictions respectively are not adequate for MOL TDDB analysis. Due to the many sources of variability, only a combination of different variability separation techniques — even including a convolution of a Weibull and Lognormal distribution as a last resort for some cases — can reconcile the intrinsic breakdown mechanism with the extra variability. This approach is shown to correctly fit and predict the reliability of integrated low-k spacer dielectrics.

Time-dependent variability of modern VLSI devices, due to their associated degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), dictates a limit on the tolerable operating voltage conditions of the device. Based on a large statistical dataset, obtained by measurements on dedicated on-chip FET arrays, we propose a methodology to identify and de-convolute the active degradation mechanisms and subsequently calculate the respective lifetimes in bias {Vg, Vd} space. Utilizing a limited set of parameters for each of the identified failure mechanisms, we show excellent agreement with experimental degradation data over the entire measurable bias space. Finally, by experimental assessment of thermal resistance and degradation activation energies, we can project a self-heating-aware FET lifetime at operating conditions across the entire bias space.

In this work, the impact of 1\times 5μm} Via-last integration on an advanced bulk FinFET technology is investigated. We find that mechanical impact of TSV proximity is below detection limit, however plasma-induced damage (PID) is observed on small devices (high antenna aspect ratio). Finally, a back-side anneal raising the TSV thermal budget shows no increase of mechanical impact though it partially cures PID damage on small devices.

We study hot carrier degradation in Si 0 . 75 Ge 0 . 25 p-FinFETs by measuring degradation maps in the entire bias space and compare with Si counterparts. Hot carrier effects are found to be exacerbated in SiGe due to the reduced impact ionization threshold in small bandgap semiconductors, the larger hole mean free path, and the consequently enhanced generation of secondary electrons. Both hole and electron injections are observed and they partially compensate each other at some stress biases. Even at operating voltages of relevance for core logic applications, off-state stress causes an increased channel off-state leakage due to hot-electron-induced punch-through.

A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits.

High-performance integrated tin monoxide bottom-gate staggered p-channel thin-film transistors (TFTs) are realized and reported. The active layer has been formed by thermal vacuum evaporation and rapid thermal annealing under a continuous nitrogen flow, resulting in field-effect mobilities up to 1.6 cm2/( $\textsf {V}\cdot \textsf {s}$ ) and contact resistances of around $148~\Omega \cdot \textsf {cm}$ . The integration of these TFTs in elementary building blocks for digital circuit applications such as inverters and ring-oscillators is demonstrated, resulting in stage delays down to 300 ns. Furthermore, a unipolar p-type-only 8-bit radio frequency identification code generator is realized, achieving 12.2 kb/s and comprising 294 tin monoxide TFTs.