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In this paper, a dc/dc converter is presented that can boost very low voltages to the typical supply voltages of current integrated circuits (1.2 V--1.5 V). The converter is based on a new hybrid inductive and capacitive architecture and it is suitable for power harvesting applications too. The measured prototype can supply 1.2 V by converting an input voltage of 200 mV delivered by a thermopile exposed to a 5[degrees]C thermal gradient. A chip was designed and fabricated using a United Microelectronics Corp. (UMC) 180-nm low-threshold CMOS process. Measurements on the chip confirm the validity of the design. Index Terms--Charge transfer, CMOS analog integrated circuits, DC-DC power conversion, energy management, energy resources, energy storage.

A novel automatic-gain-control (AGC) architecture utilizing wideband current feedback is proposed for the baseband circuit of a wireless endoscope capsule. The baseband circuit consists of a fast-settling wideband AGC loop and an amplitude-shift-keying demodulator. Additional integrators in the reverse signal path provide negative feedback, bandpass-filtering effect, attenuating low-frequency noises, and dc offset from the radio-frequency front end. The baseband circuit fabricated in a 180-nm complementary metal-oxide-semiconductor process achieves a wide-intermediate-frequency (IF) cartier frequency in the range of 0.5-40 MHz, a measured settling time of 2 [micro]s, and an input sensitivity of -57 dBm. The entire baseband demodulator dissipates only 5 mA, with a 1.8-V supply at a data rate of 1.37 Mb/s and an IF carrier frequency of 10 MHz. Index Terms--Amplitude-shift keying (ASK), analog integrated circuits, automatic gain control (AGC), baseband circuitry, complementary metal-oxide-semiconductor (CMOS).

This brief presents two novel architectures, i.e., a nonlinear neural activation function and its derivative. Both are suitable for implementations of neurons in multilayer perceptron networks with an on-chip backpropagation learning algorithm. The activation function proposed shows minimal area and power consumption, can be considered as an approximation to the tanh(nx) function, and can be programmed to achieve any slope at the origin that is equal to or greater than 2. The derivative proposed also shows minimal area and maximizes its similarity, with the ideal derivative in the proximities of the origin being the best approximation for its degree of complexity. Both topologies are designed with subthreshold metal-oxide--semiconductor transistors in order to minimize power consumption. Likewise, they have been designed with balanced and fully differential topologies, so that external influences, offset, and distortion of even order are reduced. Moreover, a detailed analysis using the General Translinear Principle shows that the activation function is being affected by the body effect but the derivative function is immune to it. The activation function and the proposed derivative are thoroughly analyzed, and measured results are presented for our implementation on 0.5-[micro]m AMI Semiconductor (AMIS) CMOS technology. Index Terms--Activation function, backpropagation (BP), derivative, General Translinear Principle (GTP), low voltage and low power, metal-oxide--semiconductor (MOS) analog integrated circuits, multilayer perceptron (MLP), subthreshold.

Design and analysis of ultrahigh-frequency (UHF) micropower rectifiers based on a diode-connected dynamic threshold MOSFET (DTMOST) is discussed. An analytical design model for DTMOST rectifiers is derived based on curve-fitted diode equation parameters. Several DTMOST six-stage charge-pump rectifiers were designed and fabricated using a CMOS 0.18-[micro]m process with deep n-well isolation. Measured results verified the design model with average accuracy of 10.85% for an input power level between -4 and 0 dBm. At the same time, three other rectifiers based on various types of transistors were fabricated on the same chip. The measured results are compared with a Schottky diode solution. Index Terms--CMOS analog circuits, integrated circuit modeling, rectifiers, ultrahigh-frequency (UHF) integrated circuits.

This brief presents a baseband automatic gain control (AGC) circuit for an IEEE 802.11a wireless local area network (WLAN) direct conversion receiver. The whole receiver is to be fully integrated in a low-cost 0.25-[micro]m 75-GHz SiGe bipolar complementary metal--oxide--semiconductor (BiCMOS) process; thus, the AGC has been implemented in this technology by employing newly designed cells, such as a linear variable gain amplifier (VGA) and a fast-settling peak detector. Due to the stringent settling-time constraints of this system, a feedforward gain control architecture is proposed to achieve fast convergence. The proposed AGC is composed of two coarse-gain stages and a fine-gain stage, with a feedforward control loop for each stage. It converges with a gain error of below [+ or -]1 dB in less than 3.2 [micro]s, whereas the power and area consumption are 13.75 mW and 0.225 [mm.sup.2], respectively. Index Terms--Bipolar complementary metal--oxide--semiconductor (BiCMOS) integrated circuits, feedforward systems, gain control, peak detector, variable gain amplifier (VGA), wireless local-area network (WLAN).

This paper describes self-biased unity-gain buffers that use cascaded, complementary source followers with feed forward and feedback to reduce input-output offset and gain error. Single-ended and differential buffers have been designed, fabricated and tested. Index Terms--Analog circuits, analog integrated circuits, buffer circuits, CMOS analog integrated circuits.

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor [alpha] [less than or equal to] 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of [alpha] on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of [alpha] ([alpha] = 0, 0.5, and 1) in a 0.5 [micro]m CMOS technology with [+ or -] 1.65-V supply voltage. Experimental results show (for [alpha] = 1) a THD of -57 dB (HD2 = -70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 [micro]A/V and a power consumption of 3.2 mW. Index Terms--Analog CMOS circuits, linear resistors, low-power and low-voltage CMOS circuits, operational transconductance amplifier (OTA), quasi-floating-gate (QFG) transistors.

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significantly common mode voltage variations at the input terminals of the differential pair. The implementation of single ended two stage class AB operational amplifiers based on this scheme is discussed. Experimental results of a test chip in 0.5 [micro]m CMOS technology that validates the proposed scheme are presented. Index Terms--Analog integrated circuits, operational amplifiers, low voltage, common mode rejection ratio (CMRR).

Several design options are nowadays available for the frequency compensation of CMOS two-stage transconductance q operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the frequency performance achievable that allow to consciously choose the best approach to meet the prescribed specifications efficiently. In this paper, a comparison among the possible Miller approaches is carried out by exploiting an analytical figure of merit that expresses a tradeoff between gain--bandwidth product, load capacitance, and total transconductance for a given value of phase margin. Interesting and useful results, even unexpected, are found. The accuracy of the comparison is also validated through simulations. Index Terms--Analog integrated circuits, frequency compensation, feedback amplifier, CMOS, multistage amplifier.

In this paper, an active guarding circuit is presented for wideband substrate noise suppression. A feed-forward compensation mechanism is proposed to extend the noise suppression bandwidth and to adjust the amplitude of phase-inversed noise cancellation current by introducing a zero and an amplitude controller. A noise decoupling mechanism is developed to provide a decoupling path and to sense the noise level for generating noise cancellation current. With substrate characterization, parameters of substrate network impedance, decoupling factor, and amplitude of noise cancellation current can be either obtained or determined. The active guarding circuit is implemented in a 90-nm CMOS process based on substrate characterization. The measured substrate noise suppression is better than -9 dB from dc to 250 MHz. The -3-dB suppression bandwidth is effectively extended to 1.2 GHz. The power consumption and circuit area are 2.5 mW and 20 [micro]m x 41 [micro]m, respectively. Index Terms--Analog circuits, CMOS integrated circuits (ICs), substrate coupling noise, substrate crosstalk, substrate isolation.

A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 [micro]m SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a de calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA, 68 dBm IIP2, -3.7 dBm IIP3, and 2.9 dB NF for PCS: and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS. Index Terms--BiCMOS analog integrated circuits, filter, harmonic analysis, intermodulation distortion, low-noise amplifier, mixers, receivers.

This paper proposes a modification for the symbolic synthesis method of analog circuits using admittance matrix expansion. The modification involves a generalization of the synthesis approach to employ mirror elements (voltage mirrors and current mirrors) in the admittance matrix expansion and ideal description of active elements, rather than using only nullor elements (nullators and norators). Accordingly, more alternative ideal representations, based on nullor-mirror elements, can be realized and a wide range of active elements can be used in the circuit synthesis. Systematic synthesis of the CCII-based generalized impedance converters (GICs) is presented as an application example to illustrate the potential of this generalized approach. Multiple equivalent nullor-mirror realizations for the GIC could be extracted easily, by virtue of using mirror elements in the admittance matrix expansion. Consequently, numerous circuit realizations, spanning various combinations of CCII types, have been generated in a simple and direct way. Index Terms--Active-RC circuits, active circuit synthesis, admittance matrix, nullor, pathological element.

We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-[micro]m CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600 x and to accurately programa desired offset with maximum observed residual offset of 469 [micro]V and standard deviation of 199 [micro]V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from--1 to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW. Index Terms--Adaptive systems, analog-digital conversion, analog memories, calibration, CMOS analog integrated circuits (ICs), comparators, floating gate, high-speed ICs, hot carriers, offset cancellation.

A novel analog integrated circuit implementation of an adaptive fuzzy logic controller (AFLC), called variable universe fuzzy logic controller (VFLC), is presented which has not been reported before. The VFLC is a stable controller which has fewer on-line adapting parameters than the conventional AFLCs based on adapting fuzzy rules, thus it is more suitable for hardware implementation. The input and output universes of discourse of the VFLC are adaptively changed according to the input variables to improve the control effect. A novel peaky-triangle membership function is presented to realize the complex input universe variation. The absolute value of the integral of the input variables is used for the output universe variation, and then it is multiplied with the output of the conventional fuzzy logic controller to form the final output. The other parts are minimization circuits and a center of gravity defuzzification circuit that does not use a division circuit. An analog VFLC with 2 inputs, 1 output, and 9 rules is designed and fabricated using a 0.6-[micro]m CMOS standard technology. It can work either in a non-adaptive or an adaptive mode. The measurements show that it completes the VFLC functions. Index Terms--Adaptive control, analog circuits, fuzzy control.

A new sample-and-hold (S&H) architecture is proposed for time-interleaved analog-to-digital converter (ADC). The use of this S&H circuit in front-end of a time-interleaved ADC system eliminates the need for sample-time calibration. Using the techniques of precharging and output capacitor coupling along with a new sampling technique called middle-plate-sampling can mitigate the stringent performance requirements for the opamp and sampling switches, resulting in low power consumption and allowing very high sampling rate. Simulated by HSPICE with a standard BSIM3v3 0.18 [micro]m technology, the S&H achieves 10-12 bits resolution for a 1.6-[V.sub.pp] output at 1-GHz sampling rate. The S&H dissipates 12 mW from a 1.8-V supply. Index Terms--Analog integrated circuits, analog-to-digital circuits (ADCs), CMOS analog integrated circuits, low power analog circuits, pipeline, sample-and-hold (S&H) circuits.

The paper presents the derivation of Miller formulas for weakly nonlinear feedback networks. The expressions found are simple and compact and constitute a generalization of the well-known linear case. As an application example, the formulas are applied to a common-emitter amplifier to straightforwardly derive the closed-form expressions of second- and third-harmonic distortion factors. The results found, validated by Spectre simulations with a VBIC bipolar model, allow to understand in depth the contribution of each nonlinear element. Index Terms--Amplifiers, analog circuits, harmonic distortion, Miller theorem, nonlinear network analysis.

A new neural network for convex quadratic optimization is presented in this brief. The proposed network can handle both equality and inequality constraints, as well as bound constraints on the optimization variables. It is based on the Lagrangian approach, but exploits a partial dual method in order to keep the number of variables at minimum. The dynamic evolution is globally convergent and the steady-state solutions satisfy the necessary and sufficient conditions of optimality. The circuit implementation is simpler with respect to existing solutions for the same class of problems. The validity of the proposed approach is verified through some simulation examples. Index Terms--Analog circuits, Lagrangian networks, mathematical programming, quadratic optimization, recurrent neural networks.

A flexible chaotic ultra-wideband (UWB) communication system with an adjustable channel spectrum is proposed. Since the chaotic UWB bandwidth (BW) is independent of the data rate, the system band plan can be flexibly organized for various communication environments. The proposed system can overcome the spectral inefficiency and RF power wastage that is typically observed in conventional methods by utilizing adjustable channel allocations. A novel chaotic signal generator is designed with an adjustable frequency range of 3.5-4.5 GHz and BW of 70-620 MHz. The chaotic UWB transceiver system is implemented in CMOS 0.18- [micro]m technology, and it features tunable chaotic signal generation and adaptive detection. The system performance is evaluated for digital data transmission rates of up to 15 Mb/s. Index Terms--Chaos, CMOS analog integrated circuits (ICs), communication systems, noise generators, radio communication, signal generators.

The ever-shrinking CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. However, the trend to greater integration and systems-on-chips (SoCs), requires that digital and analog blocks be merged into single chips. High resolution digital-analog converters (DACs) are especially sensitive to the final matching of components and their nominal accuracy is typically enhanced with additional calibration circuitry or laser trimming. Additional calibration circuits increase cost significantly and mainstream laser trimming technique is applied on thin film resistive layers that are not available with most standard fabrication processes used for SoC. In this paper, we present a high-resolution DAC taking advantage of a new laser trimming technique which is compatible with standard CMOS processes, and that can be integrated in SoCs. While initial mismatch prevents reaching the targeted 14-bit resolution, the included tuning elements offer the necessary calibration to exceed the matching requirements and obtain the desired DAC linearity. The architecture of the DAC itself is a classic current-mode segmented resistor ladder: an inverted R2R ladder generating the binary weighted least significant bit currents is combined with unary current sources for the thermometer encoded most significant bits. The entire structure is precisely calibrated to obtain the final desired linearity. The effectiveness of the trimming technology and its application to high-accuracy DACs is demonstrated. Index Terms--Analog integrated circuits, calibration, CMOS, data converter, digital-analog conversion (DAC), laser trimming, linearity, R2R ladder.

An analog RF microelectromechanical systems (MEMS) slotline true-time-delay (TTD) phase shifter is presented for use in conjunction with tapered slot antennas, such as the Vivaldi aerial and the double exponentially tapered slot antenna. The design is a scalable distributed loaded-line cascade of 62 novel differential slow-wave unit cells. Each differential slow-wave unit cell comprises an electrically short slotline section, which is loaded with a shunt impedance consisting of two center-pulled contactless fixed-fixed beam RF MEMS varactors in series, sharing a common electrode. The analog RF MEMS slotline TTD phase shifter is demonstrated on a borosilicate glass wafer using a microfabrication process requiring six masks. It is designed for transistor-transistor logic bias voltage levels and exhibits a measured phase shift of 28.2[degrees]/dB (7.8 ps/dB) and 59.2[degrees]/cm at 10 GHz, maintaining a 75-[OMEGA] differential impedance match [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. The input third-order intercept point is 5 dBm at 10 GHz for a [DELTA]f of 50 kHz, measured in a 100-[OMEGA] differential transmission line system. Design and fabrication opportunities, concerning distortion and loss reduction, as well as packaging, are highlighted. Index Terms--Electronically scanned array, phase shifter, RF microelectromechanical systems (MEMS), slotline, true time delay (TTD).

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18-[micro]m SiGe BiCMOS technology for Q-band (30-50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an [IIP.sub.3] of -13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8-44 GHz. The rms gain and phase errors are [less than or equal to] 1.2 dB and [less than or equal to] 8.7[degrees] for all 4-bit phase states at 30-50 GHz. The beamformer also results in [less than or equal to] 0.4 dB of rms gain mismatch and [less than or equal to] 2[degrees] of rms phase mismatch between the four channels. The channel-to-channel isolation is better than -35 dB at 30-50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is 1.4 x 1.7 [mm.sup.2] including all pads and CMOS control electronics. Index Terms--BiCMOS analog integrated circuit, millimeter wave, multiple input/multiple output (MIMO), phased array, phase shifter, radar, SiGe BiCMOS, smart antenna, Wilkinson coupler, wireless communication.

A new digitally programmable universal current-mode biquad filter is proposed. The filter is based on digitally controlled current followers (DCCFs). It utilizes gains of the DCCFs to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. All parameters of the proposed filter can be adjusted independently. Experimental results obtained from a 0.35-[micro]m standard CMOS chip are provided. Index Terms--CMOS analog integrated circuits, current-mode (CM) filters.

A dual-frequency oscillator employing a fourth-order tank is shown to have the ability to generate simultaneous oscillations at two frequencies. A nonlinear analysis to determine the steady-state and transient behavior of this oscillator is presented. Further, the phase-noise expression for the dual-frequency oscillator is derived and compared with that of a single-frequency oscillator. A dual-loop phase-locked loop (PLL) is designed to lock the frequencies of the dual-frequency oscillator to two external references independently. A prototype of a dual-frequency voltage-controlled oscillator (VCO) along with the dual-loop PLL is implemented in a BiCMOS SiGe technology. The dual-frequency VCO oscillates simultaneously at 2.33 and 4.98 GHz with 12.5% and 10.3 % tuning ranges, respectively. The PLL has locking ranges of 4.2% and 3.6% for 2.33 and 4.98 GHz, respectively. Potential applications of concurrent multifrequency oscillators in muitifunctional communication systems and multiband beam forming are discussed. Index Terms--Analog integrated circuits, nonlinear systems, oscillators, phase noise.

The development of large-scale field-programmable analog arrays (FPAAs) provides an excellent opportunity for expanding the capabilities of analog design courses and their laboratories. These devices allow the complete design and test cycle of an analog IC to be explored within the span of a single-term course without being limited to prefabricated integrated circuits. A brief discussion of the authors' experience in incorporating the recon-figurable analog signal processor (RASP) into courses and workshops is presented. Index Terms--Analog design, analog test, field-programmable analog array (FPAA), laboratory, reconfigurable analog.

This paper presents an analytical modeling of the mechanisms of total harmonic distortion (THD) of second-order based single-feedback and double-feedback Class-D amplifiers (CDAs). We show that the overall THD in these closed-loop CDAs comprises the THD of their open-loop counterparts reduced by the Loop Gain+1 and the THD due to the combined phase and duty cycle error that is due to feedback, hence unique to closed-loop CDAs. We show that the latter THD can be large and is the dominant THD at high input frequencies (> 3 kHz), and that the mechanisms therein are the phase and duty cycle errors. By means of double Fourier series analysis, analytical expressions for the harmonic components and thereafter a THD expression for closed-loop CDAs are derived. The derived expressions depict the parameters that affect THD, and are insightful to designers to optimize/vary pertinent parameters to reduce THD. The derived THD expression is verified against HSPICE and on the basis of measurements on a prototype CDA IC and other CDAs realized discretely. Index Terms--Class-D amplifier (CDA), duty cycle error, phase error, total harmonic distortion (THD).

A method for the nonlinear analysis of voltage-controlled oscillators (VCOs) is presented, accounting for the nonlinear effect of both the varactors and the active devices. A nonlinear perturbation model of VCOs is presented, as well as a method for finding their steady-state oscillation, overcoming the limitation of previous analyses which rely on the solution of the tank balance equation only. Simple formulas for predicting the oscillation and its frequency correction due to the effect of nonlinearities are presented, allowing us to accurately predict the tuning curve of VCOs as well as the amplitude to phase-noise conversion due to the varactors. Their accuracy was validated by circuit simulations. Index Terms--AM-to-FM conversion, analog integrated circuits, nonlinear analysis, oscillators, phase noise, tuning curve, varactor, voltage-controlled oscillators (VCO).