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In many kernels of multimedia applications, the working set is predictable, making it possible to schedule the data transfers before the computation. Many other kernels, however, process data that is known just before it is needed or have working sets that do not fit in the scratchpad memory. Furthermore, multimedia kernels often access two or higher dimensional data structures and conventional software caches have difficulties to exploit the data locality exhibited by these kernels. For such kernels, the authors present a Multidimensional Software Cache (MDSC), which stores 1- 4 dimensional blocks to mimic in cache the organization of the data structure. Furthermore, it indexes the cache using the matrix indices rather than linear memory addresses. MDSC also makes use of the lower overhead of Direct Memory Access (DMA) list transfers and allows exploiting known data access patterns to reduce the number of accesses to the cache. The MDSC is evaluated using GLCM, providing an 8% performance improvement compared to the IBM software cache. For MC, several optimizations are presented that reduce the number of accesses to the MDSC.

If higher performance is required, a parallel application developer might have to extract more parallelism than initially employed in the application. To illustrate this step, this chapter presents a parallel implementation of H.264 decoding on a shared-memory system that scales to a large number of cores. The application implements the dynamic 3D-Wave algorithm, which exploits intra-frame MB-level parallelism as well as inter-frame MB-level parallelism. The 3D-Wave algorithm is based on the observation that inter-frame dependencies have a limited spatial range, i.e., that motion vectors are typically short. Experimental results obtained using a simulator of a many-core architecture containing NXP TriMedia TM3270 embedded processors show that the implementation scales very well, achieving a speedup of more than 50 on a 64-core processor for a 25-frame FHD sequence.

In the previous chapter we have reviewed the H.264/AVC standard and showed that H.264 decoding is a complex application with many options, different kernels, and dependencies between different parts. In this chapter we focus on the next step: finding or discovering the parallelism in the application. We qualitatively compare different approaches to parallelize H.264 decoding and analyze the two most promising approaches in more detail using high-level simulation. How to actually implement the algorithms and how to map the parallelism onto multi/many-core architectures will be presented in later chapters.

It previous chapters we have presented efficient and scalable parallelization strategies for different parts (stages) of H.264/AVC decoding. To obtain a fast and scalable parallel decoder, however, all stages need to be parallelized. In this chapter we will take the final step in our parallel application design process by putting together everything we learnt in the previous chapters in order to realize a highly efficient and scalable parallel application. Specifically, in this chapter we combine pipelining parallelism with data-level in the form of macroblock-level parallelism to obtain a fully parallel H.264 decoder that is optimized for core counts of future multicore systems and emerging video decoding scenarios. The presented implementation is evaluated on a 40-core cc-NUMA system using 1080p25 and 2160p50 video sequences.

In the previous chapter we have analyzed various parallelization approaches for H.264 decoding and concluded that in order to scale to a large number of cores, macroblock-level parallelism needs to be exploited. The next question is how to efficiently exploit this parallelism. In other words, how to map this parallelism onto a multi-/many-core architecture. To answer this question, in this chapter we present two implementations of the 2D-Wave approach. The first implementation maintains a centralized pool of macroblocks that are ready to be decoded and cores retrieve tasks from this Task Pool. In the second approach, called Ring-Line, full lines of macroblocks are statically assigned to cores and the cores synchronize and communicate point-to-point. Both approaches have been implemented and are evaluated on a dual-chip Cell BE system with 18 cores in total.

In the previous chapters we mainly focused on generally the most timeconsuming phase of H.264/AVC decoding, the macroblock reconstruction phase. There is another phase, however, the entropy decoding phase, that takes a significant amount of time. Therefore, Amdahl’s law teaches us that this phase also needs to be parallelized and in this chapter we show how this can be done. In order to be able to do so, however, dependencies that result from reusing sequential legacy code need to be eliminated. Experimental results gathered on a shared-memory multicore/multiprocessor system show that the presented parallel entropy-decoder scales well, but also that the obtained speedup depends in the time taken by the entropy decoding phase, due to the memory bandwidth bottleneck.

Before any attempt to parallelize an application can be made, it is necessary to understand the application. Therefore, in this chapter we present a brief overview of the state-of-the-art H.264/AVC video coding standard. The H.264/AVC standard is based on the same hybrid structure as previous standards, but contains several new coding tools that increase the coding efficiency and quality. These new features increase the computational complexity of video encoding as well as decoding, however. Therefore, parallelism is a solution to obtain the performance required for real-time processing. The goal of this chapter is not to provide a detailed overview of H.264/AVC, but to provide sufficient background to be able to understand the remaining chapters.

In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas of the Network-on-Chip based Multi-Processor System-on-Chip. The EDI replicates the NoC topology with an EDI node instantiated for each underlying NoC data module. Contention in the EDI node is handled by replicating the EDI in layers. The EDI generation is automatic, and uses as input the cross-triggering patterns that are not required to follow the communication patterns in the NoC. The generation and routing tool is also presented in this paper. The EDI is evaluated with four different implementations varying complexity and handling of contention. The area of a single EDI Layer is around 0.9% of the area occupied by the tested NoCs, using the lower area implementation. These results show that the proposed implementation of the EDI incurs low cost on the overall system.

This article presents an architecture for a motion vectors predictor using H.264/AVC standard Main profile. The motion vectors predictor is one of the most important modules of motion compensation. This architecture was developed to work at 100 MHz, providing a processing rate capable of decoding HDTV in real time. The hardware is composed by a bank of registers and a state machine operating over the registered data. The design was synthesized for FPGA Xilinx Virtex II-PRO and ASIC TSMC 0,18µm technology reaching maximum frequency of operation of 133 MHz and 129 MHz, respectively.

This paper investigates the scalability of MacroBlock(MB) level parallelization of the H.264 decoder for High Definition (HD) applications. The study includes three parts. First, a formal model for predicting the maximum performance that can be obtained taking into account variable processing time of tasks and thread synchronization overhead. Second, an implementation on a real multiprocessor architecture including a comparison of different scheduling strategies and a profiling analysis for identifying the performance bottlenecks. Finally, a trace-driven simulation methodology has been used for identifying the opportunities of acceleration for removing the main bottlenecks. It includes the acceleration potential for the entropy decoding stage and thread synchronization and scheduling. Our study presents a quantitative analysis of the main bottlenecks of the application and estimates the acceleration levels that are required to make the MB-level parallel decoder scalable.

The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is currently being used for a much broader range of applications.In this paper we evaluate if the Cell SPEs could benefit significantly from a scalar processing unit using two methodologies. In the first methodology the scalar processing overhead is eliminated by replacing all scalar data types by the quadword data type. This methodology is feasible only for relatively small kernels. In the second methodology SPE performance is compared to the performance of a similarly configured PPU, which supports scalar operations. Experimental results show that the scalar processing overhead ranges from 19% to 57% for small kernels and from 12% to 39% for large kernels. Solutions to eliminate this overhead are also discussed.

In this paper an analysis of bi-dimensional video altering on the cell broadband engine processor is presented. To evaluate the processor, a highly adaptive altering algorithm was chosen: the deblocking filter of the H.264 video compression standard. The baseline version is a scalar implementation extracted from the FFMPEG H.264 decoder. The scalar version was vectorized using the SIMD instructions of the cell synergistic processing element (SPE) and with AltiVec instructions for the Power Processor Element. Results show that approximately one third of the processing time of the SPE SIMD version is used for transposition and data packing and unpacking. Despite the required SIMD overhead and the high adaptivity of the kernel, the SIMD version of the kernel is 2.6 times faster than the scalar versions.

In this paper we present results of parallelization of Deblocking Filter (DF) of H.264 video codec on decoupled threaded architecture (DTA). We parallelized the code trying to exploit all available thread level parallelism and to make it suitable for DTA architecture. Experimental results show that significant speed up can be achieved and that DTA architecture can efficiently exploit available parallelism. We also show comparison with parallelized version of DF for Cell architecture.

This paper presents the prototyping strategy used to validate the designed modules of a main profile H.264/AVC video decoder designed to achieve 1080p HDTV resolution, implemented in a FPGA. All modules designed were completely described in VHDL and further validated through simulations. The post place-and-route synthesis results indicate that the designed architectures are able to target real time when processing HDTV 1080p frames (1080times1920). The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The prototyping strategy used an embedded Power PC and associated logic and buffering to control the modules under prototyping. A host computer, running the reference software, was used to generate the input stimuli and to compare the results, through a RS-232 serial interface.

This paper presents a motion compensation memory hierarchy for an H.264/AVC decoder with support to bi-predictive frames. The designed memory hierarchy reduces the memory bandwidth through the use of a three-dimensional cache and through the use of extra memory saving techniques. The cache size parameters were determined through the evaluation of simulation results from real video sequences. The designed memory hierarchy provides, in average, a 60% of bandwidth reduction. The architecture was designed in VHDL and synthesized for a Xilinx Virtex-II PRO FPGA

The X4CP32 is an architecture that combines the parallel and reconfigurable paradigms. It consists of a grid of reconfigurable and programming units (RPUs), each one containing 4 cells (including a microprocessor in each cell), responsible for all the processing and program flow. This paper presents architectural modifications in the X4CP32 in order to increase its performance. The RPU was implemented according to the VLIW (very long instruction word) methodology, and the cells were redesigned with a pipelined implementation. These improvements raised the maximum IPC of the RPU from 0.5 to 4 with an area overhead of 26%. To evaluate the new architecture, versions of the 2D discrete cosine transform, Montgomery modular multiplication and color space conversion were mapped, using the baseline architecture and the pipelined VLIW architecture.

This work presents the design, the validation and the prototyping of a motion compensation architecture for a H.264/AVC video decoder. The designed architecture supports the main profile level 4.0 and it targets high resolution applications, like HDTV. This design considers the sample processing of the motion compensation block, which includes quarter-pel interpolation, weighted prediction, average to bi-predictive processing and clipping. The architecture processes luma and chroma samples in parallel, with independent luma and chroma datapaths. The design uses a single interpolator to process bi-predictive macroblocks. The design was synthesized to FPGA and standard cell technologies. The synthesis results had indicated that this architecture reaches 100 MHz in both technologies, allowing real time to decode HDTV videos with 1920times1080 pixels. The prototype was targeted to a Xilinx Virtex-II PRO FPGA

This work present a sample processing architecture to the H.264/AVC, the new video coding standard of the ITU-T and ISO/IEC, main profile motion compensation video decoder. The architecture processes luma and chroma samples in parallel, with one luma and two chroma datapaths. The sample processing is formed by the quarter sample interpolation, weighted prediction, median to bidirectional processing and clipping. The design implemented both in FPGA and VLSI are able to decode HDTV (1080x1920), 30 frames per second, at real-time at 100 and 83.9 MHz clock cycle, respectively.

The X4CP32 is a novel coarse RPU runtime-reconfigurable general purpose microprocessor. It consists of 3 programming levels, based on a hierarchical array of easily and quickly reconfigurable entities. It brings a new concept of runtime reconfiguration and programming, which is its main strength. Although it is effective in heavy arithmetic applications, it is suited for virtually any task an application can demand, presenting as a solid option for a general purpose microprocessor.

The X4CP32 is a parallel/reconfigurable microprocessor with 2 programming levels. Although it is a general-purpose microprocessor, it has the reliable performance of a reconfigurable architecture. We expose its architecture and programming levels, and discuss the powerful interaction between parallel programming and reconfiguration. It shows two performance-optimized implementations of matrix multiplication using both parallel and reconfigurable paradigms and a parallel implementation of miner intelligent agents.

This paper presents the MoCHA (motion compensation hardware architecture) design. MoCHA is an architectural design for bi-predictive motion compensation of the H.264/AVC decoder. The designed architecture features a memory hierarchy to reduce the memory bandwidth and the number of memory access cycles. The architecture uses a single datapath to process bi-predictive reference areas and it processes luma and chroma samples in parallel. The design was mapped to a Xilinx Virtex II Pro FPGA and it is able to run at 100MHz. The throughput is enough to support more than 30 bi-predictive HDTV frames per second.

The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.