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Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/HfxZr1−xO2/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m−2 at Vread = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators. [ABSTRACT FROM AUTHOR]

Ferroelectric HfxZr1–xO2 (HZO) is typically achieved by crystallization of an amorphous thin film via rapid thermal processing (RTP) at time scales of seconds to minutes. For integration on III–V semiconductors, this approach can severely degrade the sensitive HZO/III–V interface. To evaluate whether a reduced thermal budget can improve the interface quality, millisecond duration thermal anneals are utilized using a flash lamp annealer (FLA) on HZO/InAs capacitors. Through thorough electrical characterization such as polarization hysteresis, endurance, and capacitance‐voltage measurements, as well as synchrotron‐based chemical interface characterization, the FLA and RTP treatments are compared and the FLA results are found in lower interface defect density and higher endurance, but also have generally lower remanent polarization (Pr) compared to RTP. Additionally, ways to achieve high Pr and low interface defect density using multiple lower energy flashes, as well as by pre‐crystallization during the ALD growth step are investigated. Using FLA, Pr exceeding 20 µC cm−2 is achieved, with extended endurance properties compared to RTP treatment and a considerably decreased defect density, indicative of a higher quality HZO/InAs interface. This work presents valuable insight into the successful integration of ferroelectric HZO on low thermal budget III–V semiconductors. [ABSTRACT FROM AUTHOR]

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs. [ABSTRACT FROM AUTHOR]

InSb has the smallest bandgap and highest electron mobility among III‐V semiconductors and is widely used for photodetectors and high‐frequency electronic applications. Integration of InSb directly on Si would drastically reduce the fabrication cost and enable new applications, however, it is very challenging due to its 19% lattice mismatch with Si. Herein, the integration of single‐crystalline InSb microstructures on insulator‐covered Si through rapid melt growth (RMG) is reported and specifically provides details on the fabrication process. The importance of achieving high‐quality conformal capping layers at low thermal budget to contain the InSb melt is assessed when the sample is annealed. The importance of ensuring a pristine Si seed area to achieve single‐crystalline InSb is illustrated and demonstrated here for the first time. [ABSTRACT FROM AUTHOR]

Nonvolatile memory devices based on ferroelectric Hf x Zr 1- x O 2 (HZO) show great promise for back-end integrable storage and for neuromorphic accelerators, but their adoption is held back by the inability to scale down the HZO thickness without violating the strict thermal restrictions of the Si CMOS back end of line. In this work, we overcome this challenge and demonstrate the use of nanosecond pulsed laser annealing (NLA) to locally crystallize areas of an ultrathin (3.6 nm) HZO film into the ferroelectric orthorhombic phase. Meanwhile, the heat induced by the pulsed laser is confined to the layers above the Si, allowing for back-end compatible integration. We use a combination of electrical characterization, nanofocused scanning X-ray diffraction (nano-XRD), and synchrotron X-ray photoelectron spectroscopy (SXPS) to gain a comprehensive view of the change in material and interface properties by systematically varying both laser energy and the number of laser pulses on the same sample. We find that NLA can provide remanent polarization up to 2 P r = 11.6 μC/cm 2 in 3.6 nm HZO, albeit with a significant wake-up effect. The improved TiN/HZO interface observed by XPS explains why device endurance goes beyond 10 7 cycles, whereas an identical film processed by rapid thermal processing (RTP) breaks already after 10 6 cycles. All in all, NLA provides a promising approach to scale down the ferroelectric oxide thickness for emerging HZO ferroelectric devices, which is key for their integration in scaled process nodes.

The ferroelectric (FE)-antiferroelectric (AFE) transition in Hf 1- x Zr x O 2 (HZO) is for the first time shown in a metal-ferroelectric-semiconductor (MFS) stack based on the III-V material InAs. As InAs displays excellent electron mobility and a narrow band gap, the integration of ferroelectric thin films for nonvolatile operations is highly relevant for future electronic devices and motivates further research on ferroelectric integration. When increasing the Zr fraction x from 0.5 to 1, the stack permittivity increases as expected, and the transition from FE to AFE-like behavior is observed by polarization and current-voltage characteristics. At x = 0.8 the polarization of the InAs-based stacks shows a larger FE-contribution as a more open hysteresis compared to both literature and reference metal-ferroelectric-metal (MFM) devices. By field-cycling the devices, the switching domains are studied as a function of the cycle number, showing that the difference in FE-AFE contributions for MFM and MFS devices is stable over switching and not an effect of wake-up. The FE contribution of the switching can be accessed by successively lowering the bias voltage in a proposed pulse train. The possibility of enhanced nonvolatility in Zr-rich HZO is relevant for device stacks that would benefit from an increase in permittivity and a lower operating voltage. Additionally, an interfacial layer (IL) is introduced between the HZO film and the InAs substrate. The interfacial quality is investigated as frequency-dependent capacitive dispersion, showing little change for varying ZrO 2 concentrations and with or without included IL. This suggests material processing that is independently limiting the interfacial quality. Improved endurance of the InAs-Hf 1- x Zr x O 2 devices with x = 0.8 was also observed compared to x = 0.5, with further improvement with the additional IL for Zr-rich HZO on InAs., Competing Interests: The authors declare no competing financial interest., (© 2022 The Authors. Published by American Chemical Society.)

Ferroelectric memories based on hafnium oxide are an attractive alternative to conventional memory technologies due to their scalability and energy efficiency. However, there are still many open questions regarding the optimal material stack and processing conditions for reliable device performance. Here, we report on the impact of the sputtering process conditions of the commonly used TiN top electrode on the ferroelectric properties of Hf 1- x Zr x O 2 . By manipulating the deposition pressure and chemistry, we control the preferential orientation of the TiN grains between (111) and (002). We observe that (111) textured TiN is superior to (002) texturing for achieving high remanent polarization ( P r ). Furthermore, we find that additional nitrogen supply during TiN deposition leads to >5× greater endurance, possibly by limiting the scavenging of oxygen from the Hf 1- x Zr x O 2 film. These results help explain the large P r variation reported in the literature for Hf 1- x Zr x O 2 /TiN and highlights the necessity of tuning the top electrode of the ferroelectric stack for successful device implementation.