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CMOS optical sensors devices are becoming increasingly important and popular for many different applications. Some of these devices are fabricated starting from SOI wafers and using semiconductor manufacturing techniques. A common feature of the CMOS sensors is the isolating trench that protects the device from electrical noise. In our particular application, the trench is much deeper than usual, in order to isolate the sensor also from stray light interference. In the present paper we describe the multistep etch process used to create the trench rounding all around the sensor chip. First a silicon oxide HM (Hard Mask) is etched in a CCP (Capacitively Coupled Plasma) chamber with a recess in silicon as shallow as possible to preserve the photo-resist; then an ICP (Inductively Coupled Plasma) reactor is used to etch 23um silicon etch, landing onto a 1um BOX (Buried OXide) layer. Finally the BOX is etched with a dedicated step followed by a second silicon etch to get a deeper isolating trench, both steps performed in the same ICP chamber. The trench layout is lined internally by a closed-loop metal line that is buried in the HM stack. While working on the process development, an unexpected asymmetrical slope of the BOX sidewalls was observed. This has prompted us to focus the attention to the BOX etch and the effect that an applied electromagnetic field and its interaction with the metal line, exert on the etch behaviour. The plasma chamber employed for the BOX and silicon etch is a reactor with a top ICP source and a platen electrode, powered by two independent RF generators, both at 13.56MHz. The peculiarity of this etcher is to have an additional coil – where a high value continuous electrical current flows - used to modulate the plasma shape in the chamber. The initial BOX etch recipe applied had been used successfully in the past for similar scopes. However when it was employed for this specific application, the subsequent XSEM inspection highlighted an asymmetrical shape of the sidewalls, in different locations on the wafer. In particular the sidewall opposite to the metal line always shows an accentuated slope, compared to the other that is straight and vertical. Starting from this observation, we assumed there was an influence of the presence of the metal line during the BOX etch. The hypothesis is that the electromagnetic field generated by the additional coil of the etcher, couples with the metal lines, acting as spires on the wafer, resulting in a local electromagnetic field that has an effect on electron and ion trajectories during the etch. The result of this is the local asymmetry of the sidewalls. To prove this hypothesis, three additional tests have been executed, so to have four distinct conditions: 1) BOX etch with Coil Current ON and metal spires buried in the HM stack; 2) BOX etch with Coil Current OFF and metal spires buried in the HM stack; 3) BOX etch with Coil Current ON and NO metal spires buried in the HM stack; 4) BOX etch with Coil Current OFF and NO metal spires buried in the HM stack. The results of these tests confirm the influence of the electromagnetic field generated by the additional coil, since it gives asymmetric features in both conditions 1) and 3), and not in conditions 2) and 4). At the same time the coupling with the metal spires has an influence too, since it gives a local asymmetry in condition 1) and a wafer level asymmetry in condition 3). Figure 1

We report for the first time, an improvement in post-cycling low resistance state retention of oxide-based resistive RAM devices by injecting copper into the oxygen vacancy conducting filament. Through first principle simulations, we find that copper encounters a larger population of high kinetic diffusion barriers than oxygen vacancies resulting in an improved low resistance state retention.

Patterning on Si with high aspect ratio trenches by spin-coating of photoresist faces significant challenges. The desire to maintain a good thickness uniformity of resist on wafer surface, to minimize any residue inside deep trenches, as well as enabling low cost of ownership has led to new process techniques. Wafer level lamination using dry film resist (DFR) has emerged as a favorable option for such applications. In this paper, a unique application of temporary DFR to overcome deep Si trenches will be presented. The integration scheme offers novel possibilities for wafer singulation in addition to resolving the issues with conventional spin-coating. An example of this approach will be presented in detail. This unique integration flow can lead to new applications that would otherwise not be feasible in technological areas such as sensor, microfluidics and MEMS.

Nonvolatile memory devices based on filamentary resistance switching (RS) areamong the frontrunners to fuel future devices and sensors of the internet of things (IoT) era. The capability of many metal-insulator-metal cells to switch between two distinctive resistive states in response to an external electrical stimulus has been demonstrated. Through years of selection, cells based on the drift of metal ions, namely conductive-bridge memory devices, have shown a wide range of applications with nanosecond switching speeds, nanometer scalability, high-density, and low power-consumption. However, for low (sub-10-μA) current operation, a critical challenge is still represented by programming variability and by the stability of the conductive filament over time. Here, by introducing the concept of reverse filament growth (RFG), we managed to control the structural reconfiguration of the conductive filament inside a memory cell with significant enhancements of each of the aforementioned properties. A first-in-class Cu-based switching device is demonstrated, with a dedicated stack that enabled us to systematically trigger RFG, thus tuning the device’s properties. Along with nanosecond switching speeds, we achieved an endurance of up to 106 cycles with a 102 read window, with outstanding disturb immunity and optimal stability of the filament over time. Furthermore, by tuning the filament’s shape, an excellent control of multi-level bit operations was achieved. Thus, this device offers high flexibility in memory applications.

We thoroughly benchmark the reliability of Cu-based CBRAM stacks with different switching layers against state-of-the-art OxRAM stacks. We optimize the switching conditions for maximizing the endurance lifetime in three CBRAM stacks, outlining the impact of the switching layer on the energy required for the switching operation and on the memory window. We show that CBRAM provide a larger memory window than OxRAM, but the switching energy is systematically higher, and the endurance lifetime is shorter. We also demonstrate that the larger memory window of CBRAM degrades over time and is thus only an apparent advantage with respect to OxRAM. Therefore, this study reveals that OxRAM devices investigated in this work are more suitable candidates than for applications targeting long data retention and low programming voltage.

In this paper, we assess the impact of different W oxidation conditions on the electrical performance of Cu/Al2O3/WOx-based CBRAM devices. While HR-TEM characterization carried out on samples with three different oxidation conditions reveals that WOx is always in the crystalline phase in our oxidation temperature range, higher oxidation temperature leads to denser and thicker oxides. By performing DC and AC electrical characterization, we demonstrate that a careful engineering of the W oxidation conditions enables to boost the performance of these devices. In particular, we prove that a trade-off between density and thickness must be pursued in order to enlarge the memory window and extend the endurance lifetime with short (10 ns) pulses.

In this abstract, we report for the first time the low-current performance enhancement combined with the improvement of the scaling potential in CBRAM devices by adopting an etch-friendly alternative material, Co, as active electrode, based on theoretical considerations and experimental results. Co is proven to yield, with respect to Cu, faster/lower voltage switching and more stable conductive filaments, irrespective of the switching layer, thanks to its higher cohesive energy. By further optimizing the switching layer, we show that the introduction of Co as active electrode is a breakthrough for boosting CBRAM performances, enabling fast and low-power switching, long endurance lifetime and optimal data retention.

We analyze the switching and retention properties of 65-nm integrated Cu(-Ge-Te)/(Ta)/GeSe conductive bridge random access memory devices operated at $50~\mu \text{A}$ . We evidence the crucial role played by a Ta buffer layer inserted between the Cu alloy and GeSe layers in decreasing the preforming current and in significantly improving the low-resistance state retention. Cu alloys of different compositions are tested to reveal lower device variability and longer retention with Cu2GeTe3 active electrode.

In this paper we engineer a TiN⧹⧹Al2O3⧹⧹(Hf,Al)O2⧹⧹Ta2O5⧹⧹Hf Oxide Resistive Random Access Memory (OxRRAM) device for fast switching at low operation current without sacrificing the retention and endurance properties. The integrated 40 nm × 40 nm cell switches at 10 μA using write pulses shorter than 100 ns (resp. 1 μs) for Reset (resp. Set) and with amplitude

In this paper we outline the effects on the memory window of the programming method and pulse width and of the temperature, in Cu/Al2O3-based CBRAM targeting a 10-μA current regime. Despite its large median value, the overall HRS/LRS ratio in these devices can be drastically reduced due to the LRS and HRS dispersion and to the instability of the resistive states over time, especially in a low-current regime. For this reason, in this study we adopt a statistical approach, focusing on the tails of the cumulative distribution Function (CDF). We compare different verify-based algorithms to force an initial tail-to-tail (1st percentile of CDF) resistive window, demonstrating that, in order to reduce the total programming time, a complete Write/Erase cycle must be performed at each verify attempt. We also prove that the stability of the programmed LRS/HRS states is strongly influenced by the external temperature and that it is affected by the programming pulse width (PW) used in the algorithm, likely driving the diffusion processes that originate the state degradation. Selecting the appropriate PW, no overlap of the LRS and HRS distributions is observed after 1 week at room temperature.

In this letter, we propose a novel single-cell, cycle-to-cycle based retention testing method, enabling fast statistical retention assessment on oxide-based resistive random access memory (RRAM). Detailed comparison between cycle-to-cycle and device-to-device retention testing methods is made on TiN\HfO2\Hf stack showing excellent agreement in terms of failure rate and extracted activation energy. Due to the unique properties of filamentary RRAM, this new retention testing method allows fast and cost effective retention benchmarking of different material stacks and is particularly versed in the study of the impact of programming algorithms.

This study is focused on Conductive Bridging Random Access Memory (CBRAM) devices based on chalcogenide electrolyte and Cu-supply materials, and aims at identifying the key material parameters controlling memory properties. The CBRAM devices investigated are integrated on CMOS select transistors, and are constituted by either Ge-Se or Ge-Te electrolyte layers of various compositions combined with a Cu2GeTe3 active chalcogenide electrode. By means of extensive physical and electrical characterization, we show for a given electrolyte system that slower write is obtained for a denser electrolyte layer, which is directly correlated with a lower atomic percentage of the chalcogen element in the layer. We also evidence that the use of Ge-Se electrolyte results in larger write energy (voltage and time), however with improved state retention properties than for Ge-Te electrolyte materials. We associate these results with the stronger chemical bonding of Cu with Se, resulting both in a stabilized Cu filament and a slower Cu cation motion. More robust processing thermal stability is also observed for Ge-Se compared to Ge-Te compounds, allowing more flexibility in the integration flow design. ispartof: FARADAY DISCUSSIONS vol:213 issue:0 pages:67-85 ispartof: location:England status: published

In this paper we demonstrate a unipolar selector based on Cu-based active layer. Volatile conductive bridge concept is explained by the means of electrical results and material properties such as device area, Cu-based active layer -thickness and composition. Beside the standard stack, the integration of a thin interfacial layer of 1nm metal oxide allows to improve VCB nonlinearity up to 6 decades, by decreasing initial current leakage to 1nA and switching V to 2.5V/1μs. Good endurance behavior is shown with more than 1E5 cycles obtained without degradation. Good switching temperature stability is demonstrated up to 125oC for both standard and HfO2/Cu-based stacks.

Chalcogenides are interesting as CBRAM electrolytes due to large memory window ranging over 3 orders of magnitude. However, switching time and LRS retention are reliability concerns in these electrolytes. To identify pathways to improve reliability, we evaluate CBRAM devices with different compositions of two chalcogenide electrolytes (Ge-Te and Ge-Se) and investigate the role of chalcogen element and its proportion on the switching and retention characteristics. We find that Ge-Se requires longer SET times and shows better retention than Ge-Te. We also observe an anticorrelation between SET time and the proportion of chalcogen element in these electrolyte systems. Plausible mechanisms which may contribute to these results are also investigated.

© 2015 Elsevier B.V. All rights reserved. The impact of different Ru precursors and/or deposition methods on the electrical characteristics of Ru/SrTiOx/Ru capacitors has been investigated. The observed increase of the leakage current density (Jg) and the equivalent oxide thickness (EOT) for ALD (atomic layer deposition) deposited Ru layers compared to PVD (physical vapor deposition) deposited ones was found to be caused by a SrRuTiOx layer formation at the SrTiOx/Ru interface aided by the presence of the oxygen co-reactant used during the ALD, regardless of the precursor used. publisher: Elsevier articletitle: Understanding the EOT–Jg degradation in Ru/SrTiOx/Ru metal–insulator–metal capacitors formed with Ru atomic layer deposition journaltitle: Microelectronic Engineering articlelink: http://dx.doi.org/10.1016/j.mee.2015.04.076 content_type: article copyright: Copyright © 2015 Elsevier B.V. All rights reserved. ispartof: Microelectronic Engineering vol:147 pages:108-112 ispartof: location:ITALY, Udine status: published

Display Omitted Metal-Insulator-Metal capacitors with strontium titanate and ruthenium electrodes.EOT=0.38nm @ 0V and current density 10-7Acm-2 @ ?1V and 25?C.J-V and C-V behavior modeled with defects and multi-phonon trap-assisted-tunneling.Relaxation measurement indicate charge loss of 6.5% @ 1s and 25?C. The electrical properties of Ru/SrTiOx/Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38nm at 0V and current density of 10-7Acm-2 at ?1V and 25?C meet the sub-20nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior.

In this work, we prove that, for a current regime of 10 μA and using industry-relevant programming pulse-width, Cu/Al2O3-based conductive-bridging RAM (CBRAM) cells ensure reliably larger memory window (MW) than state-of-the-art oxygen-vacancy-based RRAM (OxRRAM) cells. Due to the intrinsically stochastic nature of the switching mechanism, the Ron and Roff values can be widely distributed, especially in a low-current regime, drastically reducing the overall memory window. For this reason, in this study we adopt a statistical approach, focusing on the tails of the distributions. Using a program-verify method we show that the larger median MW in CBRAM allows to program a MW ≥×10 using ×10 shorter programming time with respect to OxRRAM. Moreover, we show that, in order to ensure a MW >×10 after a fixed retention time, the programming time needs to be several decades larger for OxRRAM than for CBRAM.

In this paper, we introduce rare-earth hygroscopic oxide Gd2O3 as a novel switching material allowing extended reset operation as compared to standard state-of-the-art oxide like (Hf,Al)O2. We prepared 5 nm-thick oxide layers, as integrated between TiN and Hf electrodes in 1-transistor/1-resistor configuration. Using industry-relevant programming current I ≤ 10 µA and pulse width ≤1 µs, 40 nm-size TiN\Gd2O3\Hf cells allowed reaching a median memory window (MW) > × 70 while state-of-the-art materials exhibited MW 106 cycles), and good retention of Gd2O3-based cells (>5 days at 85 °C), verify algorithms allow reliable programming with low latency.

We report on novel integrated Se-based Ovonic Threshold Switching selector devices, with sizes down to 50nm, which can be operated reliably at high drive current densities, exceeding 20MA/cm2, and have high half-bias nonlinearity exceeding well 103. We show functional devices after a thermal budget of 350°C. Their electrical properties are tunable by careful control of the GexSe1−x films composition, thickness or process condition.

In this letter, we experimentally investigate data retention in a copper (Cu)-based conductive bridge random-access memory device at a low current regime (10 $\mu \text{A}$ ) in which retention is governed by factors other than just the conductive filament. Our findings show that the retention characteristics are determined by the local chemical potential of Cu between the conductive filament and its surrounding medium. Furthermore, the retention tendencies are described by the electrochemical reaction in accordance with the potential difference of Cu ions. Therefore, an appropriate quantity of Cu ions around the filament is important for achieving thermally reliable high and low resistance states over time.

In this letter, we compare the switching performances of Cu-based CBRAM cells having either Al2O3 or SiO2 dielectric layer. Both electrical and physical characterizations revealed different Cu mobility in the two dielectrics, impacting forming/switching speed and variability as well as functionality at low current. The modeling of the conduction also indicated different filament shapes in the two dielectrics. Based on the results, dielectrics allowing high Cu mobility are required when filament temperature is low, i.e., for low-current application ( $ ), while dielectrics allowing moderate Cu mobility are more appropriate for higher current ranges ( $\ge 10~\mu \text{A}$ ), whereby Cu mobility is highly assisted by temperature.

Reducing the equivalent oxide thickness below 0.45 nm at low leakage current density of 10-7A/cm2 at ± 1V is required for DRAM MIM capacitors for the 2X node. This can be achieved using a bi-layer stack TiO2/Sr rich STO (62%), which is converted into a STO layer having 54% Sr content after crystallization anneal. The impact of TiO2 content in the initial bi-layer on the grain morphology and electrical properties of the final stack was studied. An optimal TiO2 thickness range was identified, correlated with the grain size. Ti richer STO results in a larger amount of nano-cracks and higher leakage current. The electrode/STO interface is critical in reducing the leakage current. In this regard, Ru has shown improved properties as compared to TiN. Moreover, Sr diffusion into Ru identified by SIMS measurements seems to have a beneficial effect on improving the interface and electrical properties.

Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400^oC range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. TSV aspect ratios can vary as function of the integration scheme, for instance in a via-last or via-middle flow, and thus barrier continuity requires conformality which guarantees the presence of a diffusion barrier until the bottom of the TSV. Target conformality can either be obtained by PVD, typically for TSV A.R.=

The resistive random-access memory (RRAM) device concept is close to enabling the development of a new generation of non-volatile memories, provided that their reliability issues are properly understood. The design of a RRAM operating with extrinsic defects based on metallic inclusions, also called conductive bridge RAM, allows the use of a large spectrum of solid electrolytes. However, when scaled to device dimensions that meet the requirements of the latest technological nodes, the discrete nature of the atomic structure of the materials impacts the device operation. Using density functional theory simulations, we evaluated the migration kinetics of Cu conducting species in amorphous $$\hbox {AlO}_{\mathrm{x}}$$ and $$\hbox {WO}_{\mathrm{x}}$$ solid electrolyte materials, and established that atomic disorder leads to a large variability in terms of defect stability and kinetic barriers. This variability has a significant impact on the filament resistance and its dynamics, as evidenced during the formation step of the resistive filament. Also, the atomic configuration of the formed filament can age/relax to another metastable atomic configuration, and lead to a modulation of the resistivity of the filament. All these observations are qualitatively explained on the basis of the computed statistical distributions of the defect stability and on the kinetic barriers encountered in RRAM materials.

In this paper, we demonstrate that the morphology of the conductive filament is the key parameter to control the data retention characteristics of CBRAM devices. In particular, we prove that the evolution of the LRS and HRS distributions is qualitatively related to the filament shape, whereas it is influenced quantitatively by the materials constituting the CBRAM stack, and we propose the peculiar hourglass filament shape as a solution for enabling optimal retention performances. Further analysis of the effect of cycling on retention confirms the key role of the filament morphology in the CBRAM data retention trend.

We statistically investigate for the first time the impact of programming history on the data-retention properties of tail bits in scaled OxRRAM devices. By using an innovative test method we demonstrate for a same cell that retention is not only affected by programming pulse duration but also by pre-Write pulse-pattern and delay between pulses. This approach, combined with material engineering exercise, allowed to clarify the role of oxide-metal interface and oxygen chemical potential profile along filament in improving data stability. Based on these learnings, a TaOx-based stack is proposed for embedded application, showing great retention with immunity to BEOL thermal stress.

We optimize a novel W\WO 3 \Al 2 O 3 \Cu CBRAM cell allowing excellent control of Hour-Glass (HG) shaped Conductive Filament (CF), improving switching variability, disturb and retention at low current. We evidence for the first time the critical impact of the Cu chemical potential close to the HG constriction on state retention.

We demonstrate an advanced a-VMCO nonfilamentary resistive switching memory cell with self-rectifying, self-compliant, forming-free and analog behavior. A BEOL-compatible process yields devices with excellent device-to-device variability, down to 40nm size. Detailed analysis of the a-Si/TiO 2 interface enables understanding the barrier resistance modulation, engineered for wider on/off window and current reduction, while preserving an excellent variability. Inner-interface engineered devices have an on/off window well above 102 and reset switching currents of down to ∼1uA for 40nm-size cells, scaling with size, without compromising reliability. Furthermore, vertical stack scaling allows to reduce the operating voltages, while preserving or tuning device figures.

This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20 nm wide fins are fabricated using 193 nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300 nm and the electrically active fin height is 40 nm.

In this letter we optimize Ta2O5-based resistive-switching memory cells for improved retention properties. We show that the electrode material used as oxygen-scavenging element directly controls the state stability. As compared to TiN\Ta2O5\Ti cells the conductive filament retention is improved for TiN\Ta2O5\Ta cells due to the lower oxygen affinity of Ta. The oxygen chemical potential profile along the filament is also modulated by the Ta thickness, allowing reaching excellent retention of both low- and high-resistance states for several weeks at 250°C.

Strontium titanate (STO) has been proposed as dielectric material in metal-insulator-metal (MIM) capacitors for future DRAM generations due to its higher dielectric constant and corresponding lower equivalent oxide thickness. In this letter, we show for the first time the impact of electrode composition and processing on the low-frequency noise (LFN), hence on the device material defectiveness, in large area (1000 μm × 1000 μm) MIM capacitors with STO dielectric (EOT is ~0.4nm, physical thickness is ~8.5nm) and Ru/TiN or TiN as metal electrodes. LFN measurements show that the power spectral density (S IG ) associated with gate current (I G ) fluctuations follows a 1/f shape and that SIG αI α G with α measured between 1.6 and 1.9. In particular, it is shown that PVD processing for top electrode Ru in place of chemical vapor deposition processing results in a significant (more than three decades) noise reduction (lower trap density) according to the observed lower gate leakage (

Leakage currents as low as \(10^{\mathrm {\mathbf {-7}}}\) A/cm \(^{\mathrm {\mathbf {2}}}\) at both 1 V and −1 V top electrode bias in the sub-0.4-nm equivalent SiO 2 thickness range are demonstrated in Ru/SrTiO x /Ru metal-insulator–metal capacitors in which the 8.5-nm SrTiO x layer is deposited by atomic layer deposition. The top electrode material and deposition technique as well as the postdeposition anneal are crucial parameters to control the leakage, not only at negative, but also at positive top electrode bias.

The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of interest within that family together with Ω-gates, Π-gates, gate-all-around… They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI option so far. We report in this work an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations. Both alternatives show better scalability (threshold voltage – Vt vs. L) than PLANAR CMOS and exhibit similar intrinsic device performance (Ioff vs. Ion). Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage (VDD) for the two FinFET integration schemes.

In this paper, we optimize a WO3\Al2O3 bilayer serving as the electrolyte of a conductive bridge RAM device using a Cu-based supply layer. By introducing a WO3 layer formed by thermal oxidation of a W plug, the hourglass shape of the conductive filament is desirably controlled, enabling excellent switching behavior. We demonstrate a clear improvement of the microstructure and density of the WO3 layer by increasing the oxidation time and temperature, resulting in a strong increase of the high-resistance-state breakdown voltage. The high quality WO3 microstructure allows thus the use of a larger reset pulse amplitude resulting both in larger memory window and failure-free write cycling.

We investigate the impact of pulse programming conditions on data-retention of 40nm × 40nm TiN\HfO2\Hf RRAM devices, focusing on the failure of tail bits. We demonstrate that retention loss tail bit is not due to out diffusion of filament constituents but by low activation-energy (Ea∼0.5eV) diffusing species, which are understood as metastable Oxygen (O)-ions in the neighborhood of the conductive-filament constriction. In order to minimize their impact, effective programming pathways are demonstrated, as the low-Ea population is better reduced by (i) using longer Write pulses rather than higher current-pulse amplitudes, and/or by (ii) using shorter reset pulse prior to Write set.

We statistically investigated for the first time resistance stability in HfO2 RRAM devices in the short (μs to s) transient after switching. We show that, the resistance value of both logic states is not stable after programming and subject to large discrete stochastic fluctuations. The frequency of fluctuation is found to be time-decaying thus hindering its detection in DC condition but considerably affecting throughput and effectiveness of write algorithms. We finally identify this instability as the primary source of the well-known resistance variability and we qualitatively explain it in terms of relaxation oscillation of filament microscopic configuration.

We introduce for the first time a novel integration scheme of CBRAM cells, where the Cu electrode is patterned using a subtractive dry-etching process. We demonstrate excellent performances of 30nm-size cells (1µs-write at ≤50µA, >106 endurance, excellent retention at 150°C) as well as scaling potential of CBRAM down to 10nm-node using 5nm-thick Cu electrodes.

In this abstract we demonstrate that CBRAM devices based on SiO2 dielectric can target sub-10µA application, ensuring large programming window, fast and low-voltage switching and limited cycle-to-cycle variability at 5 µA. We report, for the first time, reliable 1-µs forming operation at 5 µA on RRAM devices. The thorough comparison of SiO2- and Al2O3-based devices, in terms of electrical and physical characterization, suggests that the Cu mobility in the switching layers plays a key role, impacting forming/switching speed as well as functionality at low current, and that it can be tuned by properly selecting the switching layer material. We also correlate the mismatch in the electrical performances in the sub-10 µA regime to different filament configurations in the two resistive states.

We propose a novel metal/silicon/metal (MSM) selector using ultrathin undoped amorphous silicon (a-Si) for resistive-RAM selector application. The new selector behaves as a bidirectional diode, showing a high current drive (~2.2 MA/cm)2, high selectivity (~240 for 1/2 bias), fast switching speed , and excellent endurance ( at target drive current). The doping-free a-Si structure alleviates the dopant-induced variability concerns for ultrascaled devices and eliminates the need for a dopant-activation anneal. Circuit simulations show feasibility of 1-Mb array, with over 25% read margin and 70% write margin, when using the new MSM structure as a selector for a HfO2-based resistive switching memory element.

We report on a novel high-performance metal-insulator-metal tunnel diode, with ultrathin atomic layer deposited Ta2O5, for bidirectional selector applications in resistive switching memory. The diode exhibits high drive current of over 105 A/cm2, high nonlinearity, and fast turn-on and turn-off times in the below-ns range. A very good uniformity for structures down to 40 nm size and excellent ac endurance is demonstrated, well exceeding the stand-alone nonvolatile memory requirements.

We demonstrate the strong impact of reset amplitude and duration on the endurance degradation of scaled TiN\Ta 2 O 5 \Ta cells, which from ab-initio and electrical switching simulation is attributed to O interaction with TiN. Clear improvements are obtained using (i) shorter write pulses, (ii) low O-affinity Ru bottom electrode, and or (iii) higher O-affinity HfO 2 dielectric.

An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.