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A dual-bit trapping device, which solves most of the problems by using a split-gate structure, inspired by the HIMOS concept is presented. The device allows a high density thanks to dual-bit/cell storage and it is easily scalable since the structure is fully self-aligned and the bit areas are physically isolated.

The required transition from control gate wraparound to planar structure for NAND flash scaling below 20-nm node causes important loss of coupling factor. In order to recover the program/erase (P/E) window, we develop a novel intergate dielectric (IGD) stack. Simulations identify an ideal three-layer structure that reduces leakage through the IGD and thus improves the memory window at controlled equivalent oxide thickness. A thorough materials investigation allowed to fabricate such three-layer IGD stacks, demonstrating more than 18 V P/E window, good retention, and endurance. [ABSTRACT FROM AUTHOR]

High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa$ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- $\kappa$ IGD structures, and the fast window instability can be eliminated. [ABSTRACT FROM PUBLISHER]

High-\kappa stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-\kappa materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-\kappa IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-\kappa IPD materials. [ABSTRACT FROM PUBLISHER]

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH -evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) \SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly dielectrics. In this paper, we show results on \Al2\O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials. [ABSTRACT FROM PUBLISHER]

In this paper, a model for describing tunneling from Si inversion layers is discussed. The model accounts for the quantization effects at the silicon/dielectric interface and is able to closely follow the self-consistent calculation of the potential and inversion charge in an inverted MOS structure. It is also applicable to multilayer gate stacks, since a general procedure is used for calculating the transmission through dielectric stacks. Influence of both material and geometrical parameters of a dual layer stack are discussed and scaling projections are inferred. [Copyright &y& Elsevier]

We investigate the use of HfO2 based high-k materials as inter-gate dielectric in hybrid floating gate based memory cells for planar NAND flash. The incorporation of Al or Gd in the HfO2 allows reaching higher k values as compared with pure HfO2 through different crystalline characteritics. However, a difficult compromise is to be found between the k value and low leakage due to grain boudaries in a material with large crystalline proportions. Hence, HfGdO reaches a k value as high as 23 but shows important leakage that translates into early program saturation and room temperature charge loss. The HfAlO has more moderate k of \sim16 but shows lower leakage leading to improved device performances. Finally, a three layer stack where a high-k HfAlO layer is encapsulated into Al2O3 thinner layers shows overall best compromise in terms of program/erase window and retention. [ABSTRACT FROM PUBLISHER]