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Densely embedding Magnetic Tunnel Junctions (MTJ) in CMOS logic circuits is considered as one potentially powerful solution to bring non volatility, instant on/off and low standby power in today's programmable logic circuits, in order to overcome major drawbacks while preserving high operation speed. A critical issue in this process is the integration of MTJ electric signal to CMOS electronics, in particular the requirement of "zero" read/write error for logic applications. In this paper, we propose a new sense amplifier circuit, called Pre-Charge Sense Amplifier (PCSA). This circuit, comprising 7 CMOS transistors at minimum size, is able to read the magnetic configuration of a pair of magnetic tunnel junctions with opposite configurations at high speed (about 200 ps), with very low power and error rate compared to previously proposed solutions. Simulations using a ST Microelectronics 90 nm design kit and a compact model of MTJ demonstrate the performances of PCSA. [ABSTRACT FROM AUTHOR]

Electrons have a charge and a spin, but until recently these were considered separately. In classical electronics, charges are moved by electric fields to transmit information and are stored in a capacitor to save it. In magnetic recording, magnetic fields have been used to read or write the information stored on the magnetization, which 'measures' the local orientation of spins in ferromagnets. The picture started to change in 1988, when the discovery of giant magnetoresistance opened the way to efficient control of charge transport through magnetization. The recent expansion of hard-disk recording owes much to this development. We are starting to see a new paradigm where magnetization dynamics and charge currents act on each other in nanostructured artificial materials. Ultimately, 'spin currents' could even replace charge currents for the transfer and treatment of information, allowing faster, low-energy operations: spin electronics is on its way. [ABSTRACT FROM AUTHOR]

Discusses the adaptation of a scanning near-field optical microscope (SNOM) to image magnetic domains. Samples chosen for the structural characterization of magnetization reversal dynamics; Application of cobalt/platinum (Co/Pt) and cobalt/nickel/platinum (CoNi/Pt) samples in high resolution magnetic imaging in a SNOM; Recognition of imaging artifacts.

The article provides information on the efforts of physicists to discover a device that will use only flow of spins. It highlights the research of Tao Yang and colleagues on how to switch magnetization of a particle from electric current to a pure spin current through the demonstration of non-local spin valve. It notes that there are many problems that need to be mastered before a free current tool will be realized.

The article presents a report on Magnetic domain walls, which can be considered to be self-assembled stable nanostructures; moreover, they can be created or annihilated by external action. The manipulation of domain walls in stripes has already been proposed as a way of storing information or even performing logic functions. Conventional (CMOS) electronics is facing major technical hurdles, particularly that of miniaturization. New approaches are needed to reduce energy dissipation and fabrication costs while maintaining the rate of reduction of dimensions, and must be implemented within 15–20 years.

In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 am design kit and a complete magnetic tunnel junction model. [ABSTRACT FROM AUTHOR]

The VHSIC hardware description language (VHDL) simulation of domain wall logic allows to validate magnetic circuits functionality early in the design stage. In this paper, we present two VHDL simulation techniques for domain wall (DW) logic. The first one, closer to the physics, uses models of components described at the behavioral level. It allows to study the basic functions and reveals the specificities of DW logic. The second one, closer to the logic, models components with logic gates and delays and it allows very fast simulation of complex circuits. [ABSTRACT FROM AUTHOR]

CMOS downscaling makes advanced memory and computing systems more vulnerable to radiation. Emerging non-volatile memories such as Magnetic RAM (MRAM) are under development to replace SRAM and FLASH memories. Spin Transfer Torque Magnetic Memory (STT-MRAM) is considered as one of the most promising memories for high reliability applications. This is due to its intrinsic hardness to radiation, as storage is based on the spin direction of electrons instead of the charge. Its peripheral CMOS circuits are sensitive to radiation; however we can recharge frequently the non-volatile storage to get correct data. Different from conventional MRAM based on magnetic field switching, STT-MRAM is unable to be used directly for hard radiation applications as the current pulses induced by radiation may change the storage due to the stochastic behaviors of spin transfer torque mechanism. In this paper, we analyze firstly this issue and propose a rad-hard design for STT-MRAM sensing circuit with low area overhead and negligible performance degradation. Both transient and Monte-Carlo simulation have been performed to demonstrate its performance and behaviors. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) embedded in complementary metal–oxide–semiconductor (CMOS) has been considered as one of the potentially powerful solutions to build up nonvolatile memory and logic circuits. It possesses many intrinsic merits, such as high speed, instant on/off, good scalability and low-leakage power, and promises to extend the Moore's law. A critical issue in this hybrid MTJ/CMOS structure is the reliable integration of MTJ electric signals to CMOS electronics, especially for the deep submicrometer technology nodes (e.g., 28 nm) in presence of low supply voltage and serious process variations. In this paper, we propose a new sensing amplifier, named separated precharge sense amplifier. This circuit, by separating the discharging and evaluation stages of the sensing operation, can operate at a lower supply voltage (<1.0~V) and reduces the effects of process variations as technology scales, thereby providing higher sensing reliability compared with the previously proposed solutions while preserving the high-speed and low-power consumption. Transient and Monte-Carlo statistical simulations are performed to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Ferroelectric tunnel memristor (FTM) was recently discovered. Its resistance can be continuously tuned by controlling the growth of domain in ferroelectric tunnel barrier. Experiments show its large OFF/ON resistance ratio (>10²) and high operation speed (∼10 ns), providing great potential to build up multi-level storage and neuromorphic circuits. However, the corresponding electrical model for circuit simulation is still lacking. In this Letter, we developed a compact model for a voltage-controlled ferroelectric tunnel memristor based on experimental results and ferroelectric switching dynamics. The memristive behavior of this model was demonstrated by resistance measurements as a function of the amplitude and duration of programming voltage pulses, and the accuracy was validated by the relative good agreement between simulation results and experimental measurement. Our model was used to simulate a FTM-based spike-timing dependent plasticity circuit to show its use in neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Ferroelectric tunnel junction (FTJ) is able to store non-volatile data in the spontaneous polarization direction of ferroelectric tunnel barrier. Recent progress has demonstrated its great potential to build up the next generation non-volatile memory and logic (NVM and NVL) thanks to the high OFF/ON resistance ratio, fast operation speed, low write power, non-destructive readout and so on. In this paper, we present the first physics-based compact model for Co/BTO/LSMO FTJ nanopillar, which was reported experimentally to exhibit excellent NVM performance. This model integrates related physical models of tunnel resistance, static switching voltage and dynamic switching delay. Its accuracy is shown by the good agreement between numerical model simulation and experimental measurements. This compact model has been developed in Verilog-A language and validated by single-cell simulation on Cadence Virtuoso Platform. Hybrid simulations based on 40 nm-technology node of FTJ memory arrays and non-volatile full adder were performed to demonstrate the efficiency of our compact model for the simulation and analysis of CMOS/FTJ integrated circuits. [ABSTRACT FROM AUTHOR]

Power issues have become a major problem of CMOS logic circuits as technology node shrinks below 90 nm. In order to overcome this limitation, emerging logic-in-memory architecture based on nonvolatile memories (NVMs) are being investigated. Spin transfer torque (STT) magnetic random access memory (MRAM) is considered one of the most promising NVMs thanks to its high speed, low power, good endurance, and 3-D back-end integration. This paper presents a novel magnetic full-adder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM. It provides advantageous power efficiency and die area compared with conventional CMOS-only full adder (FA). Transient simulations have been performed to validate this design by using an industrial CMOS 40 nm design kit and an accurate STT-MRAM compact model including physical models and experimental measurements. [ABSTRACT FROM PUBLISHER]

Highlights: [•] We analyse and model the reliability issue in STT-MRAM. [•] We present a low-cost OLSC circuit to improve STT-MRAM reliability. [•] Built-in-form implementation using STT-MRAM-based logic acts as an inner code. [•] Its simple codec provides very low area and high speed. [•] Modular codec structure enables adaptive error correction capability. [Copyright &y& Elsevier]

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I>Ico) and Neel-Brown model (I<0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication. [ABSTRACT FROM AUTHOR]

A new path to frame low power, high-density and fast integrated circuits has been rolled out by the observation of current-induced domain wall (DW) motion in magnetic track. As an advanced extension of this mechanism, high performance racetrack memory can be built up combining with magnetic tunnel junction (MTJ) read and write heads. The rapid progress of CoFeB/MgO perpendicular magnetic anisotropy (PMA) shows that the PMA MTJ can be scaled down to 20 nm while keeping fast data access. These recent discoveries allow us to design an ultra-high density content addressable memory (CAM), one of the most important applications of MRAM. The mainstream CAMs suffer from high power and large area as its conventional structure is composed of numerous large-capacity SRAM blocks in order to provide fast data access. MRAM based non-volatile CAMs have been proposed to relive the power consumption, however the density issue cannot be surmounted due to the large switching currents. In this paper, we present a design of NOR-type CAM based on DW motion in PMA magnetic tracks. The CMOS switching and sensing circuits are globally shared to optimize the cell area down to 6 F^2/bit; the complementary dual track allows the local sensing and faster data search speed while keeping low power. By using an accuracy spice model of PMA racetrack memory and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its functionality and evaluate its high performance. [ABSTRACT FROM PUBLISHER]

Spin transfer torque (STT) is one of the most promising switching approaches for magnetic tunnel junction (MTJ) nanopillars to build up innovative nonvolatile memory and logic circuits. It presents low critical current (e.g., < 100\ \muA at 65 nm), simple switching scheme, and fast-speed; however, it suffers from a number of reliability issues like stochastic switching effects, process voltage temperature (PVT) variations, and erroneous reading etc. The mainstream solution is to enlarge the write pulse duration to reduce error rate, which sacrifices the speed and low power advantages. In this paper, we present a new switching circuit for STT memory and logic, allowing “error-free” as the switching operation becomes deterministic benefiting from the self-enabled mechanism. The switching power efficiency can be also improved thanks to a shorter switching duration. By using an accuracy spice model of STT-MTJ and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its high-reliable write/read operations and evaluate its potential area, power, and speed performance. [ABSTRACT FROM PUBLISHER]

Magnetic RAM (MRAM) is considered as a promising nonvolatile memory technology for aerospace and avionic electronics thanks to its intrinsic hardness to radiation. Data is stored on the spin direction “up” and “down” of electrons instead of positive and negative charge. Thanks to its fast speed, easy integration with CMOS and infinite endurance, MRAM has been proposed to build up nonvolatile latches and logic circuits to overcome the power challenge of conventional CMOS circuits. However, they are vulnerable to single event effects (SEE) due to their CMOS peripheral circuits. Hardening techniques to mitigate SEE are described in this paper. A new design of Radhard MRAM latch is firstly presented. TMR technique is then implemented on configurable logic block (CLB) to mitigate SET on data paths. By using 65 nm design kit and an MRAM compact model, hybrid simulations have been done to demonstrate the radiation hardness and performance. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area. [ABSTRACT FROM PUBLISHER]

The current challenges of spintronic devices are the large power and long latency for magnetic switching. Current-induced domain wall (DW) motion is a new switching mechanism promising low-power, high-density, and high-speed circuits. It was first studied to build “race track” memory, which is considered as one of the most emerging technologies for future stand-alone memory. Based on the 3-D hybrid integration above CMOS circuits and using magnetic tunnel junction (MTJ) as the write/read heads, DW motion can be advantageously extended to logic and embedded memory applications. In this paper, we present the first DW shift register-based lookup-table circuit to build reconfigurable logic, which may nearly halve the die area compared with conventional SRAM-LUT by sharing a number of subcircuits and suggest some new functions such as multicontext configuration and run-time reconfiguration for further performance improvement. By using a DW electrical model and CMOS 65-nm design kit, its performances such as low power and high computing/reconfiguration speed have been simulated or calculated. [ABSTRACT FROM AUTHOR]

We investigate magnetization reversal assisted by electric fields in a Co40Fe40B20/Co/Pd multilayer with soft perpendicular anisotropy deposited onto an epitaxial piezoelectric layer. Both the nucleation and depinning magnetic fields show a strong reduction of up to 30% under the application of an electric field. These results show good prospects for assisting the switching processes in ultra-low-power spintronic devices. [ABSTRACT FROM AUTHOR]

We present an experimental study of spin-torque driven vortex self-oscillations in magnetic nanocontacts. We find that, above a certain threshold in applied currents, the vortex gyration around the nanocontact is modulated by relaxation oscillations, which involve periodic reversals of the vortex core. This modulation leads to the appearance of commensurate but also, more interestingly here, incommensurate states, which are characterized by devil's staircases in the modulation frequency. We use frequency- and time-domain measurements together with advanced time-series analyses to provide experimental evidence of chaos in incommensurate states of vortex oscillations, in agreement with theoretical predictions. [ABSTRACT FROM AUTHOR]

Reversal of synthetic antiferromagnetic and synthetic ferrimagnetic multilayer structures are studied theoretically in the precession-dominated regime. The role of key material and geometrical parameters for determining the switching characteristics and addressing regions are investigated. [ABSTRACT FROM AUTHOR]