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This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions ( $L_{G}= 40$ nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub-20 nA/ $\mu \text{m}~I_{\mathrm{\scriptscriptstyle off}}$ at $V_{\mathrm {{\text {DD}}}}= -0.5$ V and $L_{G}= 40$ nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any $L_{G}= 40$ -nm Ge pMOS channel device.

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

In this work, we propose replacement metal contact (RMC) flow by using sacrificial ILD0 that is suitable for wrap around contact (WAC). RMC minimize erosion of gate plug, spacer and S/D area at scaled contact formation. The concept of the flow has been demonstrated in short loop flow with ~50% contact resistance improvement for both NMOS, Si:P and PMOS, SiGe:B.

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I on =500μA/μm at I off =100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si 0.3 Ge 0.7 SRB.

An analysis of pocket dopant deactivation and its impact on $V_{\textrm {th}}$ variation for scaled Si devices using an atomistic kinetic Monte Carlo approach are shown in this paper. B 5 keV, $5\times 10^{13}$ /cm $^{\mathrm {{2}}}+$ As 1 keV, $1 \times 10^{15}$ /cm $^{\mathrm {{2}}}$ implants were used for B pocket deactivation study. An effect of laser annealing (LA) before spike-Rapid Thermal Annealing (RTA) was investigated. In case of B pocket implant, a stable B cluster configuration is changed from $\text{B}_{\mathrm {{3}}}\text{I}$ (>1020 °C) to BI $_{\mathrm {{2}}}$ at spike-RTA temperature $\sim 1020^{\circ }\text{C}$ . BI $_{\mathrm {{2}}}$ is a source of B pocket deactivation with lower temperature than 1020 °C. LA before low-temperature spike-RTA ( $V_{\textrm {th}}$ mismatch figure of merit extracted from Pelgrom plot (Avt) degradation in nFET is shown as spike-RTA temperature is reduced. LA before spike-RTA shows a better short channel effect with lower drain-induced barrier lowering in nFET. LA + spike-RTA at 1000 °C shows better Avt than spike-RTA-only. The difference of pocket deactivation is one of possible important reasons for the higher $V_{\textrm {th}}$ mismatch for nFET than for pFET.

Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (L g =40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (L g =40nm) with DIBL of 30mV/V and sub-threshold slope (SS sat ) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

In this article, modeling of junction formation in scaled Si device is shown. An atomistic kinetic Monte Carlo (KMC) diffusion modeling is used for the analysis of dopant diffusion and defects during shallow junction formation processes. Dopant diffusion and defect evolution during sub-millisecond non-melt laser annealing (NLA) are studied in both experiments and an atomistic kMC diffusion modeling. Pre-amorphization implant is often used for ultra shallow junction formation. It is shown that Solid Phase Epitaxial Regrowth (SPER) annealing stage plays an important role for dopant diffusion in junction formation process. As Ge implant energy is increased, damage structure and IV composition of Amorphous Pockets are changed and this affects the dopant diffusion and activation behavior. KMC simulations show that B, As deactivation is induced by the formation of dopant-defect complexes, such as B n I m , As n V m , As n I m , As n , during millisecond annealing time range. Both experiments and KMC show that defect evolution during millisecond annealing time range. Fluorine, Carbon co-implant effects are also modeled using KMC.

Sub-30nm L G Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14–16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.

A comparative study of the growth behavior of nm-thin ruthenium layers by plasma enhanced atomic layer deposition using two ruthenium precursors is discussed. For bis(ethylcyclopentadienyl)-ruthenium or Ru(EtCp)2, we have found a large incubation time on titanium nitride when using N2/NH3 plasma. With N2/H2 plasma the incubation was significantly reduced. For (methylcyclopentadienyl-pyrrolyl)ruthenium or MCPRu, no incubation was observed for either plasmas. The measured growth per cycle was ~ 0.02 nm for Ru(EtCp)2 whereas ~ 0.04 nm for MCPRu. The top surface of the PE-ALD Ru films can be oxidized without surface roughening by applying a low pressure O2 anneal, while O3 exposure leads to roughening due to etching and re-deposition downstream of etched Ru. Awareness of the impact of oxidizing ambients on Ru is essential for successful integration of Ru layers as electrode in metal-insulator-metal capacitors.

A dry-wet patterning process for La2O3/HfO2-containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl3-step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

The thermal stability of Ni(Pt)-silicides by carbon implantation was evaluated. The Ni(Pt)-silicide morphology and phase formation were studied by means of sheet resistance (Rs) measurements, scanning electron microscopy (SEM) and transmission electron microscopy (TEM) inspection, energy dispersive spectroscopy (EDS) and X-ray diffraction (XRD) analysis. The substrate crystallinity, carbon implantation dose and energy and the anneal conditions determine the stability of the silicide. Platinum and carbon increase the phase stability of Ni-silicide at high temperatures by increasing the disilicide nucleation temperature. The dominant degradation mechanism is morphological degradation for the NiPtSi:C films whereas transition to the NiSi2 phase is the dominant degradation mechanism for NiSi:C films. As compared to carbon incorporation by epitaxial growth of Si:C, the carbon implant has the advantage of being a simple technique that can also be applied to pMOS devices.

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy 2 O 3 capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (J G ) reduction; (2) adding a cap has no significant impact on T inv (

In order to measure silicide-to-silicon specific contact resistance rhoc, transmission line model (TLM) structures were proposed as attractive candidates for embedding in CMOS processes. We optimized TLM structures for nickel silicide and platinum silicide and evaluated them for various doping levels of n- and p-type Si. The measurement limitations and accuracy of the specific contact resistance extraction from the optimized TLM structures are discussed in this paper.

Low Vt Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the Vt shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low Vt dual implantation approach proposed achieves a low-cost "dual dielectric" implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-k dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.

NiPt (10% Pt) and Pt were investigated as alternatives to Ni for contact formation to SiGe (20%) source/drain. The germanosilicide phase formation and morphology were studied by means of sheet resistance measurements, X-ray diffraction (XRD) analysis and scanning electron microscopy (SEM) inspection. From isothermal anneals it is found that NiPt- and Pt-germanosilicide have better thermal stability compared to Ni-germanosilicide. Improved thermal stability is observed for Ni-, NiPt- and Pt-germanosilicide on B doped SiGe as compared to undoped SiGe. The degradation mechanism of NiPt- and Pt-germanosilicide films on SiGe is morphological degradation while the film is still in the mono-(germanosilicide) phase.

Flexibly controllable threshold voltage (V"t"h) asymmetric gate oxide thickness (T"o"x) independent double-gate (DG) FinFETs (4T-FinFETs) have been demonstrated. Thin drive-gate oxide (HfO"2 or SiON or SiO"2) and slightly thick V"t"h-control-gate oxide (thick SiO"2+drive-gate oxide) have been successfully incorporated into the 4T-FinFETs by utilizing the ion-bombardment-enhanced etching of SiO"2. It was experimentally confirmed that, all the asymmetric T"o"x 4T-FinFETs give the significantly improved subthreshold slope and thus gain higher on-current as compared to the symmetric one. Simulation results showed that the asymmetric T"o"x 4T-FinFETs are advantageous even in 20-nm-gate-length region.

A systematic analysis of the different methods of work function (WF) tuning for gate stacks using fully silicided (FUSI) gate electrodes is presented. We show that FUSI gates have the potential to meet the WF requirements for future nodes, including high performance applications, achieving band edge WF, with total WF range of up to ~900 meV. The introduction of dopants (such as Sb, As, P, B) by ion implantation is shown to be effective to tune the WF of NiSi or Ni"3Si"2 on SiO"2 or SiON by ~550 meV, but is ineffective on HfSiON or for Ni-richer silicides. Different silicide phases can be used for Ni FUSI gates on HfSiON dielectrics, taking advantage of the higher WF of metal-rich silicides, achieving a WF range of ~400 meV. This method is not effective, however, on SiON dielectrics. The introduction of Lanthanides by several techniques (such as dielectric cap deposition, ion implantation into poly-Si, or at metal deposition) that result in the modification of the dielectric, is found, for Ni FUSI gates, to achieve low WF (~4.0 eV) suitable for NMOS. Similarly, incorporation of Al can be used to achieve PMOS type WF, as well as the use of metal-rich Ni and/or Pt based FUSI gates (with WF as high as 5.0 eV).

This paper describes a comprehensive study on the optimum gate workfunction (GWF) for four-terminal-driven multigate MOSFETs (4T-MUGFETs). CMOS 4T-MUGFETs with HfO2 high-kappa gate insulator (EOT=1.4 nm) and TiN metal gate have been experimentally demonstrated, and their optimum GWF has been thoroughly investigated. Based on the investigation, it was concluded that the optimum GWF is around 4.32 eV for the NMOS 4T-MUGFETs while 5.17 eV for PMOS 4T-MUGFETs. The reason for the existence of the optimum GWF for the 4T-MUGFETs has been comprehensively explained on the basis of the universal relationship between the initial Vth in the 3T-mode (VthDG), Vth in the 4T-mode (Vth(G1)), and the second gate bias in the 4T-mode (Vg2)

We report for the first time that the optimization of a HfSiON process on Ni-FUSI devices is best tackled using a design of experiments (DOE [Myers RH, Montgomery. Response surface methodology. New York, DC: Wiley; 1995]) approach. We show that a DOE allows for directly linking process parameters to relevant short channel performance metrics. By tuning the SiO2 thickness, HfSiO thickness, Hf concentration, nitridation parameters and by using response surface modeling (RSM), we report an improvement of 12%/17% in nMOS/pMOS drive current (Idsat 600/255 uA/μm at Ioff = 20 pA/μm and Vdd = 1.1 V) over our reference process. In parallel, we demonstrate that by selecting the right parameters, plasma nitridation can outperform thermal nitridation with NH3. We believe that this new approach will be useful for device engineers and can be easily applied.

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The I ON /I OFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

NiPt (10% Pt) and Pt were investigated as alternatives to Ni for contact formation to SiGe source/drain. The germanosilicide phase formation and morphology were studied by means of sheet resistance measurements, XRD (X-ray diffraction) analysis and SEM (scanning electron microscopy) inspection. From isochronal and isothermal anneals it is found that NiPt- and Pt-germanosilicide have better thermal stability compared to Ni-germanosilicide. NiPt-germanosilicide degrades morphologically, while still in the monogermanosilicide phase.

A study of the implementation of Ni fully silicided (FUSI) gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates, resulting in a larger reacted Ni-Si ratio at short gate lengths. The linewidth dependence of the Ni FUSI phase results in an undesirable kink in the V"t roll-off characteristics, due to the difference in effective work function between the Ni silicide phases, which is particularly large for HfSiON dielectrics. An optimized 2-step RTP silicidation process is shown to eliminate this problem allowing the formation of NiSi gates uniformly at all gate lengths. The application and scalability of Ni-rich silicides to PMOS devices is also demonstrated, as well as a scheme for CMOS integration of dual WF phase controlled FUSI (NiSi for NMOS and Ni-rich silicides for PMOS), using an etch back step to reduce the poly-Si height on PMOS electrodes before full silicidation.

Integration of recessed Si:C source/drain (S/D) for deep sub- micron nMOSFET devices results in substantial improvement of electron mobility and drive current due to introduction of tensile strain in the channel. The compatibility of Ni-silicide contacts with Si:C source/drain is investigated in this paper. The Ni-silicide morphology and phase formation were studied by means of sheet resistance measurements, X-Ray Diffraction (XRD) and Energy Dispersive Spectroscopy (EDS) analysis, Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) inspection. The carbon concentration and profile in the NiSi:C film was studied by Secondary Ion Mass Spectrometry (SIMS) analysis. The strain in the Si:C substrate and NiSi:C film was studied by high resolution XRD (HRXRD). This paper demonstrates that Ni-silicide is compatible with Si:C. The tensile strain in Si:C is maintained after Ni-silicidation. The addition of carbon to silicon is found to stabilize the silicide morphology.

The Ni silicide phases and morphology in Ni fully silicided gates was investigated for varying deposited Ni to Si thickness ratios and rapid thermal processing conditions. The presence of NiSi"2, NiSi, Ni"3Si"2, Ni"2Si, Ni"3"1Si"1"2 and Ni"3Si as predominant phases was observed for increasing Ni to Si thickness ratios. In most samples, typically two of these phases were detected by X-ray diffraction. No secondary phases were detected on Ni"3Si samples (Ni to Si thickness ratio ~1.7). For samples targeting NiSi as gate electrode, RBS and TEM analysis confirmed a layered structure with NiSi at the interface and a Ni-rich silicide layer (Ni"2Si, Ni"3Si"2) on top. Process conditions were determined for the formation of gate electrodes for NiSi, Ni"2Si and Ni"3Si. Only small changes in flat-band voltage or work function were found between these phases on SiO"2 or SiON for undoped samples. While significant changes in work function with dopants were observed for NiSi on SiO"2, little or no effects were found for NiSi on HfSiON (suggesting Fermi-level pinning) and for Ni"2Si on SiO"2. An increase of >300mV was found from NiSi to Ni"3Si on HfSiON, suggesting unpinning of the Fermi level with the Ni-rich silicide.

Insight in the thermal degradation phenomena and the relation to phase transformation is presented for cobalt disilicide (CoSi2) on narrow polysilicon lines (linewidth ranging from 30nmto1μm) using electrical and morphological analysis in the temperature range 650–900°C. When polysilicon lines are scaled laterally to 30nm, an abrupt CoSi2 sheet resistance increase (>1000Ω∕sq) is observed, which is attributed to silicide agglomeration. At localized positions along the 30-nm Co-silicided lines, Si/silicide layer inversion is observed. At low formation temperature (650°C), no agglomeration phenomena occur, but incidentally the transition from CoSi into CoSi2 is delayed on the 30-nm-wide polysilicon structures to such an extent that the CoSi2 growth virtually stops. Only using nitrogen implantation through CoSi and a CoSi2 formation temperature of 900°C, low sheet resistance values are obtained for 35-nm-wide polysilicon lines. Based on the results obtained in the present work, we propose that the abrupt incr...

Excessive Ni-silicide formation is observed at the edges of poly gates and source/drain lines. The excessive silicidation results in locally completely silicided poly gates and in very high junction leakage in small source/drain islands. It was studied whether the excessive Ni-silicide formation in narrow features can be reduced in a two-step Ni-silicide process in which the thermal budget of the first RTP step is just enough to fully react the Ni. It was found that the excessive silicidation can be avoided either by reducing the anneal temperature or by reducing the anneal time. Reducing the thermal budget of the first RTP step was found to significantly improve the junction leakage in small source/drain islands for As junctions. No improvement was observed for B junctions. The latter is thought to be related to the presence of NiSi"2 pyramids.

The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node.

As scaling progresses, conventional Co/Ti silicidation is facing difficulties related to the nucleation of the low resistive Co-disilicide phase during the second RTP step of silicidation. When linewidths, junction depths and silicide thicknesses are being reduced, the RTP2 thermal process window narrows down rapidly. It is expected that the process window can be widened by alloying the Co film with Ni, because the presence of Ni lowers the nucleation barrier for the Co-disilicide phase. Replacing Co-disilicide by Ni-monosilicide is a promising alternative because the same silicide sheet resistance can be obtained with 35% less silicon consumption.

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G M,SAT,EXT / SS SAT of 250 µS.µm−1 / 130 mV.dec−1 (at the targeted V DS =0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

We present a comprehensive study of Si 0.55 Ge 0.45 -cladded p-channel FinFETs, including a comparison with planar SiGe quantum-well devices. The SiGe-cladded FinFETs exhibit ~2× higher hole mobility, ~2× better I ON /I OFF , and improved DIBL compared to Si control devices. Superior NBTI reliability over equivalent Si FinFETs is demonstrated for cladding thicknesses down to 3 nm. The dependencies of drive current and hole mobility on both SiGe thickness and device width are examined in detail. This analysis shows that SiGe thickness conformality and epitaxial facet control are crucial for the optimization of SiGe-cladded FinFETs.

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET INV -normalized G M,SAT,INT of 6.7 nm.mS/μm, the Si 0.3 Ge 0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

CoSi2 formed using a Ti cap has been shown to reduce any oxide or contaminants present during silicide growth to improve the uniformity of the silicide. However, as transistor dimensions shrink, a concern in using CoSi2 is the thermal process window for the second RTP step (RTP2). Thinner silicides agglomerate at lower temperatures but a minimum temperature is required for a uniform silicide with low junction leakage. This paper describes the results of a detailed investigation into the thermal processing of thin Ti-capped CoSi2 compatible with 0.13 μm CMOS technology. Ti-capped CoSi2 films of varying thickness on both poly and active regions were studied for three junction dopants, As, BF2, and B. The parameters investigated in the thermal processing were the temperature, time and ramp rates for RTP2. Sheet resistance, diode leakage, and interface roughness were measured as a function of the thermal processing. The results show that the optimal RTP2 thermal budget for thin Ti-cap CoSi2 on devices is 800°C for 120 s with high ramp rates giving possible leakage improvement.

Crystalline rutile TiO2 films were grown by atomic layer deposition on oxidized Ru electrodes using a titanium methoxide as the metal precursor and O3 as the oxidant. A protective layer of ∼0.3 nm TiO2 grown with H2O as the oxidant was first deposited in order to avoid etching of the Ru bottom electrode by the O3 used for the growth of the TiO2 (bulk) layer. Electrical evaluation of the capacitor stacks with TiO2 as dielectric, RuO2/Ru and Pt as the bottom and top electrodes respectively, resulted in superior characteristics of the rutile phase as compared to the anatase. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this work, the phase formation is compared for Ni- and Co-silicidation with and without Ti cap. In addition, the electrical performance of Ni-silicidation with and without Ti-cap is investigated and compared to the performance of a Co-silicidation process with a Ti cap that has the same Si consumption. The lateral confinement of the silicide in the active areas is also studied.

Flexibly controllable threshold-voltage (Vth) asymmetric gate-oxide thickness (Tox) four-terminal (4T) FinFETs with HfO2 [equivalentoxidethickness(EOT)=1.4 nm] for the drive gate and HfO2+thick SiO2 (EOT=6.4-9.4 nm) for the Vth-control gate have been successfully fabricated by utilizing ion-bombardment-enhanced etching process. Owing to the slightly thick Vth-control gate oxide, the subthreshold slope (S) is significantly improved as compared to the symmetrically thin Tox 4T-FinFETs. As a result, the asymmetric Tox 4T-FinFETs gain higher Ion than that for the symmetrically thin Tox 4T-FinFETs under the same Ioff conditions

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG=50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31 Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff=100 nA/mum) was obtained for Ni 31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt2 Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to ~ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni31Si12) pMOSFET devices. A low threshold voltage les|-0.29 V| was obtained for the Pt2Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt2Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31 Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and Vt control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting in significant Vt shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth Vt rolloff characteristics was demonstrated for NiSi, Ni2Si, and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni2Si are less than or equal to 25 degC, whereas a single-phase Ni31Si12 is obtained over an ~200degC temperature range

An analysis of dopant diffusion and defects in 3D Fin structure using an atomistic lattice kinetic Monte Carlo (KMC) approach are shown. Atomistic KMC simulations are compared with 3D methodology of Atom Probe Tomography (APT). Atomistic dopant distribution in 3D Fin structure is shown. KMC simulation shows that implant temperature has an impact on amorphization and residual defects and dopant-defect complexes are formed at top-of-Fin and edge-of-Fin-side after SPER.

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are reported for the first time, demonstrating peak transconductance gmSAT of 1.3mS/μm at VDS=-0.5V and good short channel control down to 60nm gate length. Optimization of P-doping in the SiGe, optimized Si cap passivation thickness on the Ge, and improved gate wrap of the channel all improve device characteristics. The Ge FinFETs presented in this work outperform published relaxed Ge FinFET devices for the gmSAT/SSSAT benchmarking metric.

Atomistic Kinetic Monte Carlo (KMC) diffusion modeling is used for dopant diffusion and defect analysis in ultra shallow junction formation in Si and SiGe. An analysis of dopant diffusion and defects in SiGe-channel Quantum Well (QW) using an atomistic KMC approach are shown. Thin SiGe layer with high Ge content for SiGe-channel QW has an impact on implantation damage and Boron-Transient Enhanced Diffusion (TED) suppression, and defect evolution. KMC shows that As-pocket in SiGe-channel pFET shows enhanced diffusion toward SiGe-channel and higher As concentration in SiGe-channel. The difference of pocket diffusion is one of possible reason for the higher Vth mismatch for SiGe-channel with As pocket than for Si-channel. To avoid implant damage influence, Implant-Free SiGe channel-QW with B-doped SiGe epi for extension-S/D formation is used. KMC simulation and SSRM shows that B migration from B-doped SiGe raised-S/D to SiGe-channel can form S/D-extension overlap.

An analysis of dopant diffusion and defects in SiGe-channel (SiGe-ch) Implant-Free Quantum Well (IFQW) using an atomistic KMC approach are shown. B-doped SiGe layer is used for S/D-extension formation. KMC and SSRM show that B migration from B-doped SiGe raised-S/D can form S/D-extension gate overlap. Arsenic Vt-adjustment implant before SiGe-ch formation instead of Arsenic pocket implant after SiGe-ch formation can reduce Arsenic concentration in channel region and shows better Vt-mismatch.

We propose a cell structure with monocrystalline floating gate and 6 nm to 8 nm of thermally grown SiO2 interpoly dielectric (IPD) for

A transient leakage current was measured as a function of time for thin (~9 nm) strontium titanate (STO) capacitor dielectrics with RuOx as a bottom electrode and TiN as a top electrode at different temperatures under constant direct current (DC) bias stress. With the space-charge-limited (SCL) current theory, the mobility of oxygen vacancies (VO) and the activation energy (E0) of VO were extracted. By closely examining the time-zero current-voltage (I-V) curves for a positively and a negatively held DC bias conditions before and after the stresses, an understanding of trap-assisted-tunneling (TAT) current, initiated by oxygen vacancies (VO) is presented. Based on this understanding, a way to further reduce the leakage current for a sub-10 nm dielectric film is provided.

An analysis of dopant diffusion and defects in SiGe-channel Quantum Well (QW) with Laser annealing using an atomistic KMC approach are shown. Thin SiGe layer with high Ge content for SiGe-channel QW has an impact on implantation damage and Boron-Transient Enhanced Diffusion (TED) suppression, and defect evolution. KMC shows that As-pocket in SiGe-channel pFET shows enhanced diffusion toward SiGe-channel and higher As concentration in SiGe-channel. The difference of pocket diffusion is one of possible reason for the higher Vth mismatch for SiGe-channel with As pocket than for Si-channel.

Electrical data of advanced capacitor dielectrics such as Sr-rich (Sr/(Sr + Ti) ~ 62%) strontium titanate (STO), rutile TiO 2 , which have dielectric constants higher than 60 even with physical thicknesses in the 7-10 nm range are presented. A practical capacitor model is proposed based on planar metal insulator-metal (MIM) system fabricated using 300 mm toolsets to access required capacitor dielectrics and to predict technical challenges of each technology node. Based on this practical model, mass production friendly path for the introduction of advanced capacitor dielectrics and its choice of electrode to extend life time of Dynamic Random Access Memory (DRAM) is proposed.

A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F 2 ) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.

We study the properties of a single gate oxide trap subjected to AC Bias Temperature Instability (BTI) stress conditions by means of Time Dependent Defect Spectroscopy. A theory for predicting the occupancy of a single trap after AC stress is developed based on first order kinetics and verified on experimental data. The developed theory can be used to develop circuit simulators and predict time dependent variability.