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2. Experimental realization of a 3D integrated RSFQ T-flip-flop using stackrons

3. Develop seamless interconnection among multiple general-purpose boards: inter-chip communication solutions can be tricky. Schemes built around the XMOS link look to simplify interconnections on the application-system and complex-system levels

4. A high CMRR current mode CMOS preamplifier for magnetic recording systems

5. The ultimate dielectric is... nothing: IBM packs wires in vacuum to speed chips and save power

6. Recent advances in process synthesis for semiconductor devices

7. A new device design methodology for manufacturability

10. Circuit performance modeling by means of fuzzy logic

11. The complexity of generalized retiming problem

15. Design trade-offs for the last stage of an unregulated, long-channel CMOS off-chip driver with simultaneous switching noise and switching time considerations

16. Finite Element Analysis of SiGe heterojunction devices

17. Implementation of novel 'push-forward' RSFQ carry-save serial adders

18. Bipolar pattern association using a two-layer feedforward neural network

22. High-Speed Addition in CMOS

23. A design and yield evaluation technique for wafer-scale memory

24. Task-flow architecture for WSI parallel processing

25. Wafer-scale transducer arrays

27. Filter variations

28. Precision preamplifier '96

29. Circuits by design

30. Audio design leaps forward?

32. Designing systems with mixed-voltage ASICs

34. Introducing programmable logic

35. Circuit option boost photodiode bandwidth

36. RAMDACs enhance PC and workstation displays

37. Airbags boom when IC accelerometer sees 50G

38. Trends and challenges in VLSI circuit reliability

39. A Simple Slip-Power Recovery System with a DC Voltage Intermediate Circuit and Reduced Harmonics on the Mains

40. Organic Molecule Rewires Chip Design

41. Quad DAC controls state-variable filter

43. Goof proof your input clock circuit; remove the problems associated with switching clock sources

44. 3D silicon VLSI process offers five times the density of 2D techniques

45. Low-power environment targets chip design

46. Case #114: Testing Parts 'til They're Toast

47. Wireless communications developer joins nanoelectronics design program

48. Statistical timing analysis moving to transistors

50. EDA looks to Asia

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