15 results on '"DeBrosse, J.K."'
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2. Design considerations for MRAM
3. Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
4. The evolution of IBM CMOS DRAM technology
5. A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
6. A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP).
7. A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.
8. A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
9. Flexible test mode approach for 256-Mb DRAM.
10. A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ.
11. Fault-tolerant designs for 256 Mb DRAM.
12. A 0.21 μm/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
13. A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)
14. Floating-body concerns for SOI dynamic random access memory (DRAM).
15. A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM.
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