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1. Ovonic Threshold Switching for Ultralow Energy Physical Reservoir Computing

11. A HydroDynamic Model for Trap-Assisted Tunneling Conduction in Ovonic Devices

14. Unveiling the Vulnerability of Oxide-Breakdown-Based PUF

15. Oxide Reliability Issues

24. Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery

25. Line-to-Line TDDB Modeling: LER Specs for Sub-20-nm Pitch Interconnects

27. High- k dielectrics for future generation memory devices (Invited Paper)

28. Applying complementary trap characterization technique to crystalline \gamma -phase- \hbox {Al}_{2} \hbox {O}_{3} for improved understanding of nonvolatile memory operation and reliability

29. Thermal recovery from stress-induced high-[kappa] dielectric film degradation

38. Hole traps in silicon dioxides-part II: generation mechanism

39. Hole traps in silicon dioxides-part I: properties

47. Ultrathin (4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits

48. Hydrogen induced positive charge generation in gate oxides

49. Interface state generation after hold injection

50. Defect profiling in FEFET Si:HfO2 layers

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