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Similar to other power semiconductors, gallium nitride enhancement-mode high-electron-mobility transistors (GaN E-HEMTs) require short-circuit protection (SCP) or overcurrent protection (OCP) in practical applications. However, the fast-switching characteristic of GaN introduces the challenge to the protection. For SCP, the traditional methods are either too slow or not practical for GaN. Therefore, an alternative SCP solution, which is fast and easy to implement, is much desired. For high power density applications, it is also popular to integrate OCP into the gate driver. Therefore, a fast protection circuit that can be used for either SCP or OCP is desirable. In this article, an ultrafast discrete circuit-based protection circuit is proposed for GaN HEMTs. It includes a first soft turn- off stage and a second hard turn- off stage. The soft turn- off stage effectively limits the voltage spike over the device. Following the soft turn- off stage, the hard turn- off stage will cut off the pulsewidth modulation signal immediately completely. A dual-gate implementation approach is further proposed for devices with two gate pads. The method has been verified by both SPICE simulation and hardware implementations for both SCP and OCP. The experimental results show that the total propagation delay time for SCP is only 125 ns while the normal switching performance is not affected.

The method for modeling switching converters plays a key role in real-time simulators. Associate discrete circuit (ADC) modeling technique is a commonly used method for modeling the switching converter. However, the optimal selection of the ADC-based switch model parameters has great importance in the accuracy of the real-time simulator. In this paper, the design of a real-time simulator for a switching power converter has been done, in which a novel method for detecting optimum values of the switch model parameters has been expressed. Particle swarm optimization (PSO) algorithm is used to find these optimum values using state-space analysis of the modeled circuit in the z-domain. The modified nodal analysis (MNA) method solves the real-time model at each simulation time-step. Case studies are a single-phase 5-level Cascaded H-Bridge (CHB), three-phase 9-level CHB inverter, and a Transmission line. Field-programmable gate array (FPGA) has been used as a platform for implementing the real-time simulator. Experimental result of the real-time simulator of the 5-level CHB inverter on a SPARTAN-6 FPGA and its comparison with the result of a prototype of a 5-level CHB inverter confirms not only the performance of the real-time simulator, but also the effectiveness of the proposed method for confirming the real-time simulator accuracy.

The hardware-in-the-loop (HIL) real-time simulation for high-speed train electrical traction system aims to reduce the design cost and speed up control verification process of algorithms in the developmental stage of the traction control unit. In this study, based on the dSPACE real-time simulator, the multiple-simulator, multiple-simulation step of HIL real-time simulation system is first built. Second, for the associated discrete circuit modelling method, an optimisation method is proposed to minimise the switching loss and improve the simulation accuracy by selecting the optimal discrete-time switch admittance parameter, G S . To decrease the computational burden for field-programmable gate array (FPGA), a decoupling method without simulation latency is presented to reduce the matrix dimension of the system model. Finally, the real-time simulation models of electrical traction system are realised by CPU + FPGA-based simulator, in which the power electronics converter models are computed in FPGA with a fixed 100 ns time-step. The validity and reliability of the real-time simulation system is verified by the HIL simulation and experimental results, which indicate that the real-time HIL simulation at the nanosecond level improves the accuracy essentially.

This paper presents an FPGA-based Digital Real-Time Simulation (DRTS) environment for the analysis of Electromagnetic Transients (EMTs) of power systems that include multiple Power Electronic Converters (PECs). The main features of the proposed DRTS platform are that it i) employs two-value resistor switch model for PECs and thus avoids inaccuracies of Associate Discrete Circuit (ADC) model and ii) does not require separation of PECs by transmission lines (stub lines) and thus accurately represents PECs in close electrical proximity of each other. These features respectively result in a time-variant and large system admittance matrix which significantly increases the computation burden in each simulation time-step and can render it infeasible for real-time applications. To overcome this problem this paper introduces i) Switching-Network Partitioning (SNP) method which is tailored for PECs representation in FPGA and ii) Reformulated Modified Nodal Analysis (RMNA) method to enable computational parallelism between the solution of network and component models in FPGA. SNP enables solution-level partitioning of the PECs and the rest of the system. The developed DRTS platform enables sub-microsecond simulation time-step and provides a fixed hardware irrespective of the system configuration. Performance of the platform is evaluated for a study system and verified versus off-line simulation studies.

Dual active bridge (DAB) converters are widely used in power electronic systems and energy storage devices. However, due to the existence of semiconductor power switches, the converter is a typical strongly nonlinear, variable structure, discrete circuit system in essence. Some strange behaviors often occur when it works, such as some unknown electromagnetic noise, intermittent instability and sudden collapse of the system. In this paper, the nonlinear behavior of dual active bridge converter is studied. Firstly, based on the existing method of constructing discrete model, the discrete iterative model of DAB converter considering the sample and digital control delay is established. The relationship between the stability of the DAB converter and the parameters of the proportional controller is analyzed through the simulation comparison between the discrete iterative model and the traditional single phase shift control model. Finally, the stability boundary is accurately predicted by the phase trajectory diagram, and the bifurcation phenomenon is successfully suppressed by the parametric resonance perturbation method.

In this study, a simple memristor circuit using only one Voltage Differencing Current Conveyor (VDCC), two PMOS transistors and one grounded capacitor, is designed. The presented memristor exhibits electronically controllable characteristics, which are superior to its counterparts. Both the memductance value and the operating frequency can be electronically tuned through voltage sources. The proposed memristor, which occupies 42.2 µm × 27.5 µm area excluding the area of the capacitor, is laid by using Cadence Environment using TSMC 0.18 µm process parameters. In addition, the proposed memristor is implemented by using discrete circuit elements on the breadboard and detailed analyses are given by changing the values of the discrete circuit elements. All results are compatible with the previous studies.

Power converters in the system-level real-time simulation are usually emulated by L/C-based associated discrete circuit (L/C-ADC). However, the L/C-ADC approaches may suffer from two issues: How to mitigate the unacceptable virtual power loss especially in high-frequency applications, and how to tune LC parameters setting which is affected by the external circuit. This paper proposes a novel generalized associated discrete circuit (G-ADC) model with parameterized history current sources. By utilizing the stability region of the feasible parameter space, the optimized G-ADC models with the best damping characteristic are developed for both two-level and three-level converters. The analytical results also guarantee that the parameters of the optimized G-ADC model are independent of the external circuit for most power grid applications. Furthermore, an field programmable gate array (FPGA)-based real-time simulation platform is built to verify the feasibility of the proposed scheme. Extensive simulation and hardware-in-loop experiment results demonstrate the effectiveness and superiority of best-damped models as well as the modeling flexibility corresponding to insensitivity to operating conditions and external system parameters.

Real-time Hardware-In-the-Loop (HIL) simulation tools used at various levels in the development of modern power electronics are inevitable, either testing the control board implementations with signal-level simulators or validating the power converters with power HIL solutions. The high computational power of FPGA devices used in HIL tools offers many advantages, but the developers have to make a trade-off between the precision of HIL models and the resources required by the realization. The half-bridge is the building block of many power converters, its efficient real-time model is useful in the development of HIL simulators of more complex systems. In this paper the advantages and disadvantages of real-time models of the half-bridge are studied. The simple switching function model, the more complex but widely used Associated Discrete Circuit (ADC) model, and a PI controller based model with enhanced Discontinuous Conduction Mode (DCM) emulation are compared.

The memcapacitor is one of the new memory circuit elements although it is not found on the market as a discrete circuit element. In this study, two simple memcapacitor emulators were developed using active circuit elements. These proposed circuits are both electronically controllable. The relationship between charge and flux depending on different frequencies was obtained for both presented memcapacitor circuits. To demonstrate the experimental response of the circuit, discrete circuit elements were used to build the first proposed circuit on the breadboard. All experimental results showed good agreement with the theoretical analyses.

Voltage amplification is an important element of the energy harvesting process to provide an enhanced voltage and run various digital circuits at low power. At RF frequencies, the discrete circuit arrangement using high frequency diode HSMS 2850 and capacitors have been used here to provide the voltage amplification with high power efficiency. The paper describes a mechanism of the Dickson circuit arrangement with its various parameters. The power efficiency is obtained and compared with multiple stages of the Dickson configuration for the input power, frequency of operation and its load using keysight based ADS tool. Finally a neural network has been designed using a Matlab script and the trained neural network has been applied to get the efficiency result. The result shows that with an increase in the multiplier stage of the Dickson circuit, there is a significant increase in its power efficiency. In addition the neural network implementation shows that the circuit parameters can be obtained using a well-trained neural network script.

The evolution of resistive switching device (memristor) technology during the last ten years has shown the great potential of such emerging nanoelectronic devices in several potential applications, ranging from memory to computing and sensing. As memristor technology is continuously maturing, more devices become commercially available and thus accessible to investigators working on relevant research topics, as well as to university teaching labs and academics who wish to incorporate memristor-related experiments in their classrooms. However, experimental work on circuits with memristors requires particular caution and supervision, given that such devices are both highly sensitive (i.e., can easily burn out) and still quite expensive compared to other discrete circuit components. In this context, the development of integrated instrumentation solutions that provide a safe way to experimental work with memristors is becoming increasingly relevant, and some such tools have already reached the market. In this direction, we present some early results from our experience on the design and development of an instrumentation printed circuit board (PCB), designed to provide an ad hoc low-cost solution for measurements on memristors. The driving circuitry on the PCB is interfaced through a microcontroller-based system, providing easy programming and acquisition for a variety of measurements.

Paper describes the research on the output resistance of the nanosecond pulse generator built on a Step Recovery Diode. Such generators are used as sources of short (tenths of a nanosecond) pulses. The latter are the basis for: measuring instruments, impact excitation of ultra-wideband antennas of radar sensors, radar of underground sounding and other purposes. To enable a comprehensive analysis of elements the system of differential algebraic equations is solved. The Equations are written for Kirchhoff's laws, describing the “behavior” of currents and voltages of discrete circuit elements, and the parasitic inductors and capacitors also. This is caused by strong influence of parasitic components on transients in the circuit, operating in the time range of less than a nanosecond, which is equivalent to the gigahertz frequencies and higher. The obtained solutions made it possible to reveal the influence of the nominal values of the generator circuit elements on its output resistance. Adjusting the output resistance of the generator to a value close to the characteristic resistance of the line, through which the pulses of the generator are transmitted to the load, maximize the transmission of power to the load and eliminate masking of the useful signal by pulses of re-reflections in the line.

In this paper we have designed a grounded memcapacitor emulator which is a part of memristive system providing a nonlinear relationship between Charge and Voltage. The Floating Current Source (FCS) possesses a low power consumption feature, has been utilized for the memcapacitor emulation. In this study, a memcapacitor emulator is designed utilizing discrete circuit elements. The proposed emulator circuit exhibits a simple design consisting of MOSFETs and capacitors. The emulator performance is verified theoretically, and computer simulations and results are discussed here.

This article is devoted to the development of analytically described self-oscillation stability research technique. The case when the linear part of the system contains transfer function with a zero pole is considered. Typically the transfer function study, where the numerator degree is two orders of magnitude less than the denominator degree is creates no problems. However, the presence of a zero pole makes the case special and requires investigation.A comparative evaluation of the results of self-oscillation analytical calculation and stability analysis is given, by means of technique developed for symmetric self-oscillations with half-period repetitions and asymmetric ones with period repetitions.The presented technique is a significantly new scientific step in the development of methods for calculating non-linear systems. It also allows us to evaluate the accuracy of approximate calculation methods, which is important for precision systems. The technique is relatively easy to implement. It allows to find a solution as well as for the cases having been unanalyzable so far.

In this paper, memristor emulator circuit consisting of only seven MOS transistors and one grounded capacitor is presented. Memristors exhibit nonlinear voltage-current relationship and many previous emulator circuits have multiplier circuit to provide the nonlinear characteristic of the memristor. But there is no any multiplier circuit block in the proposed circuit so the proposed memristor circuit occupies low chip area. The memristor circuit is laid by using Cadence Environment with TSMC 0.18 µm process parameters and its layout dimensions are only 12 µm × 38 µm excluding the area of the capacitor. The post-layout simulation results for memristor are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. All post-layout simulations agree well with theoretical analyses. Besides the VLSI implementation of the memristor, the proposed circuit is built on the breadboard using discrete circuit elements.

Made available in DSpace on 2019-10-06T16:54:29Z (GMT). No. of bitstreams: 0 Previous issue date: 2018-12-15 This work presents an unprecedented technique capable of representing grounding grids directly in the time domain using an association of passive and discrete circuit elements (RLC circuits: resistors, inductors and capacitors). It is based on the frequency response of RLC circuits and ensures that all elements will be positive (physically implementable), solving situations that other techniques, such as vector fitting, generally presented in the literature are not able to solve using only passive circuits (feasible). The proposed technique is applied from the harmonic impedance previously provided, and therefore this impedance can be obtained using any model. It is accurate; it presents excellent results and was validated by comparing the harmonic admittance and transient voltage curves to those obtained with the hybrid electromagnetic model. The advantage of this technique is that it allows that several components in power systems, such as grounding systems and transmission towers, to be represented by a feasible circuit. Once this circuit is implemented in the laboratory, analysis and comparisons with conventional software (e.g. ATP) can be made and accurate transient electromagnetic responses can be obtained. Campus Votuporanga Federal Institute of São Paulo - IFSP, Av. Jerônimo Figueira da Costa - 3014 Electrical Engineering Department São Paulo State University - UNESP, Av. Brasil Sul - 56 Electrical Engineering Department São Paulo State University - UNESP, Av. Brasil Sul - 56

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 °C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm.

This paper proposes a new n-port hybrid dc circuit breaker for offshore multi-terminal HVDC grid application. The n-port dc circuit breaker can substitute n-1 hybrid dc circuit breakers at a dc bus with n-1 adjacent dc transmission lines. The system level behavior of the proposed multi-port hybrid dc circuit breaker is similar to the behavior of other hybrid dc circuit breakers. The operation principles of the proposed multi-port dc circuit breaker are introduced, analyzed and compared to the existing solution in this work. The components ratings are compared to the existing solution and the functionality of proposed device is verified by simulation. ispartof: IEEE Transactions on Industrial Electronics vol:99 issue:1 pages:1-1 status: published

Purpose This paper aims to design a new bandgap reference circuit with complementary metal–oxide–semiconductor (CMOS) technology. Design/methodology/approach Different from the conventional bandgap reference circuit with operational amplifiers, this design directly connects the two bases of the transistors with both the ends of the resistor. The transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of low dropout regulator (LDO) regulator circuit, at last to realize the temperature control. In addition, introducing the depletion-type metal–oxide–semiconductor transistor and the transistor operating in the saturation region through the connection of the novel circuit structure makes a further improvement on the performance of the whole circuit. Findings This design is base on the 0.18?m process of BCD, and the new bandgap reference circuit is verified. The results show that the circuit design not only is simple and novel but also can effectively improve the performance of the circuit. Bandgap voltage reference is an important module in integrated circuits and electronic systems. To improve the stability and performance of the whole circuit, simple structure of the bandgap reference voltage source is essential for a chip. Originality/value This paper adopts a new circuit structure, which directly connects the two base voltages of the transistors with the resistor. And the transistor acts as an amplifier to amplify the change of voltage, which is convenient for the feedback regulation of LDO regulator circuit, at last to realize the temperature control.

This paper demonstrates a study of a switch-bridge-based readout circuit for differential capacitance measurement in MEMS resonators. The proposed switch-bridge circuit is improved upon a diode-bridge circuit, which is simple, highly sensitive, and environmentally robust. However, the diode-bridge circuit suffers an output limitation due to the requirement of reverse-bias for diodes. The switch-bridge circuit keeps the advantages of the diode-bridge circuit but eliminates its limitation by replacing diodes with switches. As a result, the sensitivity of the switch-bridge circuit can be further improved by increasing the reference voltage. The presented behaviors and characteristics of the switch-bridge circuit are also suitable for the diode-bridge circuit, whose detailed theoretical analyses have not been reported yet. Then, we introduce an error model to investigate the impacts of nonideal switches in practical applications. In addition, the noise feature is discussed by using a power spectral density model. Experimental results show that the switch-bridge-based readout circuit, when applied to a capacitive MEMS gyroscope, achieves a gain of 7.1 V/pF, or equivalently 1.96 V/ $\mu {\mathrm{ m}}$ , and a noise density of 0.077 aF/sqrt(Hz) between 20 Hz to 50 kHz.

Memcapacitors are become one of the research interest after the realization of memristors. Many researchers focused on the designing memcapacitor emulator because of some fabrication difficulties of this new element. In this paper, Voltage Differencing Current Conveyor (VDCC) based memcapacitor emulator is developed. This emulator is composed of two VDCCs and can be electronically controllable. To show the operation performance of the proposed circuit, some analyses and memcapacitor based associative learning circuit are given. TSMC 0.18 µm process parameters are used to simulate the memcapacitor. The circuit is also implemented on breadboard using discrete circuit elements. Both theoretical and simulation results are good agreement when compared previous studies.

In this brief, a nonlinear integrated circuit to harvest different types of digital computation from complex dynamics is designed and fabricated. This circuit can be dynamically reconfigured to implement different two-input, one-output digital functions. The main advantage of the circuit is the ability to implement different digital functions in each clock cycle without halting for reconfiguration.

Thin-film transistors (TFT) in hydrogenated amorphoussilicon, amorphousmetal oxide, andsmallmolecule and polymer organic semiconductors would all hold promise as potential device candidates to large area flexible electronics applications. A universal compact dc model was developed with a proper balance between the physical and mathematical approaches for these thin-film transistors (TFTs). It can capture the common key parameters used for device performance benchmarking of the different TFTs while being applicable to a wide range of TFT technologies in different materials and device structures. Based on this model, a user-friendly tool was developed to provide an interactive way for convenient parameter extraction. The model is continuous from the off-state and subthreshold regimes to the above-threshold regime, avoiding the convergence problems when being used in SPICE circuit simulations. Finally, for verification, it was implemented into a SPICE circuit simulator using Verilog-A to simulate a TFT circuit examplewith the simulated results agreeing verywell with the experimental measurements.

Short-circuit detection is a fundamental function of most inverters. In this paper, two new fast and easily implementable short-circuit detection approaches are presented. The first one offers a significantly accelerated desaturation detection. The second one allows a full inverter to be protected by only one short-circuit detection circuit. Both approaches are verified by simulations and hardware tests.

This paper presents a high-temperature (HT) gate drive and protection circuit for Silicon-Carbide (SiC) power mosfets entirely built from commercial off-the-shelf HT discrete components. To estimate cost reduction, a brief comparison was made between the proposed circuit and a commercial circuit using silicon-on-insulator integrated circuits. To evaluate performance, power tests were conducted up to 180°C in a thermal chamber. Eventually, the proposed circuit achieved a 90% cost reduction, and all functions were validated by experiments at 180°C. This demonstrated that the proposed circuit is a cost-effective solution for contemporary HT applications.

In this paper, a novel matching circuit design method utilizing a genetic algorithm (GA) and the measured S-parameters of randomly moved coil configurations is discussed. Through the detailed comparison of different matching circuit topologies, the superiority of active matching circuits is clearly demonstrated, and potentially there is 21.4% improvement in the wireless power transfer efficiency by using a four-cell active matching circuit, which can create 16 different impedance values. Also, the matching circuit design simulation can be further simplified by choosing a much smaller subset of representative impedance values for the utilized time-changing coil configuration through the employment of $k$ -means clustering and use only these values for the derivation of the optimal matching circuit. This heuristic approach could drastically reduce the time for the matching circuit design simulation, especially for matching circuit topologies with a larger number of cells.

Thispaper presents a novel phase change memory (PCM) cell emulator circuit design created solely with off-the-shelf discrete electronic components. The designed emulator circuit reproduces PCM cell behavior in terms of temperature across the cell, threshold voltage, and programmed resistance levels in response to a given input. The presented circuit is designed and tested in simulation environment using LTSpice. The circuit was then built with CMOS 0.35m technology along with other off-the-shelf discrete components. The designed emulator circuit successfully generated the operational features of a PCM cell. The emulator circuit assessed the impact of the programming time, produced the standard I-V characteristics of a PCM element and retained the stored data throughout the duration of operation. Furthermore, the simulation and experimental results of the designed emulator circuit were found to be in close agreement with the experimental data obtained from an actual Ge2Sb2Te5 (GST) based PCM element.

A novel photonic integrated circuit architecture for implementing orthogonal frequency division multiplexing by means of photonic generation of phase-correlated sub-carriers is proposed. The circuit can also be used for implementing complex modulation, frequency up-conversion of the electrical signal to the optical domain and frequency multiplication. The principles of operation of the circuit are expounded using transmission matrices and the predictions of the analysis are verified by computer simulation using an industry-standard software tool. Non-ideal scenarios that may affect the correct function of the circuit are taken into consideration and quantified. The discussion of integration feasibility is illustrated by a photonic integrated circuit that has been fabricated using library' components and which features most of the elements of the proposed circuit architecture. The circuit is found to be practical and may be fabricated in any material platform that offers a linear electro-optic modulator such as organic or ferroelectric thin films hybridized with silicon photonics.

In this work, a new compact CMOS potentiostat circuit for electrochemical sensors is proposed. Integrated Potentiostats in CMOS technology are usually found in the literature designed with operational amplifiers performing both the electrochemical sensor bias and signal readout. In order to present alternative circuitry, a new potentiostat topology composed of a two-stage operational amplifier and a current conveyor circuit is proposed. The current conveyor is employed to perform the bias signal readout of an electrochemical cell with three electrodes. Simulations and experimental results of a discrete circuit version show that the proposed potentiostat topology yields results compliant with those of classical topologies presented in the literature.

The new 5G evolution will remarkably raise the design complexities in handsets and transmission networks. To fulfill the growing demand for high-speed data communication and for enabling the Internet of Things (IoT), a network with high data rates and bandwidth is required. The research is focused on the work to standardize the solutions for network challenges being faced due to high radio frequencies and to enable the highly advanced attributes. The significant amount of research in the Radio Frequency Integrated Circuit (RFIC) is being conducted as the size of an IC is being smaller and its power consumption is very low compared to a discrete circuit. The present study is focused on converting the discrete wireless transceiver circuit into a System on Chip (SOC), where all different components are integrated on to a single chip. The Power amplifier (PA) is a significant part of the wireless transceiver system and consumes a lot of power. Hence the power amplifier becomes an almost integral part of the wireless communication system to study and improve its overall efficiency. In this paper, we present an account of challenges and efficient architectures used for RFIC design suitable for 5G networks.

Electrochemical impedance spectroscopy (EIS) is a widely used method to characterize the biological materials. In traditional methods for EIS, a sinusoidal current is used to excite the material under test and the measured voltage across that material is demodulated by a linear multiplication with quadrature sinusoidal signals. From the resulting demodulated output, the impedance (magnitude and phase) can be calculated. Although this sine-wave-based impedance measurement method can produce accurate impedance measurements, it requires bulky components and suffers from poor power efficiency due to sinusoidal waveform generation and linear multiplication. Alternatively, a method using square-wave signal, which is simply a clock, for both excitation and demodulation can be much more area and power efficient, but inherently suffers from substantial errors in the result due to significant harmonics in square waves. In this paper, we propose a technique to cancel out the errors caused by such harmonics of the square-wave-based excitation and demodulation. The proposed technique, based on the fact that the magnitude ratio of all the harmonics of a square wave are known, cancels out harmonic errors by subtracting or adding the square-wave-based measured results at higher harmonic frequencies as a simple post-processing calculation. Simulations on specific and also generic impedance models demonstrate the applicability of this technique to various impedance models. Experimental results using a discrete circuit model show that this technique can provide a precise measurement of the impedance with 1% magnitude error and 0.5° phase error considering just five terms. In addition, measurements with a biological tissue show an average magnitude and phase error of 0.7% and [Formula: see text], respectively, using the proposed error cancellation. Because this method replaces sinusoidal signal generation and linear multiplication with clock generation and simple switching, it has great potential to be integrated in a wearable and implantable health monitoring device at low area and power consumption.

This work focuses on the integrated circuit design for CMOS-MEMS-based thermal-piezoresistive oscillators (TPOs). Conventional TPOs necessitate bulky discrete circuit components, which impedes integration and miniaturization of the microsystems. The proposed circuit implemented using TSMC $0.18\ \mu\mathrm{m}$ CMOS technology serves as sustaining amplifier and biasing circuit for our previously developed CMOS-MEMS thermal-piezoresistive resonators (TPRs), thus achieving TPOs with small form factor, targeted for mass/particle sensing applications. The previous version using commercial PCB electronics consumes 2.73 W while the proposed design greatly reduces the power consumption down to 15 mW. In addition, no harmonics have been found in oscillator output power spectrum while reaching 0 dBm (i.e., 1 mW). The far-from-carrier phase noise is demonstrated with −73.85 dBc/Hz and −80.06 dBc/Hz at 1 kHz and 100 kHz offsets respectively at a carrier frequency of 814.49 kHz in ambient pressure; as a result it is suitable for sensor applications. The miniaturized CMOS-MEMS TPO system features a frequency resolution of 65.9 Hz, thus corresponding to a mass resolution of 33.9 pg, which would potentially serve as aerosol (PM 2.5 ) sensors.

Bipolar junction transistors (BJTs) have been widely studied and used in nanosecond high-voltage pulse generators due to the advantages of fast switching speed and high repetitive frequency. Usually the Marx-type circuit is used to raise the peak value of output pulses. In this paper, a traditional BJT-Marx circuit using charging resistors is analyzed theoretically and experimentally. Based on the results, the structure of a circuit is changed to decrease the isolation voltage across the resistors, and diodes are used to replace charging resistors to block capacitors discharging to resistors. Experimental results showed that the three Marx generators proposed in this paper output pulses with higher voltage amplitude, and the last improved circuit outputs pulses with faster fall times at a higher efficiency.

This paper develops a behavioral electro-thermal model of GaN FETs in SPICE environment for power-electronic circuit simulation. The model couples an available GaN FET electrical model with a thermal RC network for junction temperature estimation, while using modification circuits between the gate driver and device to consider thermal impacts on device performance. Both static and switching characteristics of the developed model are compared with those from the original electrical model. To demonstrate the performance and functionality of the developed electro-thermal model in circuit simulation studies, it is implemented in a boost converter as a benchmark system. Finally, a Double Pulse Tester (DPT) circuit is built and the performance of the developed model is compared with experimental results.

In this paper, we propose two emulator circuits. Firstly, we present a novel memristor emulator based on operational transconductance amplifier (OTA) which is different from classical TiO2 memristor. This memristor emulator has a threshold switching mechanism. Secondly, we create a novel neuron circuit using proposed memristor, which is capable of generating spiking and bursting firing behaviors, with a biologically plausible spike shapes. The behavior of this neuron circuit can be adjusted by changing only one external biasing voltage. This neuron circuit mimics the behavior of cortical neurons, such as regular spiking (RS), intrinsic bursting (IB), chattering (CH) and fast spiking (FS). Proposed emulator circuits are compatible with VLSI systems and they can also be implemented by using discrete circuit components for different applications.

This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.

The need for dependable digital circuitry with the capability to operate reliably in high-temperature environments has been increasing drastically in applications such as automobile, aerospace, oil exploration, and power electronics. However, wide temperature swings significantly alter the threshold voltage of individual transistors, which adversely affects circuit timing in traditional synchronous designs. Such timing changes may in turn violates the setup and hold times of the clocked components, leading to potential circuit failure. This paper presents a complex digital integrated circuit design methodology using both synchronous and asynchronous logic for comparison in a young silicon carbide (SiC) design process developed by Raytheon UK. Seventeen circuits were designed, fabricated, and tested with results showing correct operation at temperatures at and above the target temperature of 300 °C.

A short circuit event is a basic and severe fault in power converters and other power electronic circuits. When the short circuit occurs, the surge current flowing through the semiconductor device ...

Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-aided design tools to extract circuit models for prebond and postbond TSVs. It is shown how the effects of common TSV parametric and catastrophic faults such as pinholes, voids, and open circuits affect TSV circuit models through 3-D full-wave simulations. It is also shown that the substrate conductivity has a considerable effect on the TSV fault characterization. The extracted models indicate that even a relatively large void does not alter the TSV characteristic parameters and thus voids remain largely undetected with conventional test solutions. An on-chip circuit, utilizing a delay-locked loop is presented as a test solution to detect TSV parametric faults.

Ability to supply more transistors per chip is outpacing improvements in cooling and power delivery. The result is operation that selectively powers on or off subsets of transistors. This paper suggests innovate ways to take advantage of the consequent “dark” silicon to meet a pair of additional emerging challenges—reliability and tolerance of variability.

For the time domain simulation of coupled systems, co-simulation is a prominent approach. The contraction and the speed of convergence of corresponding schemes depend on the design of the coupling interface and the computational order among others. Here, the field/circuit coupling is investigated, where the standard approach of decoupling is to separate the field and the circuit part. In this context, we introduce a new decoupling approach: $LR$ -coupling. For this coupling type, general stability and contraction are directly influenced by the coupling interface. Thus, these properties are independent of embedded electric networks or embedded electromagnetic devices. Furthermore, first investigations demonstrate that the use of a dedicated coupling interface may enhance the convergence properties, i.e., it may reduce the computational effort for prescribed tolerances.

The detection circuit presented in this paper has the purpose of detecting short circuit and open circuit faults in insulated gate devices (IGBT). The detection circuit design is based on the analysis of the IGBT gate signal VGE, which is characterized by carrying out the fault detection within the IGBT switching times under test. The fast fault detection is due to the following considerations: a) Employing technology components with a high slew rate, allows the detection within the switching times, b) Employing fewer components allow the circuit design less expensive and faster, and This paper presents the experimental validation results for the proposed fault detection cases.

Evaluation of novel devices in the context of circuits is crucial to identifying and maximizing their value. We propose a new framework, Pareto optimization-based circuit-level evaluator for emerging device (PROCEED), that uses comprehensive performance, power, and area metrics for accurate device-circuit coevaluation through optimization of digital circuit benchmarks. The PROCEED assesses technology suitability over a wide operating region (megahertz to gigahertz) by leveraging available circuit knobs (threshold voltage assignment, power management, sizing, and so on). It improves the benchmark accuracy by $3\times $ to $115\times $ compared with the existing methods while offering orders of magnitude improvements in runtime over full physical design implementation flows. To illustrate the PROCEED's capabilities, we deploy it to assess emerging technologies, including novel tunneling field-effect transistors, compared with conventional silicon CMOS. As a further illustration, we extend PROCEED to evaluate future heterogeneous integration of varied devices onto the same silicon substrate.