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The correct generator circuit breaker (GCB) dimensioning is essential for the safe and reliable operation of a power plant or generation system. The dimensioning is usually based on standardized calculation methods according to standards (IEC standard 60909‐0, IEC/IEEE standard 62271‐37‐013, IEEE Std C37), often supplemented by selected transient calculations. A non‐systematic approach can often be observed here, which does not adequately take into account significant influencing variables or operating states of the generator. This article therefore systematically examines various parameters that influence the short‐circuit current components of the generator and are relevant for the dimensioning of the generator circuit‐breaker: short‐circuit angle, operating point, impedance ratios, phase clearing, switching arc, and fault arc. The results of the current parameters most relevant to the dimensioning of the GCB were then compared for different calculation methods. Special attention was paid to the effect of the switching and fault arc, which were modelled as a constant arc voltage, and its effect on the short‐circuit currents is systematically recorded. This work aims to summarize all relevant variables that influence the generator short‐circuit current and are relevant for the dimensioning of the GCB and to present the different results based on a short‐circuit calculation according to the standard and transient calculation to create a basis for a proper dimensioning of the generator circuit breaker. [ABSTRACT FROM AUTHOR]

The logic structures implemented in Field Programmable Gate Arrays (FPGAs) are often critical and their correct operation is vital. FPGA devices are often used in areas where there is increased ionising radiation (space, medical diagnostics, aviation or nuclear power). There is therefore a need for mechanisms to correct radiation-induced errors. A common approach is the redundant implementation of particularly critical parts of the logic structure. By triplicating selected fragments, it is possible not only to detect potential errors but also to correct them. Such an approach is called triple modular redundancy (TMR), and its essence lies in the use of specialised voting circuits called voters, which allow the erroneous results of individual subcircuits to be eliminated by voting. The triplicate circuit under consideration, together with the voter, constitutes the mitigation structure. It becomes necessary to develop a test environment to assess the correct operation of these circuits. Also key is the efficiency of the implementation of these structures, which can be related to the occupation of logical resources or the power consumption of a given implementation. This paper demonstrates the essence of implementing a test environment to test the correctness of the mitigation of logic structures using TMR voters. An error injector mechanism using the Pseudo-Random Bit Sequence (PRBS) register is proposed, which introduces an element of randomness into the testing process. The aim of this research is to determine the implementation efficiency of the proposed test environment. In the experimental part, the implementation costs of the proposed solution were examined. The results indicate that between 66 and 109 LUT blocks were required to implement the error injector, corresponding to a relatively small increase in dynamic power consumption: by 22% for combinational circuits and by 37% for sequential circuits. [ABSTRACT FROM AUTHOR]

LLC resonant converters are widely adopted in many different industrial applications due to their high efficiency operation. To further improve LLC resonant converters' efficiency, the secondary unregulated diode rectifier is replaced by the synchronous rectifier (SR). In many applications, LLC converter is designed to operate at resonant frequency to maximize the system efficiency and act as a DC transformer (DCX). The SR driving signal is set as the same as the primary driving signal to work in an open‐loop mode. However, the resonant frequency will deviate due to the tolerance, working environment, and ageing effect of circuit components, which will lead to the degradation of the system efficiency and output voltage variation. Unfortunately, most of the existing techniques cannot be simply adopted in SR LLC DCX. Therefore, an adaptive SR driving strategy that can compensate the circuit components' variations is necessary for SR LLC DCX. Inan adaptive SR strategy based on the constant voltage gain characteristic at resonant frequency point is proposed. The proposed strategy is applicable for all different scenarios with easy implementation and low cost. [ABSTRACT FROM AUTHOR]

This article proposes a mini‐LED pixel circuit that employs the PWM driving method to decrease power consumption. To achieve uniform current, the circuit compensates for threshold voltage variations of TFTs and VDD I‐R drops. Simulation results show that power consumption is ameliorated over 10.53% more than the 6T1C circuit. [ABSTRACT FROM AUTHOR]

The new AMOLED pixel circuit for high‐resolution applications such as AR/VR has been proposed. The simultaneous emission is adopted to minimize pixel elements. The proposed circuit can compensate for variations of threshold voltage and sub‐threshold voltage even composed with 3 TFTs and 1 capacitor. [ABSTRACT FROM AUTHOR]

Technical advances in artificial manipulation of neural activity have precipitated a surge in studying the causal contribution of brain circuits to cognition and behavior. However, complexities of neural circuits challenge interpretation of experimental results, necessitating new theoretical frameworks for reasoning about causal effects. Here, we take a step in this direction, through the lens of recurrent neural networks trained to perform perceptual decisions. We show that understanding the dynamical system structure that underlies network solutions provides a precise account for the magnitude of behavioral effects due to perturbations. Our framework explains past empirical observations by clarifying the most sensitive features of behavior, and how complex circuits compensate and adapt to perturbations. In the process, we also identify strategies that can improve the interpretability of inactivation experiments. [ABSTRACT FROM AUTHOR]

Grover's algorithm has been widely used for quantum key search to attack block ciphers with a quadratic speedup as compared to classical brute-force attacks and also used for evaluating the post-quantum security of block ciphers against quantum computer attack. But, this quantum key search on block ciphers has a high quantum circuit depth and AES-128 is still secure against such attack. In this paper, we introduce a method called the depth–measurement trade-off method that reduces the overall quantum circuit depth of quantum key search to attack block ciphers by increasing the number of measurements of the circuit. This method is to introduce dummy keys in the quantum circuit as part of the correct key. This will reduce both quantum circuit resource and quantum circuit depth. Based on this technique, the quantum circuit depth of AES-128 is less than 2 64 , while NIST suggested circuit depth should be greater than MAXDEPTH, which is 2 40 , 2 64 and 2 96 in order to resist the respective attacks. In addition, we also simulated the depth–measurement trade-off method on the reduced SIMON block cipher algorithm as a proof of concept. Furthermore, we also apply the depth–measurement technique on various block ciphers, for example AES, PRESENT, SIMON, GIFT, SPECK, RECTANGLE, LowMC, KNOT, PIPO, etc. [ABSTRACT FROM AUTHOR]

Impaired extinction of fear memory is one of the most common symptoms in post‐traumatic stress disorder (PTSD), with limited therapeutic strategies due to the poor understanding of its underlying neural substrates. In this study, functional screening is performed and identified hyperactivity in the mediodorsal thalamic nucleus (MD) during fear extinction. Furthermore, the encoding patterns of the hyperactivated MD is investigated during persistent fear responses using multiple machine learning algorithms. The anterior cingulate cortex (ACC) is also identified as a functional downstream region of the MD that mediates the extinction of fear memory. The thalamocortical circuit is comprehensively analyzed and found that the MD‐ACC parvalbumin interneurons circuit is preferentially enhanced in PTSD mice, disrupting the local excitatory and inhibitory balance. It is found that decreased phosphorylation of the Kv3.2 channel contributed to the hyperactivated MD, primarily to the malfunctioning thalamocortical circuit. Using a lipid nanoparticle‐based RNA therapy strategy, channelopathy is corrected via a methoxylated siRNA targeting the protein phosphatase 6 catalytic subunit and restored fear memory extinction in PTSD mice. These findings highlight the function of the thalamocortical circuit in PTSD‐related impaired extinction of fear memory and provide therapeutic insights into Kv3.2‐targeted RNA therapy for PTSD. [ABSTRACT FROM AUTHOR]

In this letter, a novel design of electrically tunable substrate integrated waveguide (SIW) equalizer, based on PIN diodes, is proposed. Compared to previous SIW equalizers, this one introduces PIN diodes that exhibit varying impedance under different direct current (DC) voltages. The equalizing values of the SIW equalizer are directly linked to the DC voltage applied to the PIN diode within a specific voltage range. This feature allows it to be considered as an electrically tunable SIW equalizer. The experimental results demonstrate that the equalizing values are consistently monotonic and adjustable within the range of 1.59–7.56 dB in Ku‐band. This adjustment is attained through a DC voltage step of −0.01 V, applied within the range of 1.23–1.11 V. Additionally, the microwave equalizer is a planar structure that can be conveniently implemented on traditional printed circuit board, resulting in lower costs, easier realization, and integration. This SIW equalizer can be applied in amplitude compensation circuits and networks to compensate flatness dynamically. [ABSTRACT FROM AUTHOR]

Magnetoelectric (ME) sensors cannot effectively detect broadband magnetic field signals due to their narrow bandwidth, and existing readout circuits are unable to vary the bandwidth of the sensors. To expand the bandwidth, this paper introduces a negative-feedback readout circuit, fabricated by introducing a negative-feedback compensation circuit based on the direct readout circuit of the ME sensor. The negative-feedback compensation circuit contains a current amplifier, a feedback resistor, and a feedback coil. For this purpose, a Metglas/PVDF/Metglas ME sensor was prepared. Experimental measurements show that there is a six-fold difference between the maximum and minimum values of the ME voltage coefficients in the 6–39 kHz frequency band for the ME sensor without the negative-feedback compensation circuit when the sensor operates at the optimal bias magnetic field. However, the ME voltage coefficient in this band remains stable, at 900 V/T, after the charge amplification of the direct-reading circuit and the negative-feedback circuit. In addition, experimental results show that this negative-feedback readout circuit does not increase the equivalent magnetic noise of the sensor, with a noise level of 240 pT/√Hz in the frequency band lower than 25 kHz, 63 pT/√Hz around the resonance frequency of 30 kHz, and 620 pT/√Hz at 39 kHz. This paper proposes a negative-feedback readout circuit based on the direct readout circuit, which greatly increases the bandwidth of ME sensors and promotes the widespread application of ME sensors in the fields of broadband weak magnetic signal detection and DBS electrode positioning. [ABSTRACT FROM AUTHOR]

A fiber phase-sensitive optical time-domain reflectometer (a distributed acoustic sensor) with a low-noise output signal in the frequency range of 0.01−1 Hz is proposed for seismology applications. The sensor architecture is based on an unbalanced Mach−Zehnder interferometer, which is used to form a dual-pulse probe signal with required phases of its components and to stabilize the frequency of the laser source in the feedback circuit. The low noise level of the output signal is achieved in the proposed circuit by compensating for the difference in the optical paths of the dual-pulse probe signal fields scattered by different fiber sections. The applicability of the proposed circuit has been experimentally demonstrated by detecting a remote earthquake using a fiber-optic cable located at the bottom of the Black Sea. [ABSTRACT FROM AUTHOR]

This paper investigates the design and implementation of a new single‐phase sensorless power factor corrected (PFC) circuit. Here, the inductor‐current sensor and its sensing circuit are removed. As a result, the cost and volume of the PFC circuit are effectively reduced. Two different methods, including an inductor‐voltage estimation method and an inductor‐current estimation method, are proposed and compared. To improve the dynamic responses of the PFC circuit, predictive voltage control and predictive current control are implemented here. A digital signal processor, type TMS‐320F‐2808, manufactured by Texas Instruments, is used here as the control centre to execute the sensorless methods and control algorithms. A 400 W, 50 kHz switching frequency, single‐phase alternating current (AC) 110 V /DC 300 V PFC circuit is implemented. The measured results validate the feasibility and correctness of the proposed methods. This proposed sensorless PFC circuit can be widely applied in industry due to its simplicity. [ABSTRACT FROM AUTHOR]

In this paper, an AMOLED pixel circuit based on amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) compensating for variations in sub‐threshold swing (SS) and threshold voltage (VTH) of driving TFT is proposed. The proposed pixel circuit is composed of five TFTs and one capacitor. From the simulation results, when the SS and VTH shifts of the driving up to ±10% and ±1 V, the maximum OLED current error can be suppressed to 3.6% and 7.2%, respectively. [ABSTRACT FROM AUTHOR]

The Active Matrix Organic Light Emitting Diode (AMOLED) display causes the current deviation between pixels due to the dispersion based on device characteristics such as Threshold voltage (Vth) of Thin Film Transistors (TFT). This dispersion is compensated with pixel circuits inside the AMOLED panel, but the compensation time gradually decreases because of the performance improvement of AMOLED display such as high resolution and high‐speed driving, and as a result, it is difficult to solve the problem of the current deviation at low luminance which is using low current. The deviation of charging time for the capacitance of OLED (OLED Cap) by the current deviation based on device characteristic causes the light emission delay deviation, which in turn causes Mura on the panel. In this paper, we analyze the effect of the light emission delay deviation on Mura of AMOLED panel. [ABSTRACT FROM AUTHOR]

A pulse-width-modulation (PWM) pixel circuit for Micro-LED displays is proposed based on low-temperature poly-silicon and oxide (LTPO) thin-film transistors (TFTs). The pixel circuit features fast PWM transition, as the PWM falling-time is less than 20 μs thanks to the high-gain dynamic inverter. Furthermore, the proposed pixel circuit can compensate the degradation and non- uniformities of TFT characteristics of LTPO TFTs through auto- zeroing configuration of the dynamic inverter and a diode- connected threshold voltage compensation structure. The error rate of luminous time is less than 3.2% and the error rate of current is less than 1% under VTH shift of oxide TFT ±2 V or LTPS TFT ±1 V. [ABSTRACT FROM AUTHOR]

In recent years, the active-matrix organic light-emitting diode (AMOLED) displays have been greatly required. A voltage compensation pixel circuit based on an amorphous indium gallium zinc oxide thin-film transistor is presented for AMOLED displays. The circuit is composed of five transistors–two capacitors (5T2C) in combination with an OLED. In the circuit, the threshold voltages of both the transistor and the OLED are extracted simultaneously in the threshold voltage extraction stage, and the mobility-related discharge voltage is generated in the data input stage. The circuit not only can compensate the electrical characteristics variation, i.e., the threshold voltage variation and mobility variation, but also can compensate the OLED degradation. Furthermore, the circuit can prevent the OLED flicker, and can achieve the wide data voltage range. The circuit simulation results show that the OLED current error rates (CERs) are lower than 3.89% when the transistor's threshold voltage variation is ±0.5V, lower than 3.49% when the mobility variation is ±30%. [ABSTRACT FROM AUTHOR]

In this paper, a low dropout (LDO) circuit based on a curvature compensation benchmark and closed-loop stability is designed. This circuit compensates for the higher order term of VBE in a BJT through the subthreshold characteristic of MOSFET and achieves the effect of curvature compensation. The bandgap reference circuit provides a stable input voltage for the LDO circuit, while the source follower and adaptive bias circuit improve the response speed and closed-loop stability of the LDO circuit. The temperature drift coefficient of the bandgap circuit is 8.11 ppm/°C, the input voltage is 3–5 V, the output voltage is 2.8 V, and the linear adjustment rate is 0.22%. [ABSTRACT FROM AUTHOR]

A completely distributive complete lattice is called a molecular lattice. It is well known that the category TML of all topological molecular lattices with generalized order homomorphisms in the sense of Wang, is both complete and cocomplete. In this note, we give an example which shows that the structure of equalizers introduced by Zhao need not be true, in general. In particular, we present the structures of equalizers, coequalizers, monomorphisms and epimorphisms in this category. [ABSTRACT FROM AUTHOR]

The object of the study is a three-phase shunt active power filter, which consists of a two-level voltage inverter, a capacitive storage device and a damping RL-link. Decomposition of the object of study according to the rate of motion of a dynamic system makes it possible to divide this system into two subsystems, interconnected by control. The influence of the dynamic characteristics of the low-pass filter, which acts as a subsystem of communication between the voltage stabilization circuit on the capacitor of the three-phase shunt active power filter and the circuits of compensating current, on the stability of the system is considered. The formation of the compensation current is carried out by forcing the introduction of sliding modes of the first order. The mathematical model of the voltage stabilization subsystem on the capacitor using the vector of the equivalent control under the assumption of the existence of a sliding mode in the formation of the compensation current was built. The analysis of the stability of the voltage stabilization system using a low-pass filter of the second order on the first approximation was performed. To do this, the characteristic equation of a closed system for which an interval characteristic polynomial was constructed, the Kharitonov theorem, and the Rauss-Hurwitz method for a family of these polynomials was used. To confirm the theoretical assumptions, a simulation model was built and the results of digital modeling were analyzed. [ABSTRACT FROM AUTHOR]

In this paper, an architecture of an electrical equivalence pyranometer with analog control of the temperature difference is presented. The classical electrical equivalence pyranometer employs a Wheatstone bridge with a feedback amplifier to keep the sensor operating at a constant temperature to estimate the incident radiation through the sensor thermal balance employing the electrical equivalence principal. However, this architecture presents limitations under ambient temperature variation, such as sensitivity variation. To overcome those limitations, we propose an architecture that controls the temperature difference between the sensor and ambient via an analog compensating circuit. Analytical results show an improvement near five times in sensitivity over the ambient temperature span and 76.3% increase of useful output voltage. A prototype was developed and validated with a commercial pyranometer, showing a high agreement on the measurement results. It is verified that the use of temperature difference, rather than constant temperature, significantly reduces the effect of ambient temperature variation. [ABSTRACT FROM AUTHOR]

Using multi-valued circuits reduce the number of connections on a chip and the area of the chip and power consumption in the connections.. In this paper, a new structure of single-source logic gates, AND, OR and BUFFER were designed using CNFET. In the new design, AND and OR have directly been designed instead of NAND and NOR, because in previous designs, NAND and NOR were needed to achieve AND and OR. Also, due to the fact that PT, NT inverters and positive, negative logic gates have been used, it is possible to adjust the voltage of the switch to achieve a better noise margin. Also, with the proposed ternary BUFFER, a single-source ternary memory cell was designed, with the advantages of a smaller number of transistors and the need for only a single line for reading and writing, which greatly reduces the number of interconnections. Since the number of interconnections in the memory array increases tremendously, this design significantly reduces the number of connections in the memory array. The simulation results using Hspice software and the Stanford CNT-32 nm model indicate the correct operation of the circuits and represent the improved 70% and 90% in PDP of gates compared with the state-of-art work. [ABSTRACT FROM AUTHOR]

Purpose. Justification of technical solutions as to the reduction of the amplitude and reduction of the dynamic change duration in the tension of the rolling stock at the exit of the output cage when moving to winding a new layer to an acceptable level in terms of its effect on the resulting profile of the rolled product through the control of the rotation frequency of an output cage. Methodology. The conducted research was based on a complex model of the process of rolled steel winding with a Garrett-type winder and the tension of rolled steel in the area of the exit cage-winder. To control the actual amount of tension at the output cage exit, it is suggested to use the amount of free deflection of the rolled steel directly behind the cage. The research was carried out by simulating the process of rolled steel winding according to the basic control scheme and control schemes that predict the influence on both drives, i.e. the winder drive and the output cage drive according to the actual value of tension, in various combinations with further analysis and comparison of the obtained results. Findings. It was established that the correction for the deviation of the actual rolling tension in the finishing cage-winder area from the specified value of the winding current of the winder electric drive does not eliminate rolling tension when switching to the next layer winding and the oscillating form of the transition process, which are characteristic of the basic rolling winding scheme. In turn, the correction of the rotation frequency of the output cage rolls drive reduces the amplitude of the roll tension jerk by almost half with a simultaneous reduction in the time of the transition process and readjustment when switching to a new layer winding. Originality. It has been shown for the first time that the introduction of the roll tension control circuit by correcting the highspeed rolling mode of the output cage ensures minimization of dynamic changes in the rolled steel tension when switching to a new layer winding and reduces the probability of local tightening of rolled steel profile. Practical value. The use of the described technical solutions in the control system of the section of rolled products winding of the small-grade wire mill DSDS 250/150-6 PJSC “ArcelorMittal Kryvyi Rih” ensures the improvement of the commercial properties of the winding of rolled products produced on the rolling mill. [ABSTRACT FROM AUTHOR]

Neuromorphic computing has gained a considerable research interest due to its potential in realizing highly efficient parallel computations. However, the existing neuromorphic architectures face various drawbacks. In this study, we present an integrate-and-fire (I&F) neuron using a Li-based electrochemical random access memory (Li-ECRAM) to achieve exceptional area efficiency and low-power neuromorphic computing. The proposed Li-ECRAM neuron employs a significantly reduced number of transistors when compared to other novel nonvolatile memory-based I&F neurons due to linear current integration characteristics and a high linear conductance response to the input current. As the integration-type Li-ECRAM is linear, it eliminates the requirement of a nonlinear compensating circuit. Therefore, a Li-ECRAM-based neuron has a simple structure comprising Li-ECRAM, reset transistor, inverter, and pulse generator. Furthermore, we also evaluate the operation speed and energy consumption of the proposed neuron, demonstrating the potential for high-speed and low-power operation. The proposed neuron can be applied in large-scale neuromorphic hardware applications due to the scalability and low energy consumption of Li-ECRAM. [ABSTRACT FROM AUTHOR]

After they reached the end of their useful EV life, lithium-ion batteries are still satisfactory for second life (SL) energy storage applications. However, the spread in their SL cell capacities may be much wider than in the EV, and this raises a question as to what type of cell voltage equalizer (EQU) should be used. Most users plan to retain the same passive EQU (PEQ) from the EV, but this means the battery capacity will be the same as the worst cell in the battery, just as it was in the EV. Unfortunately, the SL cell capacity spread may be much wider than it was in the EV, and if so, most of the cells will be under-utilized. This can be corrected by using an active EQU (AEQ) or a hybrid, such as the bilevel EQU (BEQ), to provide a capacity close to the cell average; but first, measured data is needed on the actual size of the cell capacity spread. To simplify and reduce the cost of these measurements, a new method is proposed that provides the capacities of the worst cell and the cell average. [ABSTRACT FROM AUTHOR]

The Triple-Modular Redundancy (TMR) technique is one of the conventional approaches to provide reliable functioning of logic circuits. When using outsourcing, it is possible to inject a Trojan Circuit (TC) in the same line of each identical TMR module, and the TMR technique becomes vulnerable. It is necessary to withstand to vulnerability. One way of solving this problem is the application of two approximate logic circuits and one correct circuit that implements the proper functioning in the frame of the TMR technique. However, this approach, as a rule, generates an unprotected area in which a fault of one of the three circuits may be undetected. It is desirable to minimize this area. In this paper, approximate circuits are built based on deriving approximate systems of Boolean functions. These systems are then applied for an approximate circuit synthesis. The approach gives additional possibilities for cutting the unprotected area compared to the methods suggested before. Algorithms of deriving the approximate systems of the Boolean functions based on analysis of an irredundant system of sums of products (SoPs) describing the behavior of the correct circuit have been developed. The algorithm appreciating the size of the unprotected area is also given. [ABSTRACT FROM AUTHOR]

In this paper, a new high-gain operational transconductance amplifier (OTA) circuit is designed. The proposed circuit uses bulk-driven technique to reduce the required supply voltage while gain-boosting as well as positive feedback techniques are used to increase the gain of the circuit and compensate the gain reduction effect due to the use of bulk-driven transistors. The performance of the proposed circuit is simulated using 180-nm CMOS technology parameters and is optimized using an optimization algorithm for the main purpose of minimizing the power consumption of the circuit. Simulated performance of the proposed circuit for 1.2 V DC supply voltage shows 94.8 dB gain, 203-MHz bandwidth, and slew-rate of 365-V/µS while occupying die area of 1360 µm2. However, the proposed circuit is also designed for a low-voltage scenario with 0.75 V DC supply voltage that results in 73.7 dB gain, 131-MHz bandwidth, and slew-rate of 149-V/µS. [ABSTRACT FROM AUTHOR]

A broadband GaN MMIC power amplifier (PA) with compact dimensions of 1.94 × 0.83 mm2 is presented for 5G millimeter-wave communication. To guarantee output capability at the operating band edges where serious performance degradation is likely to occur, the appropriate large-signal matching model and optimal impedance domain need to be carefully determined through load-pull analysis. Broadband matching networks (MNs) in the lowpass form are thereafter developed based on the Chebyshev filter synthesis theory. Using high-pass interstage MN in conjunction with parallel RC lossy circuits to compensate for the transistor's negative gain roll-off slope ensures a flat frequency response. The input MN is designed as a band-pass filter due to the reactance extracted from the input side of the stabilized device exhibiting series LC resonance characteristics. Measured on-wafer pulsed results for the proposed three-stage PA demonstrate up to 30.9 dBm of output power, more than 28.6 dB of small-signal gain, and a peak power-added efficiency (PAE) of 35.6% at 27 GHz. Both uniform gain and saturated output power (Psat) are achieved across 24–30 GHz with fluctuations of less than 0.8 dB. [ABSTRACT FROM AUTHOR]

Gate sizing and buffer insertion for timing optimization are performed extensively in electronic design automation (EDA) flows. Both of them aim to adjust the upstream and downstream capacitances of gates/buffers to minimize delay. However, most of existing work focuses on gate sizing or buffer insertion independently. This paper proposes a learning-based timing optimization framework, AiTO, that combines reinforcement learning with graph neural network, to perform simultaneously gate sizing and buffer insertion. We model buffer insertion as a special gate sizing by determining possible buffer locations in advance and treating the buffer insertion and gate sizing as an RL process. Experimental results on 10 real designs (28-nm and 110-nm) show that, AiTO can achieve better worst negative slack (WNS) optimization results than OpenROAD while being able to improve the results of the commercial tool, Innovus, to some extent. Moreover, ablation studies demonstrate the benefits of performing simultaneous gate sizing and buffer insertion for timing optimization. • Simultaneous gate sizing and buffer insertion are performed for timing optimization. • Graph edit operations are defined to perform gate sizing and buffer insertion. • Maintains correct circuit functionality and ensures that timing does not deteriorate. [ABSTRACT FROM AUTHOR]

Faced with the increasing prevalence of chronic kidney disease (CKD), portable monitoring of CKD-related biomarkers such as potassium ion (K+), creatinine (Cre), and lactic acid (Lac) levels in sweat has shown tremendous potential for early diagnosis. However, a rapidly manufacturable portable device integrating multiple CKD-related biomarker sensors for ease of sweat testing use has yet to be reported. Here, a portable electrochemical sensor integrated with multifunctional laser-induced graphene (LIG) circuits and laser-printed nanomaterials based working electrodes fabricated by fully automatic laser manufacturing is proposed for non-invasive human kidney function monitoring. The sensor comprises a two-electrode LIG circuit for K+ sensing, a three-electrode LIG circuit with a Kelvin compensating connection for Cre and Lac sensing, and a printed circuit board based portable electrochemical workstation. The working electrodes containing Cu and Cu 2 O nanoparticles fabricated by two-step laser printing show good sensitivity and selectivity toward Cre and Lac sensing. The sensor circuits are fabricated by generating a hydrophilic-hydrophobic interface on a patterned LIG through laser. This sensor recruited rapid laser manufacturing and integrated with multifunctional LIG circuits and laser-printed nanomaterials based working electrodes, which is a potential kidney function monitoring solution for healthy people and kidney disease patients. [ABSTRACT FROM AUTHOR]

Of crucial importance is to accurately simulate its switching characteristics for the application of SiC MOSFET. Due to the ultrafast switching capability, SiC MOSFET is dependent on interelectrode capacitances and extremely sensitive to parasitics. Therefore, accurate modelling of interelectrode capacitances and knowledge of parasitics are required. Here, an improved SiC MOSFET model driven by an empirical formula with three segments for the non‐linear drain‐to‐gate capacitance in relationship with the drain‐to‐source voltage is developed. In this way, the capacitance fitting at the inflection point that has a great impact on the switching delay is much improved. By simple self‐made high‐voltage C–V measurement systems, the accuracy of the proposed formula is verified. More importantly, intruded parasitics by the commonly‐used coaxial shunt current measurement loop is analysed in detail. The equivalent circuit of the current measurement loop is incorporated into the device simulation circuit to compensate measurement errors. In this way, the improved model can be more reliably verified and evaluated. A double pulse test is built to verify the proposed model. By comparison of simulation and experimental results, the proposed model works well at different voltage and current operating conditions and offers a reliable and accurate modelling approach. [ABSTRACT FROM AUTHOR]

This paper proposes a new amorphous indium gallium zinc oxide (a‐IGZO) pixel circuit for the simultaneous emission active‐matrix organic light‐emitting diode (AMOLED) displays, which can compensate for the non‐uniform threshold voltage (VTH) and mobility (μ) of the thin‐film transistor (TFT). The Negative VTH are successfully compensated by adopting the source follower method, and then mobility compensation is carried out by additional voltage adjustment. The OLED current error rate is within 9 % against the VTH and mobility variations in the simulation. [ABSTRACT FROM AUTHOR]

This article reviews existing capacitive power transfer (CPT) systems and aims to provide a universal methodology to systematically construct CPT topologies with zero-phase angle (ZPA) and load-independent output property. There are three contributions. First, y, z, g, and h parameters of a two-port network are adopted to model the capacitive coupler for four basic CPT compensations, which facilitates the resonant circuit analysis by forming parallel or series LC resonance. Second, four basic CPT compensations, series–series (SS), series–parallel (SP), parallel–series, and parallel–parallel (PP), are developed and analyzed. ZPA frequencies are identified with a load-independent output, and a unified efficiency analysis is also provided. Third, by selectively deploying high-order T/Π-type LCL/CLC networks and the SS mutual inductance with basic CPT compensations, a universal CPT design methodology is provided. In total, 144 feasible CPT topologies are derived with ZPA property and constant-current (CC) or constant-voltage output, which not only summaries existing ones but also predicts new topologies. Considerations are provided to guide the topology selection, from which ten typical CPT topologies are elaborated and recommended. A 500-W LCL–PP–LCL compensated CPT circuit is implemented. Experiments validate the proposed methodology by a ZPA property and a load-independent CC output, and a peak dc–dc efficiency of 87.76% is also achieved at 478 W. [ABSTRACT FROM AUTHOR]

This article proposes an analytical circuit model extraction technique for extracted-pole filters with nonresonant nodes (NRNs). The circuit model is described by a generalized coupling matrix incorporating both resonant nodes and NRNs. It is shown that, in most cases, Y-parameter polynomials of extracted-pole filters with NRNs take the same form as those of coupled-resonator filters. Thus, the model-based vector fitting technique can be applied to obtain legitimate rational function approximation to measured or simulated S-parameter data, and then, a circuit model in the correct form can be synthesized accordingly. This article discusses different possible arrangements of extracted-pole sections to develop a general solution to the circuit model extraction problem. It also defines a standard circuit form to rule out multiple solutions in the circuit model extraction problem for guiding the computer-aided design and tuning process. A combline filter design and a waveguide filter tuning example are presented to demonstrate the application of the circuit model extraction technique. These examples show that simple mapping relationships exist between extracted circuit parameters and physical elements. Thus, accurate dimensioning of extracted-pole filters can be accomplished without electromagnetic optimization in the design phase. Filter fine-tuning can be done by inexperienced operators or an automatic tuning machine with the circuit model extraction technique. [ABSTRACT FROM AUTHOR]

This study presents a novel multilayer structure of parallel coupled‐line bandpass filtercentered at 2.42 GHz with a fractional bandwidth value of approximately 19.4%. The designed filter can suppress harmonics with an appropriate frequency response by incorporating different techniques based on the multilayer technique. A combination of different techniques such as radial microstrip stubs and defected ground structure (DGS) and defected microstrip structure techniques are employed to suppress harmonics up to 5f0. These techniques are used in two layers to suppress up to 5f0. In addition, in this study, the effects of different parameters, such as the width of slot‐line DGS, the angle of diagonal line slots in the upper layer, and the air gap between the two layers on the filter performance, are investigated. To verify the correct circuit operation, the designed filter is implemented and tested. The measurement results of the proposed filter are compared with the simulation results. [ABSTRACT FROM AUTHOR]

Few practical products of synchronous rectification (SR) in the automotive alternator has been reported, though the driving technology of SR is abundant. Continuously and statistically changing switch frequency caused by rotor speed poses a significant challenge to the driving circuit design under the specified application area. In this article, a directly frequency tracking (D-FT) method is first proposed to ensure the switching tube's safe conduction time adapted to the rotor speed, making the SR immune to circuit oscillation or spurious ringing. The proposed self-driven circuit generates correct gate driving signals requiring no additional sensing circuits or sensors for detecting rotor speed. A hardware algorithm based on the D-FT method is built, which is convenient to implement to other kind of alternators and systems. This method is verified by prototype simulation and practical tests under the alternator test bench. A six-phase full bridge is trial-manufactured after the driver chip's tape out and performs well under 0–150 A output current and 0–18 000 r/min rotor speed. The test results show that the Verband der Automobilindustrie standard efficiency of the proposed rectifier obtains an 8% improvement compared to that of the conventional diode rectifier. [ABSTRACT FROM AUTHOR]

A new flipped voltage follower (FVF) whose current source is realized by a depletion-mode thin-film transistor is proposed. It is successfully applied to a static voltage-programmed pixel circuit. The new FVF has good adjustable self-compensation (ASC) ability, which makes the pixel circuit can compensate for different threshold-voltage shifts of thin-film transistors in not only the driving but also the FVF circuits. The simulation results show that the proposed pixel circuit exhibits a tiny current variation ranging from 1.69% to 3.80% when “global” transistors shift by ±0.2 V or ±0.3 V. In the experiment, the excellent ASC ability of the new FVF is verified by measuring the voltage transfer curve under ultraviolet exposure. Finally, the proposed pixel circuit exhibits a current variation of 1.4% after a stress time of 40000 s. [ABSTRACT FROM AUTHOR]

High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the BE transforms the bubble free code into binary code. A Tanner EDA with 250-nm Technology is used to implement the C-FADC. The proposed design achieves ENOB of 3.56, uses 3.24 mW of power, and has a FOM of 0.274pJ/conv.-step at an input frequency of 85 MHz. The suggested C-FADC has differential and integral nonlinearities of ±0.65 LSB and +0.45/-0.5 LSB, respectively. [ABSTRACT FROM AUTHOR]

Extraordinary progress has been made during the past few decades in the development of anesthesia machines and ventilation techniques. With unprecedented precision and performance, modern machines for pediatric anesthesia can deliver appropriate mechanical ventilation for children and infants of all sizes and with ongoing respiratory diseases, ensuring very small volume delivery and compensating for circuit compliance. Along with highly accurate monitoring of the delivered ventilation, modern ventilators for pediatric anesthesia also have a broad choice of ventilation modalities, including synchronized and assisted ventilation modes, which were initially conceived for ventilation weaning in the intensive care setting. Despite these technical advances, there is still room for improvement in pediatric mechanical ventilation. There is a growing effort to minimize the harm of intraoperative mechanical ventilation of children by adopting the protective ventilation strategies that were previously employed only for prolonged mechanical ventilation. More than ever, the pediatric anesthesiologist should now recognize that positive‐pressure ventilation is potentially a harmful procedure, even in healthy children, as it can contribute to both ventilator‐induced lung injury and ventilator‐induced diaphragmatic dysfunction. Therefore, careful choice of the ventilation modality and its parameters is of paramount importance to optimize gas exchange and to protect the lungs from injury during general anesthesia. The present report reviews the novel ventilation techniques used for children, discussing the advantages and pitfalls of the ventilation modalities available in modern anesthesia machines, as well as innovative ventilation modes currently under development or research. Several innovative strategies and devices are discussed. These novel modalities are likely to become part of the armamentarium of the pediatric anesthesiologist in the near future and are particularly relevant for challenging ventilation scenarios. [ABSTRACT FROM AUTHOR]

The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, NAND, and NOR gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits. [ABSTRACT FROM AUTHOR]

The beginning of the Covid‐19 pandemic was far from the 'great equalizer' sometimes described by the media. This article shares themes emerging from research conducted in 2020 in France, Italy and the USA concerning responses to the pandemic and its social effects. The authors analyze how the pandemic elicited varied reactions within the three countries where they conducted anthropological fieldwork. They propose that narratives of the Covid‐19 response can shed light on how individuals navigate social and political relationships in each context. [ABSTRACT FROM AUTHOR]

The low-power chips are occurring test challenges on chip's shmoo test on yield and performance degradation. A method for improving the performance-yield from adjusting the clock edge is presented. This work proposes a clock-edge adjusted circuit (CAC) to adjust the duty-cycle for testing multi-Vdd and multi-Vth circuits. Instead of adopting a phase-lock-loop to generate a clock with different frequencies, by external ATE cannot adjust chip-internal clock-frequency after a chip is manufactured. However, by using the proposed CAC circuit, the chip duty cycle can be trimmed. The proposed CAC generates an adjustable wide-range trigger-edge signal for the DUT chip, the duty cycles of the clock with a fixed frequency are adjusted to emulate a fast/slow chip-clock frequency. CAC can quickly push the circuit toward correct functional operation under at-speed shmoo-binning operations. It is an efficient with low-area overhead design-for–test circuit to support multi-Vdd/Vth complex designed chips. The CAC technique jointed with using Agilent-93000 automatic-test-equipment (ATE) is used to validate a four multi-Vdd/Vth Cortex-M0 processors chip. The measurements demonstrate yield improvement and accurate performance evaluation from using the CAC by ATE. [ABSTRACT FROM AUTHOR]

A liquid attenuator with multi‐aperture coupling is proposed. It consists of two coupled rectangular waveguide cavities, two transparent containers and pure water. By utilising the multi‐aperture coupling structure, the proposed design achieves large attenuation with good flatness across a wide frequency range. The pure water is employed as the liquid loading to dissipate the energy. Both simulations and measurements have been conducted. It is demonstrated that the proposed attenuator exhibits an attenuation of 59.2 dB with an attenuation flatness of ±0.9 dB from 2.19 to 3.64 GHz (the reflection coefficient is less than −10 dB across the band). Compared with conventional waveguide attenuators, this design provides a wider frequency working range, a more compact size, larger and flatter attenuation and better heat dissipation. It can be a promising candidate for high power applications. [ABSTRACT FROM AUTHOR]

Featured Application: Interface low-voltage battery packs with medium-voltage or high-voltage DC buses, e.g., DC buses in microgrids or electric vehicles. Devices connected to microgrids require safe conditions during their connection, disconnection and operation. The required safety is achieved through the design and control of the converters that interface elements with the microgrid. Therefore, the design of both power and control stages of a battery charger/discharger based on a flyback is proposed in this paper. First, the structure of a battery charger/discharger is proposed, including the battery, the flyback, the DC bus, and the control scheme. Then, three models to represent the battery charger/discharger are developed in this work; a switched model, an averaged model, and a steady-state model, which are used to obtain the static and dynamic behavior of the system, and also to obtain the design equations. Based on those models, a sliding-mode controller is designed, which includes the adaptive calculation of one parameter. Subsequently, a procedure to select the flyback HFT, the output capacitor, and the K v parameter based on operation requirements of the battery charger/discharger is presented in detail. Five tests developed in PSIM demonstrate the global stability of the system, the correct design of the circuit and controller parameters, the satisfactory regulation of the bus voltage, and the correct operation of the system for charge, discharge and stand-by conditions. Furthermore, a contrast with a classical PI structure confirms the performance of the proposed sliding-mode controller. [ABSTRACT FROM AUTHOR]

In ultracold-atom and ion experiments, flexible control of the direction and amplitude of a uniform magnetic field is necessary. It is achieved almost exclusively by controlling the current flowing through coils surrounding the experimental chamber. Here, we present the design and characterization of a modular, analog electronic circuit that enables three-dimensional control of a magnetic field via the amplitude and direction of a current flowing through three perpendicular pairs of coils. Each pair is controlled by one module, and we are able to continuously change the current flowing thorough the coils in the ±4 A range using analog waveforms such that smooth crossing through zero as the current's direction changes is possible. With the electrical current stability at the 10 − 5 level, the designed circuit enables state-of-the-art ultracold experiments. As a benchmark, we use the circuit to compensate stray magnetic fields that hinder efficient sub-Doppler cooling of alkali atoms in gray molasses. We demonstrate how such compensation can be achieved without actually measuring the stray fields present, thus speeding up the process of optimization of various laser cooling stages. [ABSTRACT FROM AUTHOR]