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Background It is unclear to which extent persistence of symptoms and/or residual haemodynamic impairment clinical course of pulmonary embolism are associated with worse quality of life (QoL). Aims To study the correlation between symptoms and haemodynamic impairment with QoL during the first year after acute pulmonary embolism (PE). Methods The Follow-Up after acute pulmonary embolism (FOCUS) study prospectively enrolled and followed consecutive adult patients diagnosed with acute symptomatic objectively diagnosed PE. In the present analysis, we considered patients who completed the Pulmonary Embolism QoL (PEmb-QoL) Questionnaire at predefined visits 3 and 12 months after acute PE. The PEmb-QoL score ranges from 0% (best QoL) to 100% (worst QoL). We evaluated at these two time points the correlation between persisting symptoms (group: symptoms), elevation of natriuretic peptides or residual right ventricular dysfunction (group: RVD), or their combination (group: symptoms + RVD) and QoL. Results A total of 617 patients were included; their median age was 62 years, 44% were women; 8% had active cancer, and 21% previous venous thromboembolism. At 3 months, patients with neither symptoms nor RVD (n=302) had the highest quality of life (median score 18%, 25th–75th percentile: 8%–34%), followed by those without symptoms but with RVD (n=255; median score 19%, 25th–75th percentile: 7%–34%), and by those with symptoms only (n=131; median PEmb-QoL 31%, 25th–75th percentile: 18%–49%). Patients with both symptoms and RVD (n=170) had the worst quality of life (median score 38%, 25th–75th percentile: 19%–53%); Figure 1A. At 12 months, we found an overall improvement of PEmb-QoL score. The degree of this QoL improvement varied across groups, being largest for patients who recovered from having symptoms + RVD at 3 months to normalization of at least one at 12 months. The change in QoL from 3 to 12 months was smaller both in patients who had neither symptoms nor RVD and in patients who had no recovery in either symptoms or RVD; Figure 1B. Conclusions Persistent symptoms after PE, especially in patients with elevated biomarkers or residual echocardiographic dysfunction, were the main drivers of QoL at 3 months as well as of the course of QoL over time. Figure 1 Funding Acknowledgement Type of funding source: Public grant(s) – National budget only. Main funding source(s): University Medical Center of the Johannes Gutenberg University, Mainz, Germany; German Federal Ministry of Education and Research

We synthesize findings from one of the world’s largest and longest-running experimental investigations, the Biological Dynamics of Forest Fragments Project (BDFFP). Spanning an area of ~1,000 km2 in central Amazonia, the BDFFP was initially designed to evaluate the effects of fragment area on rainforest biodiversity and ecological processes. However, over its 38-year history to date the project has far transcended its original mission, and now focuses more broadly on landscape dynamics, forest regeneration, regional- and global-change phenomena, and their potential interactions and implications for Amazonian forest \ud conservation. The project has yielded a wealth of insights into the ecological and environmental changes in fragmented forests. For instance, many rainforest species are naturally rare and hence are either missing entirely from many fragments or so sparsely represented as to have little chance of long-term survival. Additionally, edge effects are a prominent driver of fragment dynamics, strongly affecting forest microclimate, tree mortality, carbon storage and a diversity of fauna. \ud Even within our controlled study area, the landscape has been highly dynamic: for example, the matrix of vegetation surrounding fragments has changed markedly over time, succeeding from large cattle pastures or forest clearcuts to secondary regrowth forest. This, in turn, has influenced the dynamics of plant and animal communities and their trajectories of change over time. In general, fauna and flora have responded differently to fragmentation: the most locally extinction-prone animal species are those that have both large area requirements and low tolerance of the modified habitats surrounding fragments, whereas the most\ud vulnerable plants are those that respond poorly to edge effects or chronic forest disturbances, and that rely on vulnerable animals for seed dispersal or pollination.\ud Relative to intact forests, most fragments are hyperdynamic, with unstable or fluctuating populations of species in response to a variety of external vicissitudes. Rare weather events such as droughts, windstorms and floods have had strong impacts on fragments and left lasting legacies of change. Both forest fragments and the intact forests in our study area appear to be influenced by larger-scale environmental drivers operating at regional or global scales. These drivers are apparently increasing forest productivity and have led to concerted, widespread increases in forest dynamics and plant growth, shifts in tree-community composition, and increases in liana (woody vine) abundance. Such large-scale drivers are likely to interact synergistically with habitat fragmentation, exacerbating its effects for some species and ecological phenomena. Hence, the impacts of fragmentation on \ud Amazonian biodiversity and ecosystem processes appear to be a consequence not only of local site features but also of broader changes occurring at landscape, regional and even global scales.

Objectives Ceftaroline (active form of the prodrug ceftaroline fosamil) is a novel cephalosporin with activity against pathogens commonly associated with community-acquired pneumonia (CAP), including Streptococcus pneumoniae and Gram-negative pathogens. This randomized, double-blind, Phase III study evaluated the efficacy and safety of ceftaroline fosamil in treating patients with CAP. The primary objective was to determine non-inferiority [lower limit of 95% confidence interval (CI) ≥ -10%] of clinical cure rates achieved with ceftaroline fosamil compared with those achieved with ceftriaxone in the clinically evaluable (CE) and modified intent-to-treat efficacy (MITTE) populations. Methods Patients hospitalized in a non-intensive care unit setting with CAP of Pneumonia Outcomes Research Team (PORT) risk class III or IV requiring intravenous (iv) therapy were randomized (1:1) to receive 600 mg of ceftaroline fosamil iv every 12 h or 1 g of ceftriaxone iv every 24 h. Clinical cure, microbiological response, adverse events (AEs) and laboratory tests were assessed. FOCUS 2 registration number NCT00509106 (http://clinicaltrials.gov/ct2/show/NCT00509106). Results The study enrolled 627 patients, 315 of whom received ceftaroline fosamil and 307 of whom received ceftriaxone. Patients in both treatment groups had comparable baseline characteristics. Clinical cure rates were as follows: CE population, 82.1% (193/235) for ceftaroline fosamil and 77.2% (166/215) for ceftriaxone [difference (95% CI), 4.9% (-2.5, 12.5)]; and MITTE population, 81.3% (235/289) for ceftaroline fosamil and 75.5% (206/273) for ceftriaxone [difference (95% CI), 5.9% (-1.0, 12.7)]. Clinical cure rates for CAP caused by S. pneumoniae in the microbiological MITTE (mMITTE) population were 83.3% (35/42) and 70.0% (28/40) for ceftaroline fosamil and ceftriaxone, respectively. Ceftaroline fosamil and ceftriaxone were well tolerated, with similar rates of AEs, serious AEs, deaths and discontinuations due to an AE. The most common AEs for ceftaroline fosamil-treated patients were diarrhoea, headache, hypokalaemia, insomnia and phlebitis, and the most common AEs for ceftriaxone-treated patients were diarrhoea, insomnia, phlebitis and hypertension. Conclusions Ceftaroline fosamil achieved high clinical cure and microbiological response rates in patients hospitalized with CAP of PORT risk class III or IV. Ceftaroline fosamil was well tolerated, with a safety profile that is similar to that of ceftriaxone and other cephalosporins. Ceftaroline fosamil is a promising agent for the treatment of CAP.

Belastungstests konnen zur Beurteilung der korperlichen Belastbarkeit, zur differenzialdiagnostischen Abklarung der Dyspnoe, zur Analyse von Gasaustauschstorungen, zur Beurteilung eines belastungsinduzierten Bronchospasmus, zur Trainingssteuerung und bei der Begutachtung wie auch zur praoperativen Risikoabschatzung eingesetzt werden. Sie sind ferner zur Beurteilung von medikamentosen und nichtmedikamentosen Therapieeffekten sowie zur Abschatzung der Prognose bei zahlreichen Herz- und Lungenerkrankungen hilfreich. Die Auswahl des Belastungstests erfolgt in Abhangigkeit von der Fragestellung. Vor Durchfuhrung der Belastung sollten neben Anamnese und korperlichem Untersuchungsbefund ein Ruhe-EKG, eine Rontgenuntersuchung der Thoraxorgane, fakultativ auch eine Spirometrie mit Bestimmung der Blutgaspartialdrucke in Ruhe erfolgen. Die Belastungstests konnen zur Beurteilung der Ausdauerleistung sowie der maximalen Leistungsfahigkeit eingesetzt werden. Haufigste Belastungsuntersuchungen sind der 6-min-Gehtest, die Ergometrie auf dem Fahrrad in sitzender oder halb liegender Position sowie die Untersuchung auf dem Laufband. Mittels standardisierter Protokolle werden Kenngrosen der Belastung entweder unter Steady-state-Bedingungen oder – zunehmend haufiger – in Form eines Rampenprotokolls untersucht. Die Ergebnisse der Belastungsuntersuchungen sind in Zusammenschau mit Anamnese, klinischen Untersuchungsbefunden und klinischen Befunden zu werten.

Das pulmorenale Syndrom ist ein internistischer Notfall, der unbehandelt mit einer hohen Letalitat einhergeht. Die haufigsten Ursachen sind die ANCA-assoziierten Vaskulitiden – unter diesen am haufigsten die Wegener-Granulomatose und die mikroskopische Polyangiitis – und das Goodpasture-Syndrom. Nach primarer respiratorischer und hamodynamischer Stabilisierung der Patienten ist eine schnelle Diagnose unter Berucksichtigung vieler Differenzialdiagnosen wichtig, um unverzuglich eine adaquate Therapie einleiten zu konnen. Hilfreich sind hier neben einer gezielten Anamnese und Untersuchung die Bestimmung von Autoantikorpern sowie Bildgebung und Bronchoskopie, auserdem sollte eine Nierenbiopsie erfolgen. Der diagnostische Wert einer Lungenbiopsie ist bisher nicht belegt. Die Therapie basiert im Wesentlichen auf einer aggressiven Immunsuppression und der Plasmapherese.

Eine 60-jahrige Patientin prasentierte sich 4 Monate nach einer Herztransplantation mit Fieber und einem neu aufgetretenen Lungenrundherd. Die mikrobiologische Aufarbeitung einer bronchoalveolaren Lavage und eines Lungenteilresektats ergab die Diagnose einer pulmonalen Nokardiose. Weiterhin konnte eine Beteiligung des zentralen Nervensystems festgestellt werden. Eine antibiogrammgerechte Therapie uber rund 1 Jahr fuhrte zu einer vollstandigen Eradikation der pulmonalen und zerebralen Nokardiose. Bei pulmonalen Raumforderungen immunsupprimierter Patienten ist fruh nach einer Organtransplantation vor allem an opportunistische Infektionen zu denken. In der Spatphase konnen Tumoren ursachlich sein.

BASIC PROBLEM AND OBJECTIVE OF THE STUDY Lung volume reduction (LVR) is a new surgical approach designed to relieve shortness of breath and improve exercise tolerance in patients with severe lung emphysema. The aim of this study was to analyse changes of lung function, gas exchange, exercise tolerance and degree of dyspnoea one and 3 months after LVR. PATIENTS AND METHODS Seventeen patients (15 men and two women; mean age 53 [38-68] years) with severe emphysema (six with alpha 1-PI deficiency) underwent unilateral (n = 14) or bilateral (n = 3) LVR surgery. One week before and one and 3 months after surgery pulmonary function tests, arterial blood gas analysis at rest breathing room air, 6-minute walking distance and dyspnoea score (Medical Research Council Scale) were determined. RESULTS There was a significant increase in forced expiratory vital capacity after one second (FEV1, P < 0.001), and a significant decrease in total lung capacity (TLC, P < 0.0001) and residual volume (RV, P < 0.0001). The mean increase in FEV1 was 39% and in PaO2 9%. The mean decrease in TLC was 20%, in RV 26% (P < 0.001; both comparisons), and in paCO2 4% (not significant). The mean 6-minute walking distance increased by 96% from 229 to 405 meters (P < 0.0001). The mean dyspnoea score on a five point scale (0-4 points) decreased by 52% from 3.4 to 1.6. With the exception of the improved inspiratory vital capacity the postoperative results at one and 3 months after LVR did not differ significantly. All patients were alive 3 months postoperatively. CONCLUSIONS In patients with severe emphysema surgical LVR shows significantly improved pulmonary function, gas exchange, dyspnoea and walking distance as assessed one and three months postoperatively. The early mortality seems to be low.

Summary Background Hypocomplementemic urticarial vasculitis (HUV) with pulmonary emphysema is associated with a poor prognosis, despite high-dose anti-inflammatory treatment including steroids. Objective A female former marathon runner, age 47 years, was diagnosed with HUV with skin, renal and pulmonary involvement. Pulmonary arterial pressure was increased during exercise, a novel finding in this disease entity. Complement consumption was associated with the presence of an anti-C1q autoantibody (IgG). Methods The initial treatment included high-dose steroids and chloroquine. In analogy to other systemic inflammatory lung diseases, increased oxidant levels were postulated and high-dose acetylcysteine (NAC) was initiated. Later on, dapsone as an inhibitor of pathologically increased neutrophil function was added. Results Within 3 months, this therapy resulted in a significant increase of the reduced serum complement levels (CH50, APH50, C4A, and C4B), diffusing capacity, decrease of the anti-C1q autoantibody titer, and normalization of the increased granulocyte count in the broncho-alveolar lavage. Additionally, a stepwise improvement of exercise tolerance (6-min walk test, oxygen consumption during exercise) was seen. Dapsone had no further effect on diffusing capacity or (did not affect) complement serum levels, which remained slightly reduced but stable despite the presence of the anti-C1q autoantibody. The effects have remained stable for the following 36 months. The therapy was well tolerated. Conclusions Antioxidant therapy with high-dose NAC might be a potential addition to the conventional anti-inflammatory therapy in patients with HUV and pulmonary involvement. It should be considered for investigation in a larger patient population.

The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.

We examine the diagnosis of processor array systems formed as two-dimensional arrays, with boundaries, and either four or eight neighbors for each interior processor. We employ a parallel test schedule. Neighboring processors test each other, and report the results. Our diagnostic objective is to find a fault-free processor or set of processors. The system may then be sequentially diagnosed by repairing those processors tested faulty according to the identified fault-free set, or a job may be run on the identified fault-free processors. We establish an upper bound on the maximum number of faults which can be sustained without invalidating the test results under worst case conditions. We give test schedules and diagnostic algorithms which meet the upper bound as far as the highest order term. We compare these near optimal diagnostic algorithms to alternative algorithms, both new and already in the literature, and against an upper bound ideal case algorithm, which is not necessarily practically realizable. For eight-way array systems with N processors, an ideal algorithm has diagnosability 3N/sup 2/3/-2N/sup 1/2/ plus lower-order terms. No algorithm exists which can exceed this. We give an algorithm which starts with tests on diagonally connected processors, and which achieves approximately this diagnosability. So the given algorithm is optimal to within the two most significant terms of the maximum diagnosability. Similarly, for four-way array systems with N processors, no algorithm can have diagnosability exceeding 3N/sup 2/3//2/sup 1/3/-2N/sup 1/2/ plus lower-order terms. And we give an algorithm which begins with tests arranged in a zigzag pattern, one consisting of pairing nodes for tests in two different directions in two consecutive test stages; this algorithm achieves diagnosability (3/2)(5/2)/sup 1/3/N/sup 2/3/-(5/4)N/sup 1/2/ plus lower-order terms, which is about 0.85 of the upper bound due to an ideal algorithm.

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed; this approach is initially based on fault simulation using a small set of random vectors; an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.

This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); and the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM can be affected by multiple faults. Maximal diagnosis consists of detection and location of all diagnosable faults as well as type identification of multiple faults affecting each line. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-1}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines. IMDA executes in three different steps: the first step diagnoses the data lines (and in particular the stuck-at faults); the second step accomplishes maximal diagnosis of the shorts (involving either the data lines only, or the data and address lines); and the third step completes the diagnosis of the address lines.

We address the problem of predicting the yield of a chip composed of cores. A center-satellite model is used to directly represent observed spatial autocorrelation of integrated circuit spot defects. This model is compared to another (large-area clustering) model that only indirectly represents intrawafer correlation. We illustrate that, when different portions of a chip have different susceptibility to defects, the chip layout will affect the predicted yield. This is particularly relevant when portions of a chip are defect-tolerant because their susceptibility to defects is dramatically different. We illustrate how the yield models can be used to predict the utility of making much of a chip (or an embedded core) defect-tolerant. Two yield points parameterized the models. The one extra parameter of, and the suitability of, the center-satellite model allowed it to track the yield data points with less than 1 /10,000 of the error of the large-area clustering model. However, the simpler large-area clustering model is accurate in some circumstances, especially when the chip area is small.

We give two algorithms for maximal diagnosis of wiring networks without repair under a general fault model. Maximal diagnosis consists of identifying all diagnosable faults under the assumptions that each net can have multiple drivers and receivers and can be affected by any number of short and open faults. This process is equivalent to verifying all connections between inputs and outputs. Matrices represent the connections in fault-free and faulty networks. We present two new algorithms and discuss prior algorithms. All algorithms discussed are adaptive and have their tests divided into two phases. Our first new algorithm exploits a unique condition for verifying the connections; our second new algorithm maps the connection verification problem to a bipartite graph. All algorithms discussed use an independent test set for the first test phase. Simulation results show that the proposed algorithms outperform previous algorithms for maximal diagnosis in terms of the number of tests. The total time complexity for computing the test sequences and analyzing the output response is polynomial.

Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models. We propose several methods and strategies for a diagnosis using different fault models, including those applicable to submicron technology. Besides defining new features, such as the logical extent of faults, we also propose a reduction strategy that permits 100% fault detection and identification (including fault location).

We present a methodology for production-time testing of one-time programmable field programmable gate arrays (FPGAs) such as those manufactured by Actel. The methodological principles are based on connecting the uncommitted modules (sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays, similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions for constant testability (C testability). Two design approaches are proposed. Features such as testing time and hardware requirements (measured by the number of cycles and additional transistors and primary input-output pins) are analyzed. We show that the proposed designs require considerably less testing time than a previous technique based on scan. The proposed approaches require 8+n/sub f/ vectors for testing the Actel FPGAs, where n/sub f/ is the number of flip-flops in a row. Hardware overhead for the testing circuitry is also analyzed.

An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing by up to a factor of seven versus direct methods of multiple faulty block detection.

This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors.

Field-programmable gate arrays can suffer from a variety of faults, ranging from wire anomalies and defects to inoperative programmable connections. The solution to these faults depends on whether or not we are dealing with a reprogrammable FPGA or a one time programmable (OTP) FPGA. To correct faults, developers can reconfigure FPGAs such as those made by Xilinx and Altera by reprogramming. These devices can be programmed many times, for different designs and applications. Correcting faults in OTP FPGAs, such as those made by Actel is more difficult. For one thing, OTP FPGAs are based on antifuses. With an antifuse, the FPGAs configuration information has an initial (default) value that can be changed, but once changed cannot be restored. Therefore, the procedures to bypass faulty cells or faulty routing in an OTP FPGA must meet more stringent requirements than for reprogrammable FPGAs. The "Reconfiguration Approaches" sidebar describes two methods other researchers have tried. This article describes our approach to reconfiguring OTP FPGAs. We explain how we determine if reconfiguration is feasible, the algorithms we used, and the results of our experiments on a generic OTP FPGA model and a generic detail router.

We give three new algorithms to compute tests for faults in the interconnects of random access memories (RAM) using only read and write operations. Diagnosis of address line faults is the most difficult step. Our Adaptive Diagnosis Algorithm (ADA) considers each address line separately. Single line faults are easy to diagnose, so the objective is to ascertain which address lines are free of faults, thereby pruning impossible multi-line faults. Our Consecutive Diagnosis Algorithm (CDA) uses a more complicated and lengthier test sequence. However, with CDA, interpreting the test results is easier and the diagnostic resolution is superior. Our third algorithm, Adaptive Diagnosis Algorithm with Repair (ADAR), relies upon additional testing after repair in order to diagnose more faults than would otherwise be possible. ADAR has three test stages with two repair stages between them.

This approach uses the criterion of equivalent classes to establish the equivalence between two circuits and designs. Combining simulation and automatic test pattern generation, it exploits similarities among designs to assess logical equivalence quickly and reliably.

We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

This paper presents a new approach for diagnosing shorts in interconnects in which the adjacencies between nets are known. This structural approach exploits different graph coloring techniques to generate a test set with no aliasing and confounding, i.e., full diagnosis (detection and location) is accomplished. Initially, a simple coloring approach based on a greedy condition of the adjacency graph is proposed for fault detection. Then, the conditions for aliasing and confounding are analyzed with respect to the sizes of the possible shorts. These results are used to generate new colors using a process called color mixing. Color mixing guarantees that additional tests, required in order to avoid aliasing/confounding, will use appropriate codes. The characteristics of unbalanced/balanced codes for encoding the colors in the vector-generation process of interconnect diagnosis are discussed and are proved to yield full diagnosis using a novel method. An algorithm for full diagnosis is then presented; this algorithm has an execution complexity of O ( max { N 2 , N × D 3 }) where N is the number of nets and D is the maximum degree of the nodes in the adjacency graph. Simulation results show that the proposed approach requires a smaller number of test vectors than previous approaches.

To determine the optimal redundancy organization for yield enhancement, redundant and modular memories are analyzed using the center-satellite model. The model suggests that the degree of redundancy for a memory module be determined according to its distance from the periphery of the wafer since the defect density increases as the periphery is neared. Analytical expressions are formulated for the yield of memory modules with extra rows and/or extra columns, coding, and coding with extra rows. Results from the analysis suggest that, for high levels of defect densities, coding can be more effective than simple extra rows and columns. For high levels of defect densities, coding with extra rows is shown to offer even better yield. For low levels of defect densities, though, just extra rows and columns may be sufficient for a high yield. An optimal amount of redundancy can be found to achieve the highest possible yield using the model that considers precise cluster distributions on the wafer, defects in a cluster, and the radial variation of these defects. >

The impact of communication structures on the robustness and performance of distributed computing systems is discussed. Communication structures are categorized as (1) point-to-point, (2) bus, and (3) multistage switching. The most significant networks that have been proposed are discussed. Networks are compared with respect to (1) connectivity, (2) diameter, (3) average distance, (4) diameter in the presence of faults, (5) extensibility (ease of adding or deleting processors), and (6) ease of routing in the presence of faults. Some attempts directed at achieving near optimality for each of these six factors are discussed. A strategy for designing good networks with respect to all of these factors is suggested. Attempts to predict the real-time robustness of systems are reviewed and commented on and the power and consistency of metrics associated with such attempts are discussed. The impact of communication structures is discussed with respect to fundamental fault-tolerant objectives, such as diagnosis and disconnection of faulty units and establishment of a logical link between units not connected by a physical link. Current trends and suggested trends in communication network research are commented on. © 1993 by John Wiley & Sons, Inc.

The problem of achieving consensus in a distributed system is discussed. Systems are treated in which either or both of two types of faults may occur: dormant (essentially omission and timing faults) and arbitrary (exhibiting arbitrary behavior, commonly referred to as Byzantine). Previous results showed that are number of dormant faults may be tolerated when there are no arbitrary faults and that, at most, (n-1/3) arbitrary faults may be tolerated when there are no dormant faults (n is the number of processors). A continuum is established between the previous results: an algorithm exists iff n>f/sub max/+2m/sub max/ and c>f/sub max/+m/sub max/ (where c is the system connectivity), when faults are constrained so that there are at most f/sub max/ and at most m/sub max/ of these that are arbitrary. An algorithm is given and compared to known algorithms. A method is given to establish virtual links so that the communications graph appears completely connected. >

A young pregnant woman (32nd week of gestation) presented with acute chest pain due to right coronary artery dissection (CAD) in a pre-hospital setting. The pre-hospital diagnosis by the ambulance staff of an acute myocardial infarction in the antenatal period based on a 12-lead ECG combined with successful treatment by percutaneous coronary intervention with stenting is novel.

An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around cost-effective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed

This work describes the implementation of two different BISR algorithms for memories with spare rows and columns. The choice of BISR technology must depend on the final net yield due to area, susceptibility to defects, and repair probability. The Single Deferral algorithm has near the minimal memory requirement. The greedy algorithm is a standard heuristic algorithm that iteratively repairs the line with the most excess defects. The memory requirement for the greedy algorithm is quadratic in the number of spares while Single Deferral is linear. Since the repair probability with Single Deferral is near optimal, it is more cost-effective than greedy.

The objective of this paper is to provide a framework by which jitter phenomena, which are encountered at the output signals of a head board in an automatic test equipment (ATE), can be studied. In this paper, the jitter refers to the one caused by radiated electromagnetic interference (EMI) noise, which is present in the head of all ATE due to DC-DC converter activity. An initial analysis of the areas of the head board most sensitive to EMI noise has been made. It identifies a sensitive part in the loop filler of a phase locked loop which is used to obtain a high frequency clock for the timing generator. Different H-fields are then applied externally at the loop filter to verify the behavior of the output signal of the head board in terms of RMS jitter. As for RMS jitter measurements, a frequency domain methodology has been employed. A trend for RMS jitter variation with respect to radiated EMI magnitude as well as frequency has been obtained. Also the orientation of the external H-field source with respect to the target board and its effects on the measured RMS jitter has been investigated. For measuring the RMS value, a proper circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment.

This paper presents theoretical yet practical methodologies to model, assure and optimize the reliability of clockless wave pipeline. Clockless wave pipeline is a cutting-edge and innovative technology as an alternative to traditional pipeline, and a promising computing model towards ultra-high throughput and speed. The basic computational components of such clockless wave pipeline are data waves in association with request signals and switches. The key to the success of clockless wave pipeline is how to coordinate and ensure the processing of datawaves throughout the pipeline in association with the request signals without relying on any intermediate access points under clocked-control. Due to the complication of clockless operations, an efficient and effective method to model and analyze the confidence level (referred to as reliability or yield) of clockless operations of wave pipeline is exigently demanded, but has not yet been adequately addressed, in an integrated level such as datawaves in association with request signals, leaving this as a challenge. In this regard, out-of-orchestration between datawaves and request signals, referred to as datawave fault, is the major concern in assuring and optimizing the reliability of the system. This paper specifically addresses and resolves: extensive and practical clockless-induced datawave-fault modeling; assurance and optimization; clockless-oriented fault tolerant design methods. The proposed methods will establish a sound and adequate theoretical foundation for development of innovative yet practical test/diagnosis/fault-tolerant design methods in early design stage of clockless wave pipeline.

This work presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as a design case.

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (OUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.

Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16 A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.

With the increasing needs for memory testing and repair, yield evaluation is an essential decision-making factor to define redundancy allocation and testing strategies. In particular, yield evaluation can resolve the many issues revolving around cost-effective BIST solutions and purely ATE based techniques to guarantee higher test transparency. In this document, two different yield calculation methodologies for SRAM arrays are presented. General yield calculation formulas for VLSI chips are initially presented. The regular repetitive structure of a RAM array is considered because it shows major yield improvements with the introduction of redundancy. Two repair yield evaluation formulas for a 1D redundant array are introduced and compared; the first one is based on Markov modeling, the second one is based on an approximation.

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments - such as extreme radiation - can be experienced throughout the mission. Acceptable dependability for these instruments have been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering. This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a sound foundation of measurement. Then, long-life dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (MTTF i.e., the expected time that a system will operate before it fails).

Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. Instrumentation and measurement systems have found and enjoyed their performance enhancement through parallel and distributed processing. High speed and density Multistage Interconnection Networks (MINs) are widely-used subsystems of parallel processing and communication systems. New performance models are proposed to evaluate the fault tolerant MIN in this paper, thereby establishing a sound foundation for assuring the performance and reliability of fault tolerant MINs with high confidence level during parallel instrumentation. A concurrent fault detection and recovery scheme for MINs is introduced to enable a generic approach to fault tolerance by rerouting over the redundant interconnection links. A switch architecture to realize the concurrent testing and diagnosis is shown. The proposed performance models are developed and used to evaluate the compound effect of the fault tolerant operations such as testing, diagnosis and recovery on the throughput and delay. Results are shown on single transient and permanent stuck-at fault on links and storage units in switching elements. it is shown that the performance degradation for the overhead due to the fault tolerance is quite graceful while the performance degradation without fault recovery is unacceptable.

This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ).

A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.

We examine the problem of identifying good processors in self-testing two-dimensional grid systems. The grids have boundaries (not wrap-around) and degree 8. Our diagnostic objective is to identify at least one fault-free processor. From this, at feast one faulty processor could be identified and it would be possible to sequentially diagnose the system by repeated repair. We establish an upper bound on the worst case maximum number of faults while still being able to meet the diagnostic goal with an ideal diagnosis algorithm. A straightforward ideal diagnosis algorithm would have exponential complexity and would involve 16 parallel rounds of processor testing. We give a test schedule with at most 6 parallel rounds of testing. This test schedule tolerates asymptotically as many faults as an ideal algorithm (by a constant factor). The new test schedule will also work for grids with degree 4, which have inferior diagnostic potential.

We give two algorithms for maximal diagnosis of wiring networks without repair under a general fault model. Maximal diagnosis consists of identifying all diagnosable faults under the assumptions that each net can have multiple drivers and receivers and can be affected by any number of short and open faults. This process is equivalent to verifying all connections between inputs and outputs. Matrices represent the connections in fault-free and faulty networks. All algorithms discussed are adaptive and have their tests divided into two phases. Our first algorithm exploits a unique condition for verifying the connections; our second algorithm maps the connection verification problem to a bipartite graph. All algorithms use an independent test set for the first test phase. Simulation results show that the proposed algorithms outperform previous algorithms for maximal diagnosis, in terms of the number of tests. The total time complexity for computing the test sequences and analyzing the output response is polynomial.

We give a comprehensive model of interconnect testing in boundary scan architectures. This includes two fault categories: driver faults (stuck-at, stuck-driving, and stuck-not-driving (equivalent to stuck-open)) and net faults (shorts). We permit short faults to exhibit zero-dominance (wired-AND), one-dominance (wired-OR), and net-dominance. We split the built-in self-test hardware into two components: a control pattern test generator (CTPG) and a data pattern test generator (DTPG). For the DTPG, we use a complementary counting sequence, which is an instance of a maximal independent test set. We give novel designs for CTPGs that guarantee 100% fault coverage with low hardware overhead and time complexity. We give a general and complete procedure to implement the CTPGs. Using a linear feedback shift register as a one-shot counter to cover all control cells in the boundary scan, we ensure that no two control cells of one net are assigned to a single register; this avoids circuit damage when testing.

In this paper, a novel architecture for built-in self test (BIST) and different designs for both the control and data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity.

This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM are involved in multiple faults simultaneously. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-I}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines.