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39 results on '"Fonteneau, Pascal"'

7. $4.6\mu \mathrm{m}$ Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera

Author

Tubert, Cedric, primary, Mellot, Pascal, additional, Desprez, Yann, additional, Mas, Celine, additional, Authie, Arnaud, additional, Simony, Laurent, additional, Bochet, Gregory, additional, Drouard, Stephane, additional, Teyssier, Jeremie, additional, Miclo, Damien, additional, Bezal, Jean-Raphael, additional, Augey, Thibault, additional, Hingant, Franck, additional, Bouchet, Thomas, additional, Roig, Blandine, additional, Mazard, Aurelien, additional, Vergara, Raoul, additional, Mugny, Gabriel, additional, Tournier, Arnaud, additional, Lalanne, Frederic, additional, Roy, Francois, additional, Goncalves, Boris Rodrigues, additional, Vignetti, Matteo, additional, Fonteneau, Pascal, additional, Farys, Vincent, additional, Agut, Francois, additional, Santos, Joao Miguel Melo, additional, Hadden, David, additional, Channon, Kevin, additional, Townsend, Christopher, additional, Rae, Bruce, additional, and Pellegrini, Sara, additional

Published
2021
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8. 4.6µm Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera

Author

Tubert, Cedric, primary, Mellot, Pascal, additional, Desprez, Yann, additional, Mas, Celine, additional, Authie, Arnaud, additional, Simony, Laurent, additional, Bochet, Gregory, additional, Drouard, Stephane, additional, Teyssier, Jeremie, additional, Miclo, Damien, additional, Bezal, Jean-Raphael, additional, Augey, Thibault, additional, Hingant, Franck, additional, Bouchet, Thomas, additional, Roig, Blandine, additional, Mazard, Aurelien, additional, Vergara, Raoul, additional, Mugny, Gabriel, additional, Tournier, Arnaud, additional, Lalanne, Frederic, additional, Roy, Francois, additional, Goncalves, Boris Rodrigues, additional, Vignetti, Matteo, additional, Fonteneau, Pascal, additional, Farys, Vincent, additional, Agut, Francois, additional, Santos, Joao Miguel Melo, additional, Hadden, David, additional, Channon, Kevin, additional, Townsend, Christopher, additional, Rae, Bruce, additional, and Pellegrini, Sara, additional

Published
2021
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10. Z²-FET as capacitor-less eDRAM cell for high-density integration

Author

Navarro, Carlos, Duan, Meng, Parihar, Mukta Sing, Adamu-Lema, Fikru, Coseman, Stefan, Lacord, Joris, Lee, Kyunghwa, Sampedro, Carlos, Cheng, Binjie, El Dirani, Hassan, Barbe, Jean-Charles, Fonteneau, Pascal, Kim, Seong-Il, Cristoloveanu, Sorin, Bawedin, Maryline, Millar, Campbell, Galy, Philippe, Le Royer, Cyrille, Karg, Siegfried, Riel, Heike, Wells, Paul, Kim, Yong-Tae, Asenov, Asen, and Gamiz, Francisco

Subjects
Hardware_INTEGRATEDCIRCUITS
Abstract

2-D numerical simulations are used to demonstrate the Z²-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

Published
2017

11. Extended analysis of the Z²-FET: operation as capacitorless eDRAM

Author

Navarro, Carlos, Lacord, Joris, Parihar, Mukta Singh, Adamu-Lema, Fikru, Duan, Meng, Rodriguez, Noel, Cheng, Binjie, El Dirani, Hassan, Barbe, Jean-Charles, Fonteneau, Pascal, Bawedin, Maryline, Millar, Campbell, Galy, Philippe, Le Royer, Cyrille, Karg, Siegfried, Wells, Paul, Kim, Yong-Tae, Asenov, Asen, Cristoloveanu, Sorin, and Gamiz, Francisco

Subjects
Hardware_MEMORYSTRUCTURES, Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY
Abstract

The Z²-FET operation as capacitorless DRAM\ud is analyzed using advanced 2-D TCAD simulations for IoT\ud applications. The simulated architecture is built based on\ud actual 28-nm fully depleted silicon-on-insulatordevices. It is\ud found that the triggering mechanism is dominated by the\ud front-gate bias and the carrier’s diffusion length. As in other\ud FB-DRAMs, the memory window is defined by the ON voltage\ud shift with the stored body charge. However, the Z²-FET’s\ud memory state is not exclusively defined by the inner charge\ud but also by the reading conditions.

Published
2017

12. Z2-FET memory for low power applications

Author

Parihar, Mukta Singh, Lee, Kyunghwa, Dirani, Hassan El, Navarro, Carlos, Lacord, Joris, Martinie, Sebastien, Barbé, Jean-Charles, Fonteneau, Pascal, Galy, Philippe, Le Royer, Cyrille, Mescot, Xavier, Gamiz, Francisco, Cheng, Binjie, Asenov, Asen, Taur, Yuan, Bawedin, Mayline, Cristoloveanu, Sorin, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), University of Granada [Granada], Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Synopsys Inc., James Watt School of Engineering [Univ Glasgow], University of Glasgow, University of California [San Diego] (UC San Diego), University of California, 2017 ESSDERC, Universidad de Granada = University of Granada (UGR), and University of California (UC)

Subjects
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2017

13. ${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Author

Navarro, Carlos, primary, Duan, Meng, additional, Parihar, Mukta Singh, additional, Adamu-Lema, Fikru, additional, Coseman, Stefan, additional, Lacord, Joris, additional, Lee, Kyunghwa, additional, Sampedro, Carlos, additional, Cheng, Binjie, additional, El Dirani, Hassan, additional, Barbe, Jean-Charles, additional, Fonteneau, Pascal, additional, Kim, Seong-Il, additional, Cristoloveanu, Sorin, additional, Bawedin, Maryline, additional, Millar, Campbell, additional, Galy, Philippe, additional, Le Royer, Cyrille, additional, Karg, Siegfried, additional, Riel, Heike, additional, Wells, Paul, additional, Kim, Yong-Tae, additional, Asenov, Asen, additional, and Gamiz, Francisco, additional

Published
2017
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14. Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Author

Navarro, Carlos, primary, Lacord, Joris, additional, Parihar, Mukta Singh, additional, Adamu-Lema, Fikru, additional, Duan, Meng, additional, Rodriguez, Noel, additional, Cheng, Binjie, additional, El Dirani, Hassan, additional, Barbe, Jean-Charles, additional, Fonteneau, Pascal, additional, Bawedin, Maryline, additional, Millar, Campbell, additional, Galy, Philippe, additional, Le Royer, Cyrille, additional, Karg, Siegfried, additional, Wells, Paul, additional, Kim, Yong-Tae, additional, Asenov, Asen, additional, Cristoloveanu, Sorin, additional, and Gamiz, Francisco, additional

Published
2017
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15. Low-Power Z2-FET Capacitorless 1T-DRAM

Author

Parihar, Mukta Singh, primary, Lee, Kyung Hwa, additional, El Dirani, Hassan, additional, Navarro, Carlos, additional, Lacord, Joris, additional, Martinie, Sebastien, additional, Barbe, Jean-Charles, additional, Fonteneau, Pascal, additional, Galy, Philippe, additional, Le Royer, Cyrille, additional, Mescot, Xavier, additional, Gamiz, Francisco, additional, Cheng, Binjie, additional, Asenov, Asen, additional, Taur, Yuan, additional, Bawedin, Mayline, additional, and Cristoloveanu, Sorin, additional

Published
2017
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16. A lesson from archeology: The buried gates

Author

Litty, Antoine, Solaro, Yohann, Dirani, Hassan El, Ortolland, Sylvie, Fonteneau, Pascal, Onestas, L., Fenouillet-Beranger, Claire, Le Royer, Cyrille, Bawedin, Maryline, Zaslavsky, Alexander, Ferrari, Philippe, Cristoloveanu, Sorin, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), School of Engineering (Brown Engineering), Brown University, Ducroquet, Frédérique, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMethodologies_GENERAL, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS
Abstract

session poster; International audience

Published
2015

17. New Insights in Z2-FET Mechanisms at Variable Temperature

Author

Dirani, Hassan El, Onestas, L., Ferrari, Philippe, Cristoloveanu, Sorin, Solaro, Y., Fonteneau, Pascal, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Triggering Voltage, Zero Impact Ionization and Subthreshold Slope FET (Z2-FET), Electrostatic Discharge (ESD), Temperature Dependence, Leakage Current, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Fully Depleted SOI (FDSOI)
Abstract

session 4: Steep slope devices; International audience; The Z2-FET (Zero Impact Ionization and Subthreshold Slope FET), a recent sharp switching devicewith zero subthreshold swing and zero impact ionization, is considered for Electro-Static Discharge (ESD)protection of Fully Depleted SOI (FDSOI) circuits. We study the impact of low and high temperature on thedevice performance, showing its effect on the output characteristics, triggering voltage (VON) and leakagecurrent (ILeak).

Published
2015

18. Thin-body ESD protections in 28nm UTBB-FDSOI: From static to transient behavior

Author

Solaro, Yohann, Fonteneau, Pascal, Legrand, Charles-Alexandre, Marin-Cudraz, David, passieux, Jérémy, guyader, pascal, Clément, Laurent-Renaud, Fenouillet-Beranger, Claire, Ferrari, Philippe, Cristoloveanu, Sorin, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Electronic ISBN: 978-1-58537-257-7, Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Ducroquet, Frédérique

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Innovative Ultra-Thin Body and Buried Oxide FDSOI protections (BBC-T and Z2-FET) are characterized and analyzed in order to assess the CDM time domain behavior. In addition to static (leakage and triggering) control, it is found that front and back gate coupling is a very efficient way to improve the transient responses of the proposed devices.

Published
2014

19. Z^\textsf 2 -FET as Capacitor-Less eDRAM Cell For High-Density Integration.

Author

Navarro, Carlos, Meng Duan, Singh Parihar, Mukta, Adamu-Lema, Fikru, Coseman, Stefan, Lacord, Joris, Kyunghwa Lee, Sampedro, Carlos, Binjie Cheng, El Dirani, Hassan, Barbe, Jean-Charles, Fonteneau, Pascal, Seong-Il Kim, Cristoloveanu, Sorin, Bawedin, Maryline, Millar, Campbell, Galy, Philippe, Le Royer, Cyrille, Karg, Siegfried, and Riel, Heike

Subjects
CAPACITORS, CIRCUIT elements, FIELD-effect transistors, COMPUTER simulation, ELECTROMECHANICAL analogies
Abstract

2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. [ABSTRACT FROM AUTHOR]

Published
2017
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21. Local ESD protection structure based on Silicon Controlled Rectifier achieving very low overshoot voltage

Author

Bourgeat, Johan, Entringer, Christophe, Galy, Philippe, Fonteneau, Pascal, Bafleur, Marise, STMicroelectronics [Crolles] (ST-CROLLES), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), convention CIFRE STMicrolectronics, Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
Hardware_INTEGRATEDCIRCUITS, ESD, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, SCR, 45nm CMOS technology, overshoot
Abstract

International audience; This paper presents a new local ESD protection structure. This structure is based on static triggered SCR and realized in a 45nm CMOS technology node. This protection achieves very low static triggering voltage, low on-resistance, low DC leakage current for off configurations. This new structure is latch-up free and fail safe.

Published
2009

22. Sharp-switching band-modulation back-gated devices in advanced FDSOI technology.

Author

Fonteneau, Pascal, Legrand, Charles-Alex, Marin-Cudraz, David, El Dirani, Hassan, Solaro, Yohann, Ferrari, Philippe, and Cristoloveanu, Sorin

Subjects
*SILICON-on-insulator technology, *IONIZATION (Atomic physics), *FABRICATION (Manufacturing)
Abstract

A band-modulation device with a free top surface, named Z 3 -FET (Zero front-gate, Zero swing slope and Zero impact ionization) and fabricated in the most advanced Fully Depleted Silicon-On-Insulator technology, is demonstrated experimentally. Since the device has no front gate, the operation mechanism is controlled by two adjacent heavily doped buried ground planes acting as back-gates. Characteristics such as sharp quasi-vertical switching, low leakage, and tunable trigger voltage are measured and discussed. We explore several variants (thin and thick silicon or SiGe body) and show promising results in terms of high current, switching performance and ESD capability with relatively low back-gate and drain bias operation. [ABSTRACT FROM AUTHOR]

Published
2017
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25. Innovative ESD protections for UTBB FD-SOI technology

Author

Solaro, Yohann, primary, Fonteneau, Pascal, additional, Legrand, Charles-Alexandre, additional, Marin-Cudraz, David, additional, Passieux, Jeremy, additional, Guyader, Pascal, additional, Clement, Laurent-Renaud, additional, Fenouillet-Beranger, Claire, additional, Ferrari, Philippe, additional, and Cristoloveanu, Sorin, additional

Published
2013
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39. Z2-FET: A promising FDSOI device for ESD protection.

Author

Solaro, Yohann, Wan, Jing, Fonteneau, Pascal, Fenouillet-Beranger, Claire, Le Royer, Cyrille, Zaslavsky, Alexander, Ferrari, Philippe, and Cristoloveanu, Sorin

Subjects
*SILICON-on-insulator technology, *IMPACT ionization, *ELECTROSTATIC discharges, *PARAMETER estimation, *MICROFABRICATION
Abstract

Abstract: In this work, the use of the Z2-FET (Zero subthreshold swing and Zero impact ionization FET) for Electro-Static Discharge (ESD) protections is demonstrated. The device, fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator technology, features an extremely sharp off-on switch and an adjustable triggering voltage (Vt 1). The principle of operation, relying on the modulation of electron and hole injection barriers, is reviewed. The impact of process modules and design parameters on electrical characteristics is analyzed with TCAD simulations, showing that very low leakage current (Ileak ) and triggering capability adapted to local protection schemes are achievable. Experimental results validate the possible use of this device as an ESD protection in the 28nm FDSOI technology. [Copyright &y& Elsevier]

Published
2014
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