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International audience; Ion implantation is a suitable and promising solution for the massive industrialization of boron doping, which is a crucial process step for most next-generation solar cells based on crystalline silicon (c-Si). However, the use of ion implantation for boron doping is limited by the high temperature (in the 1050°C range) of the subsequent activation anneal, which is essential to dissolve the boron clusters and reach a high-emitter quality. In this work, we propose the use of plasma-immersion ion implantation (PIII) from B$_2$ H$_6$ gas precursor instead of the standard beamline ion implantation (BLII) technique to decrease this temperature down to 950°C. PIII and BLII boron emitters were compared with annealing temperatures ranging from 950°C to 1050°C. Contrary to BLII, no degradation of the emitter quality was observed with PIII implants annealed at 950°C along with a full activation of the dopants in the emitter. At 1000°C, emitter saturation current densities (J$_{0e}$) below 21 fA/cm$^2$ were obtained using the PIII technique regardless of the tested implanta-tion doses for sheet resistances between 110 and 160 $\Omega$/sq. After metallization steps, the metal/emitter contact resistances were assessed, indicating that these emitters were compatible with a conventional metallization by screen-printing/firing. The PIII boron emitters' performances were further tested with their integration in n-type passivated emitter rear totally diffused (PERT) solar cells fully doped by PIII. Promising results already show a conversion efficiency of 20.8% using a lower annealing temperature than with BLII and a reduced production cost. KEYWORDS annealing temperature, B$_2$ H$_6$ plasma, boron doping, n-type PERT solar cells, plasma-immersion ion implantation, silicon solar cells We report a new way to activate implanted boron emitter at low temperature that is the use of plasma-immersion ion implantation (PIII) from B$_2$H$_6$ plasma. A full activation of the emitter at 950°C was observed even for a high implantation dose corresponding to a sheet resistance of 112 $\Omega$/sq. Promising performances while being integrated in n-PERT solar cells fully doped by PIII were demonstrated with efficiency of 20.8% % using a lower annealing temperature than with BLII and a reduced production cost.

The use of plasma immersion ion implantation (PIII) is a relevant approach for the development of advanced solar cells technologies at lower cost (€/W p ). In this paper, we report on the development of homogeneous boron (B) doping of n-type crystalline silicon (cSi) substrate by the PIII technique. Using diborane (B 2 H 6 ) as gas precursor, various doping profiles were identified fitting the requirements for boron-doped emitters in n-type PERT solar cells. Particularly, saturation current density (J 0e ) of 50 fA/cm 2 were achieved on symmetrical samples for a 94 Ω/sg textured B-emitter passivated with SiO 2 /SiN stack. Bifacial n-type Passivated Emitter Rear Totally-diffused (n-PERT) solar cells were fabricated using the PIII technology and conversion efficiencies up to 19.8% on 239 cm 2 Cz-Si wafers were obtained. As a consequence, these results indicate that PIII can compete with beamline technology but will have lower running cost. It is therefore a promising technology to create high efficiency cSi solar cells.

Since several years, the use of Beamline ion implantation has been proven to allow optimization of doping profiles needed for the fabrication of crystalline silicon (c-Si) solar cells while simplifying the process flow. Nevertheless the cost and complexity of such tools, associated to the difficulty to keep a small thermal budget to make high quality Boron doping for N-type cells, has slowed down the industrial introduction of ion implantation in high volume solar cell fabrication fabs.Thanks to an implant time independent to the implanted surface, and a simple tool architecture, Plasma Immersion Ion Implantation (PIII) offers an economically efficient alternative to Beamline Ion Implantation.In this paper, after having presented PULSION®-Solar, the IBS PIII tool dedicated to solar cell fabrication, we will demonstrate state of the art characteristics on different cells type either on c-Si but also on multi crystal Si where the beneficial gettering capability allowed by POCl 3 is also obtained using PIII phosphorus implantation. We will also show how the PIII doping process, thanks to its unique energy distribution, can even be more efficient than beam line, especially for boron doping, allowing lower thermal budget and co-anneal with phosphorus, simplifying even more the process flow for n-type PERT solar cells.

We have studied the influence of thermal treatments on the redistribution of Mg implanted in GaN on Si. SIMS results highlights the strong effect of Mg concentration on its diffusion behaviour. In the range of 1018 at/cm3 or below, the Mg distribution is not modified after annealing up to 1100°C. In the order of 1019 at/cm3 or higher, such thermal treatment lead to fast diffusion of the implanted Mg in the [0001] direction and a trapping of the Mg at the GaN/capping layer interface. AFM analysis of the GaN surface after capping etching suggest that emerging dislocations are favourable diffusion path for Mg toward the GaN surface. APT analysis reveals that this diffusion behavior go-on with the formation of Mg rich clusters containing about typically a hundred atoms in our process conditions. This diffusion and aggregation behaviors are specific to the Mg specie and have to be taken into account to expect successful integration of p type doping process via Mg implantation in GaN on Si.

Spectral sensitivity measurements versus temperature have been carried out on irradiated SiC p+n photodiodes, fabricated using two different doping processes: Aluminium standard implantation and Boron plasma immersion ion implantation. The spectral sensitivity of Al doped photodiodes increase for incident wavelength higher than 270 nm, and are very stable below. Boron doped irradiated photodiodes show a general increase of the photoresponse for all wavelengths. In both cases, an hysteresis effect is observable when with the temperature. Results are presented and discussed.

Localized p-doping is a keystone in the development of many GaN based devices that need selectively doped pocket area such as MOSFETs or PIN diodes. Electrical activation of implanted Mg has been obtained lately with GaN grown on sapphire substrate using an AlN based protective layer combined with multi cycle of rapid thermal annealing at very high temperature (>1300 °C) proving the feasibility and interest of the method [1]. The use of Si (111) substrate allows a better integration of the process on microelectronic production line. However the growth of GaN on Si (111) is less mature and necessitates a buffer usually composed of a complex staking based on AlN intermediate layers [2]. The difference in lattice parameters and thermal extension coefficient in the stacking may make the samples more unstable during the high thermal budget required for doping activation. In the last few years, several groups focused their research on the prevention of GaN surface degradation at high temperature [3] and we have shown that a combination of in situ epi deposited AlN and SiN thin layers is very efficient to avoid this phenomena [4]. Here, we propose to study the impact of high thermal annealing on the evolution of the damage in Mg-implanted GaN (on Si). Indeed, comprehensive studies of the GaN healing mechanism in this kind of structures are not yet reported. We use samples of GaN layer grown by MOCVD on Si (111) using an AlN based buffer layer and protected by an AlN/SiNx cap layer. These samples are implanted with Mg fluences ranging from 1013 to 1015 at/cm² corresponding to maximum effective concentration between 5.1017 and 5.1019 at/cm3 in the implanted layer. 400 °C -1100 °C anneals are proceeded in controlled N2 atmosphere. X-Ray Diffraction (XRD) and Photoluminescence (PL) measurements point out that ion implantation induced damage are healed thanks to different mechanisms: both lattice strain relaxation and point defect annihilation can occur during annealing with different kinetics. Indeed as we can see on Fig.1a, on samples implanted with low to medium fluence (up to 1014 at/cm²), relatively low temperature anneals (< 450 °C) are enough to obtain a near complete correction of the lattice deformation. However, surprisingly, the PL spectra of 400 °C annealed samples shown on Fig1.b indicates that a lot of non-radiative defects are still present and shutting down the PL intensity. The spectra of the sample annealed at 1100°C exhibits bands characteristic of Mg in Ga site (Mg(Ga)) which proves the necessity of a higher thermal treatment to reduce non radiative defects concentration and promote Mg incorporation in the GaN lattice. As shown on Fig 2.a, an increase of the fluence (1015 at/cm²) leads to an increase of the induced strain but also of the temperature necessary to fully relax it (1100°C). However, the PL spectra (Fig 2.b) indicates that even after such a high thermal treatment, the PL intensity of the bands associated with Mg(Ga) is weaker than for medium fluence despite the higher Mg concentration in the matrix [4]. We assume that this behavior may be due to residual damage. This is supported by Transmission Electron Microscopy images of the layer (not shown here) that evidence remaining defective pockets after a 1 h 1100 °C in N2 annealing. These results give insight on the healing mechanism occurring during the activation anneal of Mg implanted in GaN. They also highlight that damage management is a critical parameter for GaN (on Si) p-doping via Mg implantation. To reach this objective, we will show that it is necessary to implement further specific processes to limit the implantation induced damage and to improve the damage recovery efficiency. 1. Tadjer, M.J., et al., Selective p-type Doping of GaN:Si by Mg Ion Implantation and Multicycle Rapid Thermal Annealing. ECS Journal of Solid State Science and Technology, 2015. 5(2): p. P124-P127. 2. Charles, M., et al., The effect of AlN nucleation temperature on inverted pyramid defects in GaN layers grown on 200 mm silicon wafers. Journal of Crystal Growth, 2017. 464: p. 164-167. 3. El-Zammar, G., et al., Surface state of GaN after rapid-thermal-annealing using AlN cap-layer. Applied Surface Science, 2015. 355: p. 1044-1050. 4. Lardeau-Falcy, A., et al., Capping stability of Mg-implanted GaN layers grown on silicon. physica status solidi (a), 2016. Figure 1

Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration’s requirements, in particular non-IC related technologies one, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, lenses. Actually complex 3D structuration requires complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheaper and easiest technique to achieve 3D structures. In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In a first step a pattern is performed by lithography on a substrate, then ion implantation is realized through a resist mask in order to create localized modifications in the material, thus the pattern is transferred into the subjacent layer. Finally, after the resist stripping, a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one. In this paper, we will first present results achieved with simple 2D line array pattern processed either on Silicon or SiOCH samples. This step have been carried out to demonstrate the feasibility of this new structuration process. SEM pictures reveals that “infinite” selectivity between the implanted areas versus the non-implanted one could be achieved. We will show that a key combination between the type of implanted ion species and wet etching chemistries is required to obtain such results. The mechanisms understanding involved during both implantation and wet etching processes will also be presented through fine characterizations with Photoluminescence, Raman and Secondary Ion Mass Spectrometry (SIMS) for silicon samples, and ellipso-porosimetry and Fourier Transform InfraRed spectroscopy (FTIR) for SiOCH samples. Finally the benefit of this new patterning approach will be presented on 3D patterns structures.

International audience; Production costs and energy efficiency are the main priorities for the photovoltaic (PV) industry (COP21 conclusions). To lower costs and increase efficiency, we are proposing to reduce the number of processing steps involved in the manufacture of N-type Passivated Rear Totally Diffused (PERT) silicon solar cells. Replacing the conventional thermal diffusion doping steps by ion implantation followed by thermal annealing allows reducing the number of steps from 7 to 3 while maintaining similar efficiency. This alternative approach was investigated in the present work. Beamline and plasma immersion ion implantation (BLII and PIII) methods were used to insert n-(phosphorus) and p-type (boron) dopants into the Si substrate. With higher throughput and lower costs, PIII is a better candidate for the photovoltaic industry, compared to BL. However, the optimization of the plasma conditions is demanding and more complex than the beamline approach. Subsequent annealing was performed on selected samples to activate the dopants on both sides of the solar cell. Two annealing methods were investigated soak and spike thermal annealing. Best performing solar cells, showing a PV efficiency of about 20%, was obtained using spike annealing with adapted ion implantation conditions.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible

The doping of n-type silicon solar cells was investigated using two ion implantation techniques: beam line and plasma immersion. Initially, we evaluated the benefits of beamline ion implantation in replacement of diffusion anneal doping process. Two different annealing routines were studied. The first one using a single annealing to activate both B implanted emitter and P implanted BSF, while the second one used two different annealing to separately activate each dopant. Good yield was reached with a record cell of 20.33% efficiency. Secondly, we investigated the doping by plasma immersion ion implantation where the final objective was the fabrication of a solar cell fully doped by plasma. BF3 and B2H6 were compared as precursor gases for the boron emitter doping, while PH3 was used for the BSF doping. Hybrid cells were fabricated using both implantation techniques and a maximum efficiency of 19.8% was obtained. First cells fully doped by plasma shown promising results with a yield of 18.8%.

This paper presents a study of 4H-SiC UV photodetectors based on p+n thin junctions. Two kinds of p+ layers have been implemented, aiming at studying the influence of the junction elaborated by the ion implantation process (and the subsequent annealing) on the device characteristics. Aluminum and Boron dopants have been introduced by beam line and by plasma ion implantation, respectively. Dark currents are lower with Al-implanted diodes (2 pA/cm2 @ - 5 V). Accordingly to simulation results concerning the influence of the junction thickness and doping, plasma B-implanted diodes give rise to the best sensitivity values (1.5x10-1 A/W @ 330 nm).

Ga-doped 3C-SiC layers have been grown on on-axis 6H-SiC (0001) substrates by the VLS technique and investigated by low temperature photoluminescence (LTPL) measurements. On these Ga-doped samples, all experimental spectra collected at 5K were found dominated by strong N-Ga donor-acceptor pair (DAP) transitions and phonon replicas. As expected, the N-Ga DAP zero-phonon line (ZPL) was located at lower energy (~ 86 meV) below the N-Al one. Fitting the transition energies for the N-Al close DAP lines gave 251 meV for the Al acceptor binding energy in 3C-SiC and, by comparison, 337 meV for the Ga acceptor one.

In this paper, we communicate on the design, fabrication, and testing of optical modulators for Silicon-based photonic integrated circuits (Si-PICs) in the O-band (1.31 μm), targeting the 100GBASE-LR4 norm (4 wavelengths at 25 Gbit/s). The modulators have been conceived to be later coupled with hybrid-III-V/Si lasers as well as echelle grating multiplexer, to create a hetero-integrated optical transmitter on a silicon-on-insulator (SOI) platform. The devices are based on a Mach-Zehnder Interferometer (MZI) architecture, where a p-n junction is implanted to provide optical modulation through carrier depletion. A detailed study focusing on the best doping scheme for the junction, aimed at optimizing the overall transmitter performance and power-efficiency is presented. In detail, the trade-off between low optical losses and high modulation efficiency is tackled, with a targeted CMOS-compatible voltage drive of 2.5 V. Process simulations of the junction are realized for the doping profile optimization. Modulators of different lengths are also investigated to study the compromise between extinction ratio, insertion losses and bandwidth. Furthermore, coplanar-strip (SGS) travelling-wave electrodes are designed to maximize the bandwidth, to reach the targeted bit rate of 25 Gbit/s. Measurements show modulation efficiencies up to 19 °/mm (or 2.4 V.cm) for a 2.5 V input voltage, with doping-related losses below 1 dB/mm, in line with theoretical estimates, and well-suited to enhance the Si-PIC transmission and power-efficiency. Finally, an electro-optical (EO) bandwidth at 1.25 V bias is measured above 28 GHz.

Classical beam line ion implantation is limited to low energies and cannot achieve P+/N junctions requested for Compared to conventional beam line ion implantation limited to a minimum energy implantation of 200 eV, plasma immersion ion implantation (PIII) is an emerging technique to get ultimate shallow profiles (as-implanted) due to no lower limitation of energy and high dose rate. On the another hand, laser thermal processing (LTP) allows to obtain very shallow junction with no TED, abrupt profile and activated depth control. In this paper, we show the implementation of the BF3 PIII associated with the LTP. Ions from BF 3 + plasma have been implanted in 200 mm n-type silicon wafers with energies from 100 eV to 1 keV and doses from 3E14 to 5E15 at/cm2 using PULSION® (IBS PIII prototype). Then, wafers have been annealed using SOPRA VEL 15 XeCl excimer lasers (l = 308 nm, 200 ns, 15 J/pulse) with energy density from 1 to 2.5 J/cm2 and 1, 3 or 10 shots. The samples have been characterized at CEA LETI by secondary ion mass spectrometry (SIMS) combined with four points probe sheet resistance measurements.

7th International Workshop on Plasma-Based Ion Implantation, San Antonio, TX, SEP 17-19, 2003; International audience; The efficiency of plasma immersion ion implantation (PIII) is no more to prove for the realization of ultra shallow junctions (USJ) in semiconductor applications. Interest for the fabrication of submicrometer CMOS devices is well known, but the ability of PIII to implant quickly high doses at very low energy and low price makes it a good candidate for the Fabrication of solar cells. In this paper, we present results obtained by a semi-industrial prototype of PIII (PULSION(R)) designed by the French company IBS. First, metallic contamination, homogeneity, reproducibility, and SIMS profiles of ultra shallow junctions made by PULSION(R) BF3 implantation on 200-mm silicon wafers are presented. Results are compared with BF2+ implantations made on an AXCELIS NV-8200P beam line implanter and demonstrate the compatibility with semiconductor requirements. Then, results on solar cells with BF3 shallow junctions made by PIII are presented. The simulated and measured internal quality factor (IQE) with an improved behavior in blue wavelengths demonstrates the interest of PIII for this applications field. (C) 2004 Elsevier B.V. All rights reserved.

Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration requirements, in particular for non-IC related technologies ones, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, micro lenses manufacturing. Actually complex 3D structures (pattern with several levels) requires either altering several steps of layering and etching or the use of complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheap and easy technique to achieve 3D structures. In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH …). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In this paper, we will present 2D and 3D structures obtained on silicon. The process scheme is described in figure 1, 2. In a first step a pattern is performed by nanoimprint lithography on a substrate (Figure 1a, 2a). Then ion implantation is realized through the (2D/3D) resist mask in order to create localized modifications in the material and transfer the pattern. The subjacent layer is protected partially or completely by the resist according to different levels of the pattern, so the ions are stopped differently, which makes the transfer possible. Finally, after the resist stripping (Figure 1b, 2b), a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one (Figure 1c, 2c). Many chemistries have been tested, the most efficient and selective one were silicon anodization in acid bath. The achieved selectivity comes from modifications induced into silicon during ion implantation. By using heavy ions, the material is amorphised, which has been confirmed by Raman spectroscopy. Despite this morphological defects, Scanning Spreading Resistance Microscopy (SSRM) shows that implanted areas has a lower resistivity than non-modified ones, which can be explained by the appearance of states in the forbidden gap of Si, generated by induced defects. Photoluminescence spectroscopy has been performed and bears out this idea. We also noticed, thanks to SSRM, a depletion zone in the interface between implanted and non-implanted Silicon which may guide electric field during the electrochemical process. All these elements makes the dissolution of implanted silicon more selective regarding non implanted one. The 3D structuring process that we are proposing leans on several parameters, some are related to dissolution mechanism like illumination, current and electrolyte composition, others concern ion implantation process such as type of ion, energy and dose, and finally lithography parameters for instance type and thickness of the resist. We will show that a key combination between all this parameters is required to achieve pattern transfer. Figure 1

The evolution of hydrogen-related defects introduced in the InP lattice due to the implantation and subsequent annealing is investigated as a function of the implantation temperature, that was varied from −15 °C to 230 °C. Implanted and annealed samples were analyzed by optical microscopy, SIMS and FTIR. The obtained results are discussed in terms of the formation of V In H x complexes that seems to be efficient H trapping centers, probably being the precursors of the fracture process in InP.

The doping of n-type silicon solar cells was investigated using two ion implantation techniques: beam line and plasma immersion. Initially we studied the effects of beam line ion implantation, where the dopants were activated by two different annealing routines. The first one used a single annealing to activate both B implanted emitter and P implanted back surface field (BSF), while the second one used two different annealing to separately activate the dopants. Good yield was reached with a record cell of 20.33% efficiency. Secondly, we investigated the doping by plasma immersion ion implantation with final objective of fabricate a solar cell fully doped by plasma.

This paper deals with the thermal and morphological stabilization of nickel-based silicides and germanides using tungsten and fluorine implantation for 3D monolithic CMOS applications. The incorporation of few % of W and/or F at various steps of the salicide process can successfully address two major issues: the morphological degradation (agglomeration) of NiSi and NiGe layers on one side and the Ge diffusion outside the active regions on the other side. The paper highlights cumulative effects of Pt alloying together with the incorporation of F and W for delaying at higher temperatures the agglomeration phenomenon. It also deals with the strong reduction of Ge diffusion using W and F implantation. Implantation conditions (dose, energy) and schemes (implantations prior metal deposition, after metal deposition, into the silicide) are discussed.

4H-SiC p+n photodiodes based on ultrathin-junctions have been fabricated with distinct processes for the p+-region creation: either with Aluminium conventional ion implantation, or with Boron Plasma Ion Immersion Implantation. Spectral sensitivity measurements were performed at several temperatures from room temperature up to 340°C, with incident wavelengths ranging from 200 to 400 nm. Both responses are characterized by a stability between 200 and 270 nm, and a important increase with temperature between 270 and 380 nm. This fact has to be related to the two different kinds of optical absorption phenomena in SiC with respect to the wavelength, which are direct and indirect (phonon assisted) transitions. When decreasing the temperature, we noticed a hysteresis effect, which could be due to charge trapping by temperature activated defects. After strong proton and electron irradiations, the diodes showed a stability of the response below 270 nm, making them suitable for use in harsh environments. Simulation was performed at room temperature, with a good correlation between simulated and experimental room temperature curves.

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.

SiliconPV: March 25-27, 2013, Hamelin, Germany; International audience; The aim of the study was to develop a very simple process for the fabrication of large area n-type PERT cells by means of ion implantation. We showed an improvement of the implanted boron activation rate with the annealing temperature by comparing boron SIMS and ECV concentration profiles. A direct positive impact on the boron emitter saturation current density (J 0e) was measured. We also investigated the effect of varying the oxidation conditions during the annealing on the implanted boron emitter and the phosphorus BSF quality. Low emitter saturation current density (J 0e) of 131 fA/cm 2 was measured on textured surfaces, close to the value obtained with diffused B-emitters. A process flow was developed leading to an average efficiency of 19% on 239 cm 2 bifacial solar cells, using only eight processing steps with two implantations and one activation annealing.

International audience; A comparison is made between two kinds of Nitrogen implantations for the formation of thin n+p junctions in p-type Silicon Carbide (SiC) epitaxial layers. The standard beam ion implantations and PULSIONTM processes were performed at two distinct energies (700 eV and 7 keV) and the subsequent annealing was held at 1600°C in a resistive furnace specifically adapted to SiC material. Positron Annihilation Spectroscopy (PAS) and unpolarized infrared reflectivity (IR) measurements were carried out before and after the annealing, respecively. Despite the presence of deep vacancy clusters near the as-implanted sample surfaces, no extended defects were detected after the annealing. Plasma implanted samples prove to contain a lower point defect concentration than beam implanted samples. The concentration of these defects (resulting from plasma process) is higher in the plane parallel to the optical axis, which denotes an energy spreading alongside the dopant distribution.

International audience; This paper deals with the study of the photoresponse properties of 4H-SiC UV-photodetector devices based on a thin junction following their testing in darkness and under UV light over the 200 to 400 nm range. An increase of the carrier harvesting for low implanted layer thickness was shown by simulation. Thus, an implantation at low energy (27 keV) was carried out on our samples. Because of the thin junction architecture, the photocurrent at 280 nm was found to be four orders of magnitude larger than the dark current. A spectral responsivity of our photodetectors shows a peak at 280 nm with a value of 0.03 A/W.

Here, we present and discuss the electrical characteristics of fully depleted MOSFET transistors of planar and tridimensional architecture, doped by Plasma Immersion Ion Implantation (PIII) or Beam Line Ion Implantation (BLII). Both techniques delivered similar and satisfactory results in considering the planar architecture. For tri-dimensional Tri-Gate transistors, the results obtained with PIII are superior.

International audience; This paper focuses on the formation of thin n+p junctions in p-type Silicon Carbide (SiC) epitaxial layers using two kinds of Nitrogen implantations. The standard beam ion implantations and PULSIONTM processes were performed at two distinct energies (700 eV and 7 keV), and the subsequent annealing was held at 1600°C in a resistive furnace specifically adapted to SiC material. No measurable electrical activity was obtained for both implantations performed at 700 eV, due to some outdiffusion of N dopants during the annealing despite a low surface roughness (rms ~ 1.4 nm) and no residual damage detected by RBS/C. A higher sheet resistance was measured in plasma-implanted samples at 7 keV (in comparison with beam-line implanted samples), which is partly related to N outdiffusion. The profiles of N atoms beam-implanted at 7 keV are not affected by the annealing. The corresponding electrical activation is fully completed.

In this paper, we deal with the study of Ultra Violet (UV) photodetector device based on SiC material undergoing a p-i-n structure process. Current density-voltage (J-V) measurements in reverse and forward bias, are performed on the UV photodetector device. Due to a very thin p+-type doping layer, a high reactivation annealing and the metallic contact deposit, experimental measurements point out Junction Barrier Schottky (JBS) device behaviour in spite of the p-i-n structure device process. To understand this involuntary phenomenon, these experimental characteristics are accompanied with an experimental study by the SIMS analysis.

For continued scaling of future CMOS devices (sub-32 nm), heavily-doped ultra-shallow junctions are required. Plasma doping (PD) with PULSION® offers the attractive capability of high dose and low energy doping with short production times [1, 2]. All of these aspects make plasma doping a good candidate for the next technology steps driven by the roadmap. In this paper we discuss the integration of plasma doping into a Fully Depleted SOI CMOS process flow (sub-10 nm top Si layer). The compatibility of PD with patterns (charging effects) has been studied as well as the Selective Epitaxial Growth (SEG) performed after the source/drain extension implantations to thicken these regions prior to silicidation [3].

We report on Ga-doped 3C-SiC epitaxial layers grown on on-axis (0001) 6H-SiC substrates using the vapor-liquid-solid technique and different Si1-xGax melts. The resulting samples have been investigated using secondary ion mass spectroscopy (SIMS), micro-Raman spectroscopy (mu-R) and, finally, low temperature photoluminescence (LTPL) spectroscopy. From SIMS measurements we find Ga concentrations in the range of 10(18) cm(-3), systematically accompanied by high nitrogen content. In good agreement with these findings, the mu-R spectra show that the Ga-doped samples are n-type, with electron concentrations close to 2x10(18) cm(-3). As expected, the LTPL spectra are dominated by strong N-Ga donor-acceptor pair (DAP) transitions. In one sample, a weak additional N-Al DAP recombination spectrum is also observed, showing the possibility to have accidental codoping with Ga and Al simultaneously. This was confirmed on a non-intentionally doped 3C-SiC (witness) sample on which, apart of the usual N and Al bound exciton lines, a small feature resolved at 2.35 eV comings from neutral Ga bound excitons. Quantitative analyses of the DAP transition energies in the Ga-doped and witness sample gave 346 meV for the optical binding energy of Ga acceptors in 3C-SiC against 251 meV for the Al one. The conditions for the relative observation of Ga and Al related LTPL features are discussed and the demonstration of room temperature luminescence using Ga doping is done. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3455999]

Thanks to the European Project SEA‐NET, an industrial version of the IBS Plasma Ion Implantation tool has been installed in LETI for the fabrication of Ultra‐Shallow Junction for 45 & 32 nm CMOS on 200 and 300 mm wafers. In this study, we present first doping results on 300 mm wafers using BF3 plasma. Annealing after PULSION implantation is perfomed by the ASM furnace LEVITOR. This tool, which works on conduction heating is emissivity independent for temperature control and allows reaching high ramp up and ramp down speeds (up to 900 °C/s). Main characteristics of as implanted wafers are presented (metal contamination 2E10/cm2, SIMS depth profiles down to 5 nm). Then the effect of convection gas in the annealing process on sheet resistance, junction depth and uniformity is presented.

This work demonstrates the efficiency of a Germanium and Carbon co-implantation that suppresses the Boron Transient Enhanced Diffusion, enhances Boron activation and enables large improvement of Short Channel Effects in PMOS devices while maintaining drive current performances. We present here 65/45nm node devices on conventional bulk substrates featuring Germanium and Carbon engineered shallow junctions that enable to reduce the Drain Induced Barrier Lowering compared to devices implanted only with Boron. This improvement is attributed to the suppression of Boron channelling with Ge pre-amorphization (PAI), and to the reduction of Boron TED due to the trapping of interstitial defects by Carbon with Germanium PAI.

Boron and more recently BF2 implantation are commonly used in production to achieve ultra shallow P+/N junctions. Very low energy implantation is needed for Boron and then specific ultra low energy implanters are necessary. Several studies have shown that Fluorine enhances Boron diffusion through the gate oxide and then BF2 is not so favorable. BCl2 implantation showed the interest of its high atomic mass to get shallow Boron as implanted profile, so that higher energy is needed to achieve the same depth. In this paper we show the implementation of the BCl2+ implantation process on a medium current implanter. BCl2 have been implanted with energies from 8 keV down to 3 keV with doses of 5e13 to 1e15 at/cm2. Such kind of implantation energy is equal to a 1.1 keV down to 400 eV Boron implant equivalent energy and p+/n junction can reach the 50nm ITRS node. SIMS characterizations combined with sheet resistance 4-point probe measurements shows very interesting result in terms of Xj vs. Rs criteria for the junction. Polysilicon gate implantation has also been done to look at the chlorine effect on Boron diffusion through the gate oxide. Defect in c-Si injected during implantation step is much higher with the high effective mass of this cluster ion, and amorphisation occurs with doses close to 2e14 at/cm2. Therefore the annealing step is regarded as a key point to restrict the Boron diffusion. Spike anneal activation as well as curing furnace anneal are also addressed here for BCl2.