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Author(s): Tobias Schaetz One of the goals most eagerly pursued by physicists is the development of a universal quantum computer -- a machine capable of running a superposition of many [...]

A generalized temperature-dependent channel backscattering extraction method that could self-consistently determine the temperature sensitivity of the low-field mobility and the critical length in nanoscale MOSFETs is reported. The efficient temperature-dependent method could be used in technology development for the process of monitoring purpose.

Varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration are employed to analyze strained pseudomorphic Si/[Si.sub.1-x][Ge.sub.x]/Si gate-controlled band-to-band tunneling (BTBT) devices. The results showed that the switching characteristics of TFETs could be significantly improved by controlling the strained-SiGe bandgap of 0.55 eV.

A detailed study of gate length scalability and device performance of undoped-body with extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates is presented. The results demonstrated that the improvement of short channel characteristics leads to higher drive current [I.sub.DSAT] and lower extrinsic gate delay CV/I at a fixed OFF-state current [I.sub.OFF].

A newly developed noniterative physics-based compact model for carbon nanotube (CNT) transistor and interconnect which supported early stage design exploration and accurately predicted both I-V and C-V characteristics is described. The developed model served as one of the most important bridges between CNT processes and design and give key insights into the development of CNT-based electronics.

The article studies the performance and dependability of gold (Au) and platinum (Pt) single-layer nanocrystal (NC)-based Flash memory devices for NAND application using CMOS-compatible process flow. Findings reveal that annealing-temperature-dependent gate is practical in Au devices using analytical methods.

The article studies the physics-based model of TANOS memory programming transients in Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. Findings further highlight the valid contribution for the investigation of the achievable performances of the TANOS technology.

The article studies the role of gate disturbs and data retention optimization on scaling of flash cell spacer. Findings reveal that quality of spacer can improve the data retention and reduce gate disturb.

The effect of gate-tunneling leakage in the MOS capacitor on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology is examined. The MOS capacitors with different oxide thicknesses are used for examining their affect on the PLL performance and the locked time, static phase error and jitter of the second-order PLL are degraded by the gate-tunneling of the MOS capacitor used in the loop filter.

The program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for NAND application is examined. The IPD current blocking ability is quantified that is required for future scaled FG memory cells.

The characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-[Al.sub.2][O.sub.3] gate dielectrics are examined. The studies have shown that the relatively inferior n-FET has resulted from the larger source/drain contact resistance, higher surfaces states scattering, and lower substrate-doping concentration.

The experimental hole gate direct tunneling current of p-MOSFETs are described under shallow trench isolation (STI)-induced longitudinal compressive stress, which has not followed the trend caused by the strain-altered valence-band splitting alone. The strain-retarded oxide growth rate has enhanced hole direct tunneling and has reversed the conventional trend due to the strain-altered valence-band splitting.

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are described and the structure is characterized by a compound buried layer (CBL) made of two layers and a polysilicon layer between them. The maximal temperature of CBL SOI is reduced by 25 K because of a window in upper buried oxide (UBO) when compared with the conventional SOI.

The length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are examined. The compressive stress from the SiGe S/D has dominated the LOD effect for dummy poly gate located outside the active area, whereas the LOD effect is controlled by the SiGe S/D stress within the dummy gate and the STI stress for dummy poly gate located within the active area.

Millisecond Flash anneal (MFLA) is demonstrated on a matured DRAM product for gate-induced drain leakage (GIDL) improvement, while examining the device impact and junction defects. Bright field and weak-beam dark-field TEM images has showed perfect dislocation loops and fault dislocation loops staying in the {113} plane and these defects might be the one of the leakage sources for a defect-assisted trap charge, leading to trap-assisted tunneling.

The effect of controllable process parameters such as metal-gate physical thickness and interfacial-layer-formation method on the electrical and structural properties of TiN/Hf[O.sub.2]/Si[O.sub.2] gate stacks is studied. Hf-rich chemical interfacial oxides have not degraded the device performance and a small reduction in transconductance is seen for physically thinner interfacial layers.