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By virtue of hardware parallelism, ternary content addressable memory (TCAM) is attractive for low-latency search for packet forwarding in routers for network communications in the upcoming fifth-generation (5G) era. However, the demand for high-density TCAM encounters remarkable costs in silicon area and power consumption. In this work, a 16-kb nonvolatile ternary content addressable memory (nvTCAM) test chip based on resistive memory (ReRAM) is demonstrated in 28-nm process with two techniques to deal with the aforementioned issues. First, the crossbar array with 2-diode-2-ReRAM (2D2R) nvTCAM cell is proposed to realize $>3\times $ improvement in storage density. The back-end-of-line integration of both diode and ReRAM resistor also allows for further 3-D stacking to realize larger storage density. Second, the machine learning concept is exploited to realize intelligent search operation. ${K}$ -means clustering is employed to allocate the entry storage and then the search of destination IP address can be targeted to a specific bank for low power. The evaluation shows >70% reduction in search energy with 2% overhead in silicon area for bank count of four. The test chip also achieves a match delay of 2 ns under nominal operating conditions.

This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, i.e., 4T2C, for minimal area penalty and full logic compatibility. The FeCAP with 10-nm-thick Hf0.5Zr0.5O2 film shows excellent ferroelectricity (Pr $= 15\,\,\mu \text{C}$ /cm2) and good memory characteristics (cycles $> 10^{11}$ ). The 4T2C nvSRAM is capable of storing and restoring previous memory states for nonvolatile data storage. To compensate the leakage current in the dynamic nodes of 4T load less SRAM, we propose a dynamic current compensation operation scheme by exploiting the polarization-dependent leakage current of FeCAP. Outstanding characteristics were achieved in this nvSRAM cell: 1) elimination of the dc path; 2) ultralow store and restore power consumption; and 3) high area efficiency.

Resistance fluctuation is a big concern of resistive random access memory (RRAM) since it has close connection with chip design. In this work, resistance fluctuation of RRAM devices fabricated on 28-nm CMOS platform is investigated systematically by means of low frequency noise measurement. The relationship among resistance fluctuation and resistance states/reading time/ reading conditions is quantitatively analyzed. We show that the resistance broadening has positive correlation with resistance states and reading time. Meanwhile, for reading voltage, it should be selected below 0.3V in order to avoid resistance degradation. Based on this quantitative analysis, an analytical formula to predict the resistance spread as a function of time, resistance, read voltage is derived. This prediction result provides a valuable guideline for selection of resistance working range and read pulse parameter, which is of great importance for future circuit design.

In this letter, the endurance property of Hf0.5Zr0.5O2(HZO) based ferroelectric capacitor has been improved using Ru electrodes. Compared to the widely used TiN/HZO/TiN capacitor, the Ru/HZO/Ru capacitor shows comparable remnant polarization ( ${\sim }20~\mu C/cm^{2}$ ), lower leakage current ( $5.67\times 10^{-5}A/cm^{2}$ ) and higher breakdown electric field (~4 MV/cm) at room temperature. The reduction of the leakage current and the enhancement of the breakdown electric field, which are ascribed to the small number of defects and vacancies in HZO thin films with Ru electrodes, prompt the endurance improvement of HZO-based capacitor from $3\times 10^{10}$ cycles for TiN electrodes at 3 MV/cm to more than $1.2 \times 10^{11}$ cycles for Ru electrodes at 3.5 MV/cm. This work provides an effective way to reduce the leakage current and improve the endurance property of HZO-based capacitors.

In this letter, trench-gate metal–oxide–semiconductor field-effect transistors on (010) $\beta $ -Ga2O3 epitaxial layer are fabricated. Enhancement mode is achieved by the gate-recess process, through thoroughly depleting the $\beta $ -Ga2O3 channel to get a positive threshold voltage. For the first time, by using a dynamic parameter test system, the Ga2O3 MOSFET with 2- $\mu \text{m}$ gate length is characterized to present short switching time, including turn-on time ( $\textit {t}_{ \mathrm{\scriptscriptstyle ON}}$ ) of 28.6 ns and turn-off time ( $\textit {t}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of 94.0 ns. In addition, OFF-state interelectrode parasitic capacitances, including input capacitance ( $\textit {C}_{\text {iss}}$ ) of 37 pF/mm, output capacitance ( $\textit {C}_{\text {oss}}$ ) of 42 pF/mm, and reverse transfer capacitance ( $\textit {C}_{\text {rss}}$ ) of 14 pF/mm are also obtained, which can account for the high switching speed. The static and dynamic switching properties of the trench-gate device show the potential of $\beta $ -Ga2O3 MOSFET for the high-speed switching applications.

In this letter we present a high performance $\varepsilon $ -Ga2O3 solar-blind photodetector (SBPD) with asymmetric Schottky electrodes. The $\varepsilon $ -Ga2O3 films were heteroepitaxially grown on ${c}$ -plane sapphire by metal-organic chemical vapor deposition (MOCVD). The SBPDs were fabricated in the form of lateral interdigitated Schottky electrodes composed of a Pt/Ti/Au metal stack and a Ti/Au metal stack. The SBPD shows a rectification ratio of ~ 102 with low dark current of 25 pA at ${V} = {6}$ V. A high photo-to-dark-current ratio of ${5.7}\boldsymbol {\times }{10}^{{4}}$ under 254 nm light illumination was measured. Furthermore, the SBPD exhibits an ultrahigh detectivity and external quantum efficiency of ${4.2}\boldsymbol {\times }{10}^{{14}}$ Jones and ${4.1}\boldsymbol \,\,{\times }\,\,{10}^{{4}}$ %, respectively. Most importantly, the SBPD possesses an ultrahigh responsivity of 84 A/W with a fast response speed of 100 ms, suggesting the promise of $\varepsilon$ -Ga2O3 in the future photodetector applications.

An enhancement-mode $\beta $ -Ga2O3 metal–oxide–semiconductor field-effect solar-blind phototransistor on Si-doped homoepitaxial film grown by molecular beam epitaxy is demonstrated in this letter. Gate-recess process was employed to fully deplete the Ga2O3 channel to achieve positive threshold voltage ${V}_{{\textsf {th}}}$ (7 V), which broadens the operating range of the solar-blind phototransistor. The dark current of about 0.7 pA is extremely low. Under 254-nm light illumination of 63 $\mu \text{W}$ /cm2, the change of drain current reaches more than 6 orders of magnitude. Record high detectivity of 1.3 $\boldsymbol {\times }\,\,10^{{\textsf {16}}}$ Jones and photo-to-dark current ratio of $1.1\,\,{\boldsymbol {\times }}\,\,10^{{\textsf {6}}}$ are obtained, respectively. In addition, the rise and decay time are as short as 100 and 30 ms, respectively. High responsivity of $3\,\,\boldsymbol {\times }\,\, 10^{{\textsf {3}}}$ A/W and external quantum efficiency of $1.5\,\,\boldsymbol {\times }\,\,10^{{\textsf {6}}}$ % are also achieved with apparent solar-blind photodetection.

The 3D crossbar arrays provide a cost-effective approach for high-density integration of resistive switching random-access memory (RRAM). A selector device or self-selective cells can be used to inhibit the sneaking current from the unselected cells. The coexistence of memory switching (MS) with inherent nonlinearity and threshold switching (TS) with high current density in an individual material system will lead to technological benefits for memory integration and neuromorphic computing. However, the reported conductive filament (CF)-type MS and TS combining devices cannot meet the requirements for practical applications, as these devices lack built-in nonlinearity in memory mode and display low current density and large relaxing time in the selector mode. In this letter, we report a 3D TiN/TiO2/NbOX/Pt device with MS and TS before and after the forming processes. In the MS mode, this device shows >50 nonlinearity, a 100 ON/OFF ratio, non-volatility, and stable homogeneous switching due to vacancy redistribution. In the TS mode, owing to the metal–insulator transition, a high ON-state current (1.6 MA/cm 2), high switching speed (

Ferroelectric materials with a perovskite structure have various shortcomings, including poor Si compatibility, large physical thickness, and small bandgap. HfO2-based ferroelectric materials provide a new solution for ferroelectric semiconductor devices. HfO2-ZrO2 solid solution (HZO) thin films have been widely studied due to their low crystallization temperature and wide stoichiometric range. Considering its low cost and flexible deposition conditions, the sputtering technique is a useful method for HZO deposition. However, sputtered HZO ferroelectric films have been rarely reported, and the composition effect on the ferroelectric properties of HfXZr1−XO2 thin films is still unclear. In this letter, sputtered HfXZr1−XO2 thin films were studied with different Zr contents (from 12.49 to 20.34 mol%) by varying the sputtering power ratio of ZrO2 to HfO2. We found that the dopant concentration with the best ferroelectric properties in the HfXZr1−XO2 system is ~15–16 mol%, which is much lower than that in the ALD-based HZO film. First-principle calculation shows that oxygen vacancies doped in the HZO film lead to a change in the Helmholtz free energy of different phases, which affected the optimal Zr concentration for the largest ferroelectric polarization.

Bi-layer structure has been widely adopted to improve the reliability of the conductive bridge random access memory (CBRAM). In this work, we proposed a convenient and economical solution to achieve a Ta2O5/TaOx bi-layer structure by using a low-temperature annealing process. The addition of a TaOx layer acted as an external resistance suppressing the overflow current during set programming, thus achieving the self-compliance switching. As a result, the distributions of high-resistance states and low-resistance states are improved due to the suppression of the overset phenomenon. In addition, the LRS retention of the CBRAM is obviously enhanced due to the recovery of defects in the switching film. This work provides a simple and economical method to improve the reliability of CBRAM.

To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaO x /Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications.

Ferroelectric capacitors (FeCAPs) with high process compatibility, high reliability, ultra-low programming current and fast operation speed are promising candidates to traditional volatile and nonvolatile memory. In addition, they have great potential in the fields of storage, computing, and memory logic. Nevertheless, effective methods to realize logic and memory in FeCAP devices are still lacking. This study proposes a 1T2C FeCAP-based in situ bitwise X(N)OR logic based on a charge-sharing function. First, using the 1T2C structure and a two-step write-back circuit, the nondestructive reading is realized with less complexity than the previous work. Second, a method of two-line activation is used during the operation of X(N)OR. The verification results show that the speed, area and power consumption of the proposed 1T2C FeCAP-based bitwise logic operations are significantly improved.

High-density embedded nonvolatile memory (eNVM) at advanced technology nodes is still in great demand for SOC chips used in consumer electronics, self-driving cars, industrial control, and IoT edge devices. Although embedded NOR Flash is still main stream, its process complexity and high integration cost make it difficult to scale beyond 28nm. RRAM has become a promising alternative owing to its excellent scalability, low power, and compatibility with logic processes [1 –6]. However, several challenges still exist that restrict RRAM from practical eNVM applications, as shown in Fig. 24.2.1. 1) a high supply voltage is needed, because of high operation voltages and a considerable voltage drop on write path. 2) The IR drop on write path varies significantly with the distance of a cell from the peripheral circuits. 3) Prior self-write termination (SWT), with its abrupt cutoff, fails to form dense conductive filaments (CFs). While delayed termination helps to alleviate this issue, its delay time is not optimized for fast and slow cells [3]. 4) Previous read reference schemes that use a small number of HRS/LRS cells may collapse when encountering tail bits, resulting in a poor reference [6]. In this work, we demonstrate a 1Mb 14nm-FinFET RRAM with a $0.022 \mu m^{2}$ cell size. The cell array is in a deep N-well with adequate P-substrate biasing to alleviate the difficulty of high voltage transfer. Placing the bit line (BL) and source line (SL) drivers on the top and bottom of the array reduces the IR-drop variation for near and far cells. Self-adaptive delayed termination (SADT) adjusts the termination time according to cell characteristics (fast or slow), helping to generate robust CFs. A read reference with multiple dummy 1T1R cells avoids the reference collapse issue. The test chip supports reliable read operation at a minimum supply voltage of 0.5V from $-40^{\circ}C$ to $125^{\circ}C$.

The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

In this work, we propose and demonstrate a multi-layer 3-dimensional (3D) vertical RRAM (VRRAM) PUF with in-cell stabilization scheme to improve both cost efficiency and reliability. An 8-layer VRRAM array was manufactured with excellent uniformity and good endurance of >107. Apart from the variation in RRAM resistance, enhanced randomness is obtained thanks to the parasitic IR drop and abundant sneak current paths in 3D VRRAM. To deal with the common issue of unstable bits in PUF output, in-cell stabilization is proposed by first employing asymmetric biasing to detect the unstable bits and then exploiting reprogramming to expand the deviation to stabilize the output. The bit error rate is reduced by >7X (68X) for 3(5) times reprogramming. The proposed PUF features excellent resistance against machine learning attack and passes both National Institute of Standards and Technology (NIST) 800-22 and NIST 800-90B test suites.

RRAM suffers from poor retention with short-term memory time when using low compliance current for programing. However, the short-term memory time exhibits ideal randomness, which can be exploited as an entropy source for physically unclonable function (PUF). In this work, we demonstrated a novel PUF utilizing the stochastic short-term memory time of oxide-based RRAM. The proposed PUF was implemented on a 256Kb HfO 2 /WO x bilayer RRAM test chip in 0.13μm logic process. The RRAM PUF is capable of regenerating >1020 times after 10 years@115°C and the bit error rate (BER) remains

To address the failure mechanisms in ferroelectric devices, this work presents a systematical study on Hf 0.5 Zr 0.5 O 2 -based ferroelectric memory. Firstly, by detail electrical characterizations of P-V and C-V curves in field-cycled devices, three dominant failure modes can be well distinguished. Then, by combining the TDDB measurements and first-principles calculations, it is found that, 1) the annealing temperature has large impacts on the initial defects concentrations while weakly affect the trap generation rate; 2) the breakdown paths take place mainly in the amorphous regions, which could generate reconfigurable filaments and cause RRAM properties; 3) temporary recovered ferroelectricity during cycling can be explained by considering the unstable breakdown paths generated at the grain boundary.

For the first time, the oxide based resistive random access memory (OxRRAM) integrated at 14nm FinFET platform was demonstrated. The scalability potential towards 10nm and beyond was analysis by considering the programing voltage, current and stability factors. Negative bias scheme with deep N well was proposed to solve the voltage mismatch between the OxRRAM and transistor. In order to meet the product-level stability requirement, the operation current was suggested to be higher than 100uA. Based on such constrain, cell size at different technology is projected. As an attempt, a design rule and array architecture was proposed to implement the OxRRAM on 5nm FinFET platform.

Von Neumann computing architecture system has the characteristic of high energy consumption and slow speed due to the memory bottlenecks of hardware platforms when it processes computing tasks that rely on big data. The drawbacks of memory bottlenecks in traditional structures can be improved significantly using PIM (processing-in-memory) architectures. FeRAM (ferroelectric memory) is a novel memory with the advantages of simple structure, high integration and low power consumption. Thus, it has always been considered as one of the most proper memories for PIM. In this paper, FeRAM was designed as memory and converted to basic computing cells, based on its charge sharing function. A mechanism of two-line activation was adopted during the process of X(N)OR. Then, peripheral circuits were moderately modified to implement bit-by-bit X(N)OR operations between operands stored in the same bit line. Besides, the simulation of X(N)OR logic was carried out. The final simulation results show that the speed, area and power consumption of current FeRAM-based logic operations are improved. The research can be used to enhance the performance of arithmetic logic units for future PIM.

Power consumption is an essential issue in nano CMOS integrated circuits. The power-off operational mode and low-voltage circuits have proposed to reduce energy dissipation. Due to the compatibility of Hf02 ferroelectric capacitors (FeCAP) with CMOS process, FeCAP have been restudied as nonvolatile memory. In this paper, we proposed novel full logic compatible 7T1C nonvolatile static random-access memory (nvSRAM) based on FeCAP. The proposed memory cell consists of a traditional 6T SRAM core and a FeCAP circuit (1TIC) nonvolatile memory cell, making a 7T1C a scheme. The proposed novel 7T1C nvSRAM cell offers better performance when compared with the exiting nonvolatile nvSRAM cell. The direct current (DC) path is eliminated, and the static power consumption of SRAM is reduced. The power consumption of store, and restore is reduced and the speed is increased. Restore mode operation destructively reads data and does not need to write the data back to SRAM.

For the first time, 1T2R RRAM cell using PMOS selector is proposed and demonstrated with improved reset voltage and high density for embedded NVM. Hierarchical bit line and 3-state cell storage confine the associated sneaking current locally within a small zone and further suppress it by >90%. Self-adaptive write driver with current limiter and sneaking current compensator realizes power saving and accurate current compliance for set. To suit PMOS selector, reverse read using current sensing with dummy reference brings fast and reliable read. A 1.5Mb RRAM test chip in 28nm improved the record storage density by 40% to 14.8 Mb/mm2. Reliable read is performed at low VDD of 0.6V@(−40, 125)°C.

In this work, we demonstrated a novel true random number generator (TRNG) utilizing stochastic short-term recovery of Charge- Trapping (CT) FinFET devices. The true random bits were generated by measuring the recovery time of CT-FinFET with a digital counter by a time-to-digital count converter (TDCC) unit. The resulting CT - TRNG circuit shows great immunity against a power noise of up to 600m V in amplitude and up to 1.5G Hz in frequency across a wide range of temperatures (-20 to 85°C). It passed all NIST 800–22 and NIST 800-90B randomness tests. We have shown this novel CT - TRNG to be the most promising high-reliability hardware security solution to date.

Carbon (C)-doped Ge2Sb2Te5 material is a potential candidate in phase change random access memory (PCRAM) because of its superb thermal stability and ultrahigh cycle endurance. Unfortunately, the r...

Ubiquitous artificial intelligence (AI) applications call for increasing computing power and large communication bandwidth, which are challenging to meet given the diminishing benefits from traditional planar CMOS scaling. Three-dimension (3D) integration of integrated circuits (IC) promises to achieve further performance improvements at reduced power and smaller footprint. Here, we report a 3D array of 8 layers of field-programmable ferroelectric diode (FPD) for binary convolutional neural network (BCNN) in energy-efficient AI applications. The convolutional kernels are duplicated and stored in the pillars in 3D FPD array to providing high computation parallelism. An AND-based logic using FPD is proposed to realize the XNOR function in BCNN. As a proof-of-concept demonstration, a BCNN is constructed based on the 3D FPD array for MNIST test and qualified to present the advantages of our proposal in 28nm logic process design kit.