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Micro-electro-mechanical (MEM) switches show promise for ultra-low-power computing since they can operate with negligible subthreshold leakage current. A principal challenge for MEM switch design is to achieve low pull-in voltage (V pi ) for low-power device operation. Usually this requires low structural stiffness (k), small as-fabricated actuation gap thickness (g), and large actuation area (A). However, assuming the difference between the actuation gap and contact gap is small, such a design has low spring restoring energy (∼0.5kg2) and hence is susceptible to stiction-induced failure. To alleviate this challenge, we propose, simulate and analytically model a new MEM actuator design that incorporates a structure with negative stiffness, that is, a buckling fixed-fixed beam. Prior work has leveraged residual stress (σ o ) in thin films to create buckled structures for memory devices, pressure sensors, and microactuators [1]-[3]. A compensated spring system that combines a negative stiffness spring with a positive stiffness spring to lower the actuation force has been proposed and demonstrated in large-scale vibration isolators [4]-[6]. However, to the authors' knowledge this method has not yet been applied to MEM switches.

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy-performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/2)(Seff/Soff) - 0.56(Son/Soff) - 0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy-delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology.

Microelectromechanical relays have recently been proposed for ultra-low-power digital logic because their nearly ideal switching behavior can potentially enable reductions in supply voltage (Vdd) and, hence, energy per operation beyond the limits of MOSFETs. Using a calibrated analytical model, a sensitivity-based energy-delay optimization approach is developed in order to establish simple relay design guidelines. It is found that, at the optimal design point, every 2 X energy increase can be traded off for a ~1.5x reduction in relay delay. A contact-gap-to-actuation-gap thickness ratio of 0.7-0.8 is shown to result in the most energy-efficient relay operation, implying that pull-in operation is preferred for an energy-efficient relay design. Based on the analytical model and design guidelines, a scaling theory for relays is presented. A scaled relay technology is projected to provide >; 10 X energy savings over an equivalent MOSFET technology, for circuits operating at clock frequencies up to ~100 MHz.

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

Power density has grown to be the dominant challenge for continued complementary metal-oxide-semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applications. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical switches, with particular emphasis on electromechanical relays since they are among the most promising for IC applications. Relay reliability and process integration challenges are discussed. Demonstrations of functional relay logic circuits are then presented, and relay scaling for improved device density and performance is described. Finally, the energy efficiency benefit of a scaled relay technology versus a CMOS technology with comparable minimum dimensions is assessed.

The Euler-Bernoulli beam equation is solved simultaneously with the Poisson equation in order to accurately model the switching behavior of nanoelectromechanical field-effect transistors (NEMFETs). Using this approach, the shape of the movable gate electrode and semiconductor potential across the width of the channel are derived for the various regimes of transistor operation (before gate pull-in, after gate pull-in, and at the point of gate release). The impact of various transistor design parameters such as the body doping concentration, gate work function, gate stiffness, and as-fabricated actuation gap thickness, as well as source-to-body bias voltage and surface forces, on the gate pull-in and gate release voltages are examined. A unified pull-in/release voltage model is developed to facilitate NEMFET design for digital- and analog-circuit applications.

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

One of the criteria often overlooked in the adoption of any technology is the cost viability of that technology at scale. In the case of the semiconductor industry, it was born out of the need for a cost-effective computing solution to replace unsustainable predecessors that used mechanical parts [1], magnetic relays [2], and vacuum tubes [3]. The industry’s more recent success can be traced back to the early 1970s when the industry began to transition from bipolar junction transistors (BJTs) to metal-oxide-semiconductor field-effect transistors (MOSFETs). Despite producing relatively slower transistors, MOSFET technology offered a lower power alternative that required a lower complexity and integration-friendly manufacturing process [4]. This transition to MOSFETs, and subsequently complementary metal-oxide-semiconductor (CMOS) technology, enabled the dramatic transistor scaling of the last several decades that has not only shrunk manufacturing cost but also yielded improvements in performance and functionality with each new technology generation. Combined with advancements in integrated circuit design, CMOS scaling has reduced the cost of data collection, computation, and communication such that it has fueled the adoption of electronics across an increasingly broad spectrum of applications [5].

In this chapter, we first review various process integration issues for micro-relay fabrication, followed by a detailed discussion of the prototype relays fabricated using a CMOS-compatible poly-Si0.4Ge0.6 surface micromachining process. We also present the results of various prototype relay technologies recently developed in various research laboratories.

This chapter begins with a detailed analysis on the design and modeling varies micro-relays. Analytical formulations for the switching voltages, spring design and modeling, and the dynamic behavior of micro-relays are established. These delay and energy models are then used for relay energy-delay optimization and scaling in Chap. 5.

In this chapter, we provide a general overview and initial measurement studies of various failure modes for micro-relays, including structural fatigue, dielectric charging, contact surface oxidation, and welding-induced failure. We then use these results to establish the micro-relay design guidelines for applications such as digital logic and CMOS power gates.

In the previous chapter, we investigated the viability of micro-relays as a general building block for circuit design. In the process, we developed some underlying principles about how to best utilize micro-relay devices to take advantage of their strengths while mitigating their weaknesses. In this chapter, we make use of these design principles and apply them to various circuit building blocks commonly used in VLSI systems. In particular, this chapter focuses on circuit and micro-architecture design using micro-relays. Rather than rehash the volumes of CMOS literature on each topic, only relevant context and differences with respect to CMOS designs are highlighted. We also provide some comparisons with respect to CMOS performance for the resulting circuits. In addition, some of the obstacles for enabling modern automated design flows using micro-relays are addressed.

This chapter begins with general overview of the relay energy-delay optimization, followed by a sensitivity-based energy-delay optimization methodology. We establish simple relay design guidelines and examine the implications of scaling relay devices using the proposed design methodology. We also show that in a manner highly analogous to MOSFET scaling, dimensional scaling can be applied to relays to improve device density, switching delay, and power consumption.

Four-terminal-relay inverter circuit characteristics are investigated. To achieve maximum noise margin and zero crowbar current while allowing for relay-to-relay variations, the optimal biasing scheme provides for switching that is symmetric about VDD/2 with minimum hysteresis and no possibility of both the pull-down and pull-up devices being on simultaneously.

Various logic functions can be implemented by appropriately biasing a single seesaw relay. The seesaw relay can also be configured as a bistable latch so that a memory cell can be implemented with one relay and one access transistor. Measurements of seesaw relay switching speed are well matched to lumped-parameter modeling results.

A dual-ended (?seesaw?) relay design is proposed for ultralow-power digital logic applications. Fabricated seesaw relays demonstrate a perfectly complementary switching behavior that is symmetric about V DD/2, with extremely steep switching behavior (< 0.1 mV/dec) and low on -state resistance (< 1 k?). The perfectly complementary and symmetric operation provides for maximum operating voltage margin and minimal crowbar current, as evidenced by an abrupt inverter voltage transfer characteristic.

Fundamental energy-efficiency limits for transistor-based digital logic circuits have led to renewed interest in micro-electro-mechanical (MEM) switches [1-12] because they have the ideal characteristics of zero off-state leakage and abrupt switching behavior. Reliable operation with high endurance is a key requirement for digital logic applications, and historically has been a challenge for mechanical computing devices. This paper discusses various failure modes for MEM switches, with particular focus on contact stiction due to welding. Experimental results show that device endurance (number of on/off switching cycles before welding-induced failure) improves exponentially with decreasing contact temperature, and that it depends on the contact material, contact voltage (VC), on-state resistance (RON) and load capacitance. A contact reliability model calibrated to the experimental data projects that endurance will exceed 1015 cycles at 1V operating voltage. Implications for switch contact design, logic applications and dimension scaling are discussed.

Multi-functional digital logic circuits, each utilizing only two relays, are demonstrated for the first time. This work can be extended to relay designs comprising greater than two input electrodes and/or greater than two sets of source/drain electrodes, for more compact realization of zero-leakage digital ICs in the future.

Micro-electro-mechanical (MEM) switches are of interest for ultra-low-power electronics applications [1–5] because they offer the ideal characteristics of zero off-state leakage and abrupt switching behavior. The endurance of these devices can be limited by Joule heating at the contacting asperities (Figs. 1 and 2) which eventually leads to welding-induced failure. To provide guidance for reliable MEM switch design, a predictive contact reliability model is developed and validated in this work. The results show that device endurance depends not only on the contact material, but also on the operating voltage, series resistance, load capacitance, and logic style. Using the reliability model, endurance exceeding 1015 on/off cycles is projected for a scaled MEM switch technology operating at 1V.

Power density has grown to be the dominant challenge for continued IC technology scaling. This has led to renewed interest in mechanical computing for ultra-low-power applications. This paper provides an overview of recent developments in electrostatic micro-relay design and process technology, and discusses technology scaling to achieve MEM switches that are advantageous over CMOS transistors for ultra-low-power digital logic applications.

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency [1]. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate switching device with steeper sub-threshold slope—i.e., lower V DD /I on for the same I on /I off [2]. One promising class of such devices with nearly ideal I on /I off characteristics are electro-statically actuated micro-electro-mechanical (MEM) switches [6]. Although mechanical movement makes MEM circuit delay significantly larger than that of CMOS, we have recently shown that with optimized circuit topologies MEM switches may potentially enable ∼10x lower energy over CMOS at up to ∼100MHz frequencies [3].

Characterization of adhesion force using atomic force microscopy is adapted for micro-relay applications. Measurements indicate that micro-relays with W contacting electrodes have low adhesion force (≪16.5nN/µm2). Adhesion force, as expected, scales with contact force and contact area. TiO 2 coating to improve relay reliability comes at a trade-off in surface adhesion force, which will ultimately limit energy efficiency.

A 4-terminal (4T) relay technology is proposed for complementary logic circuit applications. The advantage of the 4T relay design is that it provides a means for electrically adjusting the switching voltage; as a result, a 4T relay can mimic the operation of either an n-channel or p-channel MOSFET. Fabricated 4T relays exhibit good on-state current (I on ≫ 700µA for V DS = 1V) and zero off-state leakage current. Low-voltage switching (≪ 2V) and low switching delay (100ns) are demonstrated by appropriately biasing the body terminal. Endurance exceeds 10 9 on/off cycles without stiction or wear issues. Complementary operation is demonstrated in a functional relay inverter circuit.

Micro-electro-mechanical (MEM) relays recently have been proposed for ultra-low-power digital logic applications because their ideal switching behavior can potentially allow the supply voltage (V DD ) to be scaled down further than for CMOS devices [1–3]. This paper describes design techniques to achieve reliable (high-endurance) MEM relay operation. Prototype relays fabricated using a CMOS-compatible process are demonstrated to operate with low surface adhesion force, adequately low on-state resistance (≪ 100kΩ) over a wide temperature range (20°C–200°C), and ≫109 on/off switching cycles in N 2 ambient without stiction- or welding-induced failure. Measured characteristics are well predicted by both ANSYS simulations and an analytical model. Using the calibrated analytical model, scaled relay technology is projected to achieve ≫10× energy savings over comparably sized CMOS technology at throughputs up to ∼100MHz.

Power consumption has grown to be the dominant challenge for continued CMOS scaling. This issue can be traced directly to the fact that the thermal voltage kBT/q does not scale, limiting the extent to which the MOSFET threshold voltage and hence the supply voltage (f/dd) can be scaled. To circumvent this limit, alternative switching device designs [1,2] which can achieve

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages and large sensing margin. Because only dielectric and metal layers are required, this cell design is suitable for post-CMOS fabrication. As the cell area is reduced, low operating voltages can be maintained by scaling the vertical dimensions of the cell. Nanometer-scale electro-mechanical memory technology is therefore attractive for high-density embedded memory applications.

An accumulation-mode design for nanometer-scale electromechanical-gate field effect transistors (NEMFETs) is proposed and studied via simulation. In the off state, the gate electrode is in contact with the thin gate dielectric and short-channel effects are effectively suppressed. In the on state, the gate electrode is separated from the thin gate dielectric so that the threshold voltage VT is dynamically lowered and the transistor drive current I on is enhanced, and gate leakage is eliminated. The NEMFET can likely meet performance specifications for low-power applications at 25 nm gate length, and is attractive for scaled supply voltage operation