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Two years after Chatgpt took the world by storm, generative artificial intelligence seems to have hit a roadblock. The energy costs of building and using bigger models are spiralling, and […]

Byline: Hans Greimel Toyota Motor Corp. and Denso Corp. have partnered with some of Japan's top companies to produce cutting-edge, next-generation computer chips by the late 2020s as Japan Inc. [...]

High-voltage components can make collisions involving electric vehicles particularly dangerous, not just for the victims, but also for first responders. Some suppliers and automakers are looking to make EVs less [...]

Samsung Electronics Co. has successfully completed the development of its 5G mmWave chipsets comprised of Radio Frequency Integrated Circuits (RFICs) and Digital/Analog Front End (DAFE) Application-specific Integrated Circuits (ASICs) supporting [...]

Byline: -JONATHON KEATS JARGON WATCH IPU n . Short for intelligence processing unit, a new kind of computer chip optimized for AI. psdJARGON WATCH ILLUSTRATION BY LEON EDLER22 Way back [...]

ams introduced the AS39513, an NFC sensor tag and data logger IC for smart labels which enables more efficient and accurate monitoring of the condition of assets such as food, [...]

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers. This process provides the shortest distance between the stacked layers ([10.sup.8] vias/[cm.sup.2]), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

THE SEMICONDUCTOR INDUSTRY is unique in having a blue print for development that has proved accurate for 39 years. In 1965, Electronics magazine asked Gordon Moore, PhD, a founder of [...]

IN A RECENT EDITORIAL, EDN Executive Editor Bill Schweber reflected on the rapidly increasing ability of today's SOC (system-on-chip) IC processes to capture an entire design on a single die [...]

PROGRAMMABLE-LOGIC devices are the fastest growing segment of the logic-device family, for two fundamental reasons. Their ever-increasing gate count per device gathers up functions that you might otherwise spread over [...]

The changes that have occurred in the field of electronics including the introduction of the IC and using phase-locked loops, the synchrodyne and cassette recorders are discussed. The impact of digital technology on electronics is also described.

In this paper the next generation of a low cost, high performance single-chip picture-in-picture IC is presented. This chip will be produced in a 0.35 mu eDRAM technology and integrates a digital multistandard color decoder, embedded DRAM, A/D and D/A converters as well as a data slicer for caption services. The paper deals with the digital video signal processing for color decoding with asynchronous sampling and the compensation of the skew. A new algorithm for a jointline-free true frame display was developed. The chip allows a smooth scaling from 1/81 to of full-screen picture size and implements a data compression algorithm for split-screen modes.

High-dose buried layer (HDBL) substrates are beginning to enter mainstream integrated circuit processing, after several years of research and development. A buried layer is a heavily doped region of the […]

Adjustment-free clock and data recovery for 2.488-Gbit/s SONET applications is provided by a 1.77W, 3.45 x 3.45-[mm.sup.2] chip implemented in a 25-GHz [f.sup.T] silicon bipolar process. The chip has an […]

The lid of an ASIC package can significantly increase the temperature of the die by impeding heat transfer. In flip-chip package the backside of a die can be exposed by […]

The Latest ICs For Mobile And Cordless Telephones And ISDNs Are Showcased, With SLICs Controllers Also Featured. At Electronica '96 (Nov. 12-15, 1996), a host of new announcements were made […]

A Fast 95-V Complementary Bipolar Process Puts Three 40-MHz Amplifiers On One IC To Drive SVGA Or XGA CRT Monitors With Standard RGB Video. If you explore the guts of […]

ENHANCED DSP CHIP ARCHITECTURES MAKE MULTIMEDIA AND HDTV SUBSYSTEMS PRACTICAL BY PACKING LOTS OF PUNCH IN ONE CHIP. Digital - signal - processing (DSP) technology has invaded nearly every aspect […]

A HIGH-PERFORMANCE, TESTABLE SUBSTRATE TECHNOLOGY MAKES MULTICHIP MODULES A VIABLE COMMERCIAL PACKAGING OPTION. Although many system designers see multichip modules (MCMs) as the ticket to pushing today's ultra-fast ICs to […]

The demands for portability and higher performance are forcing IC designers to develop smaller, lower-power-consuming, and higher-bandwidth devices of all types. Nowhere are these demands more evident than in the […]

Several technical sessions at this year's ISSCC reinforce the belief held by many that the 1990s will be the Decade of Communications. After the initial lukewarm reception to new advanced […]

Third-generation RISC processors are moving into the technical world spurred by rising chip densities and higher clock rates. RISC (reduced-instruction-set computer) microprocessors delivering 50 to 100 VAX Mips are here [...]

A team led by Yale University researchers has created the first rudimentary solid-state quantum processor, taking another step toward the ultimate goal of building a quantum computer. They used a [...]

JukeBlox® 4 SDK enables audio brands to develop high-quality, low-latency products, such as standalone or multi-room wireless speakers, AV receivers, mini and micro systems, and sound bars. In combination with [...]

Establishing Standardized Military Drawings Requires Cooperation Engineers and IC manufacturers must team together to address the lack of procurable standard military drawings. SMDs for new integrated circuits will ultimately control [...]

HIGHER INTEGRATION AND MERGED ANALOG AND DIGITAL BLOCKS LET DSPS Do THE HARD JOBS. Ever the past decade, digital signal-processing chips have evolved from hard-to-use building-block circuits to relatively simple-to-program, […]

FOR EMBEDDED CONTROL, MICROCONTROLLERS SOLVE MOST NEEDS. Single-chip microcontrollers are evolving with more features and higher throughputs, and are packed with CPU, RAM, and nonvolatile memory (ROM, EPROM, or EEPROM), […]

today's proliferation in power distribution architectures is driving new solutions in power management and power conversion. Semiconductor companies have responded to this evolving opportunity by developing an ever-widening array of […]

Researchers from Sandia National Laboratories have demonstrated the first solid-state white light-emitting device that uses quantum dots as phosphors, a development they say could lead to a revolution in lighting [...]