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In this article, the electrical characteristics of Al0.28Ga0.72 N/AlN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) with a 20-nm-thick Al2O3 layer by using radio-frequency sputtering as the gate dielectric layer are compared to the conventional metal-semiconductor HEMT (MS-HEMT) with Pd/GaN gate structure. For the insertion of the Al2O3 layer, the energy band near the AlN/GaN heterojunction is lifted slightly up and the 2DEG at the heterojunction is reduced to shift the threshold voltage to the right side. Experimental results exhibits that though the maximum drain current decreases about 6.5%, the maximum transconductance increases of 9%, and the gate leakage current significantly reduces about five orders of magnitude for the MOS-HEMT than the MS-HEMT.

In this work, an AlGaN/GaN enhancement-mode high electron mobility transistor (HEMT) with two-step gate recess and electroless plating (EP) approaches is reported. Scanning electron microscopy and atomic force microscopy surface analysis are used to analysis the related properties of the EP-gate structure. A positive threshold voltage Vthof 0.68 V is obtained for the enhancement-mode EP-HEMT. In addition, a traditional HEMT based on thermal-evaporation gate is compared for the demonstration of the studied EP-HEMT with the improved performance, such as a higher maximum drain saturation current of 228.9 mA/mm, a higher maximum transconductance of 107.2 mS/mm, a lower gate leakage current of 1.2 × 10–7 mA/mm, and a higher ON/OFF drain current ratio of 4.57 × 105.

A new Pd|HfO2|AlGaN|GaN metal-oxide-semiconductor (MOS) enhancement-mode high electron mobility transistor (HEMT) is fabricated with low-temperature sensitization, activation, electroless-plating, and two-step gate-recess approaches. Experimentally, a high positive threshold voltage Vth of 1.96 V, a very low gate leakage IG of 6.3 × 10–8 mA/mm, a high maximum extrinsic transconductance gm, max of 75.3 mS/mm, a high maximum drain saturation current ID, max of 266.9 mA/mm, and a high ON/OFF current ratio of 7.6 × 107 are obtained at 300 K. Moreover, the related temperature-dependent characteristics, over temperature ranges from 300 to 500 K, are comprehensively studied. The very low temperature coefficients on gate current, drain saturation current, transconductance, and threshold voltage confirm the thermal-stable capability of the studied device. Therefore, based on these advantages, the studied Pd|HfO2|AlGaN|GaN MOS structure is suitable for the development of high-performance HEMTs.

Unlike the conventional GaAs- and InP-based enhancement/depletion-mode (E/D-mode) transistors, the improved gate characteristics of the AlGaAs/InGaAs E-mode high electron mobility transistors (HEMTs) by way of hybrid gate recesses to remove the n-AlAs/i-GaAs/n-AlGaAs virtual channel layers upon 2DEG channels are demonstrated. As compared to the D-mode device (sample A), the gate reverse currents are effectively reduced by 45 and 102 times for the E-mode devices with additional gate recess time of 24 s (sample B) and 30 s (sample C) to remove part of the virtual channel layers, respectively. Under gate forward bias, the hybrid gate recesses also enable the gate turn-on voltages to increase. Furthermore, the threshold voltages of –1.25, 0.09, and 0.22 V are observed in the samples A, B, and C, respectively. The maximum transconductances of 187.3, 209.2, and 243.4 mS/mm and saturation current density of 482.8, 410.6, and 347.4 mA/mm are obtained in the samples A, B, and C, respectively.

In this article, the hydrogen sensing characteristics of Al0.25Ga0.25In0.5P/In0.1Ga0.9As enhancement/depletion-mode co-integrated pseudomorphic doping-channel field-effect transistors by wet selectively etching process are demonstrated. At drain current of 0.1 mA/mm, the threshold voltages are of −0.97 (+0.6) V and −1.22 (+0.31) V in air and at hydrogen concentration of 9800 ppm, respectively, for the depletion (enhancement)-mode device. In addition, by employing the co-integrated FETs the transfer characteristics of the direct-coupled FET logic (DCFL) obviously vary under hydrogen ambience. The VOH value reduces and the VOL value increases in the DCFL with the measurement of hydrogen detection.

The characteristics of GaN-based light-emitting diodes (LEDs) with a hybrid structure incorporating a microhole array, 45 sidewalls, and an appropriate SiO2 nanoparticle (NP)/microsphere (MSs) passivation layer are studied and reported. The use of a SiO2 NP/MSs passivation layer causes a remarkable reduction in reverse-biased leakage current. The employment of this hybrid structure leads to substantial enhancements in optical properties without any degradation in electrical performance. In addition, a lower content of SiO2 NP in the mixed SiO2 NP/MSs solution leads to enhanced optical behavior due to the improved transmittance. Experimentally, as compared with a conventional LED (Device A), the studied Device E shows 50.6%, 50.9%, 48.4%, and 49.9% enhancements in light output power, luminous flux, luminous efficacy, and wall-plug efficiency, respectively. These advantages are mainly attributed to the increased scattering probability and the opportunity to find photon escape cones as well as the reduced total internal reflection and Fresnel reflection effects. Therefore, the studied hybrid structure provides a promise for high-performance GaN-based LED applications.

An interesting device design including a zirconium oxide (ZrO2) current blocking layer (CBL) and a ZrO2 surface passivation layer (SPL) is employed to manufacture a GaN/InGaN light-emitting diode (LED). Based on the inherently good performance of ZrO2, the current spreading effect and the undesired surface leakage are efficiently enhanced and suppressed, respectively. Energy-dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM) are used to study the relevant properties. It is found that by series calibration, 50 nm is the proper thickness of the ZrO2 CBL and SPL. The peak emission wavelength of the proposed LEDs is around 452 nm. Experimentally, at the operating condition of 110 A cm−2, the proposed Device L3 with a 50 nm-thick ZrO2 CBL and a 50 nm-thick ZrO2 SPL demonstrates improvements of 66.1% in light output power (LOP) and 64.5% in wall plug efficiency (WPE) as compared to a traditional Device L1 without the specific design. Furthermore, the proposed Device L3 presents a notable enhancement in the light emission mapping image in comparison to the traditional LED. So, the proposed device design which incorporates a proper ZrO2 CBL and ZrO2 SPL, is beneficial for manufacturing GaN/InGaN LEDs.

An Al2O3 thin film is deposited on the interdigitated electrodes to fabricate a resistive hydrogen sensor. In addition, the Pd nanoparticles (NPs)/Pd film by vacuum thermal evaporation system on the Al2O3 film acts as catalytic metals for hydrogen detection. Due to the Pd NPs with an increased surface area to volume ratio as well as the spill-over effect, the catalytic activity could be improved to enhance the gas sensing performance. The experimental results showed that the sensing response ratio is 14.4% in 1000 ppm H2/air at 300 °C, which is suitable for high-temperature hydrogen detection. The studied Pd NPs/Pd/Al2O3 resistive sensor exhibits the advantages of in high-temperature operation, simple structure, easy fabrication process, and relatively low cost.

In this article, the Pd-based mixture comprising silicon dioxide (SiO 2 ) is applied as sensing material for the InGaP/InGaAs field-effect transistor typed hydrogen sensor. After wet selectively etching the SiO 2 , the mixture is turned into Pd nanoparticles on an interlayer. Experimental results depict that hydrogen atoms trapped inside the mixture could effectively decrease the gate barrier height and increase the drain current due to the improved sensing properties when Pd nanoparticles were formed by wet etching method. The sensitivity of the gate forward current from air (the reference) to 9800 ppm hydrogen/air environment approaches the high value of 1674. Thus, the studied device shows a good potential for hydrogen sensor and integrated circuit applications.

In this article, Al0.28Ga0.72N/AlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) with Ni/Au gate metal electrode are demonstrated. NiO or Al2O3 gate oxide layer is employed as a gate dielectric layer effectively decreases the gate leakage current, enhances drain current density, and transconductance, simultaneously. As compared with the metal-semiconductor (MS) Schottky-gate device, excellent characteristics are achieved for the MOS-HEMT with NiO (Al2O3) gate oxide layer, which include maximum drain-to-source saturation current density of 626.5 (692.0) mA/mm, maximum transconductance of 87.6 (94.2) mS/mm, gate-to-drain leakage current of 1.47  10-7 (8.21  10-11) mA/mm, threshold voltage of -3.48 (-3.45) V, gate voltage swing of 2.88 (3.08) V, respectively. Experimentally, the MOS-HEMT with an Al2O3 gate oxide layer shows good potential for signal amplification and circuit applications.

The GaN-based light-emitting diodes (LEDs) with various height ratios of aluminum-doped zinc oxide (AZO) stair-like transparent layers are fabricated and comparatively investigated. The characteristics of the LEDs with conventional plane AZO transparent layer (device A) and AZO stair-like transparent layers having height ratios of 1:1:1 (device B), 1.5:1:0.5 (device C), and 0.5:1:1.5 (device D) are compared. Attributed that the lower resistance is formed in the thinner AZO film of the stair-like structure, the current crowding effect is improved for extending the whole current-spreading area. Experimentally, the forward turn-on voltages of the LEDs are reduced from 3.68 V to 3.42 V as the plane AZO transparent layer is processed to form the stair-like transparent layers with height ratio of 1:1:1. In addition, the light luminous flux, output power, external quantum efficiency, and wall-plug efficiency of the device B are enhanced by 30.5, 12.1, 22.2, and 20.7%, respectively, as compared to the traditional device with plane AZO transparent layer.

A new and simple Al/aluminum-doped zinc oxide (AZO) composite structure is proposed to act as a transparent conductive layer (TCL) for GaN-based LEDs. The Al/AZO composite layers effectively improve the current spreading performance, compared with an AZO TCL. Experimentally, the specific contact resistance of the studied Al/AZO LED is reduced by about 27.6%, compared with an AZO LED. In addition, under an operating current of 20 mA, the forward voltage and light output power (LOP) of the studied Al/AZO LED are decreased by 0.15 V and increased by 19.5%, respectively. Uniform and enhanced intensities are also found in light emission mapping images of the studied Al/AZO LED. Consequently, based on benefits including simple structure and improved electrical and optical properties, the studied Al/AZO TCL is suitable for GaN-based LED applications.

The Characteristics of GaN-based LEDs with hybrid microhole arrays and SiO2 microspheres (MSs)/ nanoparticles (NPs) are comprehensively studied. The SiO2 MSs/NPs antireflection coating, deposited by a rapid convection deposition, acts as a passivation layer of GaN-based LEDs. Since the critical angle could be enlarged by antireflection coating, Fresnel reflection could be reduced. In addition, due to the roughened surface of SiO2 MSs/NPs antireflection coating, the scattering effect could also be increased. Thus, the light extraction efficiency could be further enhanced. As compared with a conventional LED with a planar aluminum-doped zinc oxide current spreading layer (Device A), the studied device with the proposed hybrid structure and a sputtered SiO2 passivation layer (Device E) causes a suppressed leakage current and % enhancements on light output power, external quantum efficiency, and wall-plug efficiency performance.

Based on an electrophoretic deposition (EPD)-gate approach, a Pt/AlGaN/GaN heterostructure field-effect transistor (HFET) is fabricated and investigated at higher temperatures. The Pt/AlGaN interface with nearly oxide-free is verified by an Auger Electron Spectroscopy (AES) depth profile for the studied EPD-HFET. This result substantially enhances device performance at room temperature (300 K). Experimentally, the studied EPD-HFET exhibits a high turn-on voltage, a well suppression on gate leakage, a superior maximum drain saturation current, and an excellent extrinsic transconductance. Moreover, the microwave performance of an EPD-HFET is demonstrated at room temperature. Consequentially, this EPD-gate approach gives a promise for high-performance electronic applications.

A simple platinum nanoparticle (Pt NP)/WO3 semiconducting metal oxide (SMO)-based structure is fabricated and completely studied as a hydrogen gas sensor. In this work, simple rapid thermal evaporation (RTE) was employed to fabricate Pt NPs. This approach could easily produce Pt NPs with a small grain size and uniformity on the WO3 thin film. Experimentally, at 200 °C, the studied device exhibited an excellent hydrogen sensing response of 1.41 × 106 (under a 1% H2/air gas), a very low detecting level of 1 ppm H2/air, and a relatively shorter response (recovery) time of 201 s (26) s. Moreover, first order differential (FOD) and shape-preserving piecewise cubic interpolation (SPPCI) were also employed to overcome the wireless transmission problem for the Internet of Things (IoTs). Furthermore, based on the thermodynamic analysis, the surface coverage performance was studied for this device. As the result, the studied device exhibited practically adsorption with hydrogen gas at 200 °C. The studied device is therefore promising for high-performance hydrogen sensing applications.

A high-power GaN-based light-emitting diode (LED) with an inductively coupled plasma (ICP)-transferred nanohemispherical hybrid backside reflector is studied. A self-assembled 100 ± 5 nm SiO2 nanosphere monolayer is drop-coated on the backside of a sapphire substrate as a mask to transfer nanohemispherical patterns onto the backside of the sapphire substrate by ICP. Nanohemispherical patterns could be transferred to the deposited backside reflector. Thus, reflected photons could be redirected and scattered into arbitrary directions for light extraction. As compared with a conventional LED without a backside reflector, at 350 mA, the studied device exhibits a 118.2% enhancement in light output power without the degradation of electrical properties. Note that the adhesion between an ICP-transferred sapphire substrate and the hybrid backside reflector is better than when directly inserting an SiO2 nanosphere monolayer in the device. Thus, the process yield could be enhanced for applying in the solid-state lighting.

In this article the characteristics of In0.49Ga0.51P/GaAs/GaAs0.975Bi0.025 and In0.49Ga0.51P/GaAs heterojunction bipolar transistor (HBTs) are demonstrated and compared by two-dimensional simulated analysis. As compared to the traditional InGaP/GaAs HBT, the studied InGaP/GaAs/GaAsBi HBT exhibits a higher collector current, a lower base-emitter (B–E) turn-on voltage, and a relatively lower collector-emitter offset voltage of only 7 mV. Because the more electrons stored in the base is further increased in the InGaP/GaAs/GaAsBi HBT, it introduces the collector current to increase and the B–E turn-on voltage to decrease for low input power applications. However, the current gain is slightly smaller than the traditional InGaP/GaAs HBT attributed to the increase of base current for the minority carriers stored in the GaAsBi base.

In this article, a high-performance AlGaN/AlN/GaN high electron mobility transistor (HEMT) with broad gate-to-source operation voltages is fabricated and demonstrated. The experimental results exhibit a maximum extrinsic transconductance of 94.2 mS/mm at VGS = -2.58 V and a threshold voltage of -3.68 V at drain output current of 1 mA/mm.The insertion of an AlN interfacial layer can enhance the carrier confinement ability in channel and extend the gate operation voltage to +5 V. Furthermore, the effect of gate recess on device performance is investigated by two-dimensional simulation. The simulated results show that the AlGaN/AlN/GaN HEMT with gate recess structure has higher equivalent Schottky barrier height, larger electron concentration in channel, larger drain output current and transconductance as compared with the device without gate recess structure. (© 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

An enhancement-mode PHEMT (EPHEMT), fabricated by Electroless Plating (EP) and gate-sinking approaches, is comprehensively studied under high-temperature ambiences (300–475 K). The interdiffusion at Pd/AlGaAs interface confirmed by Auger depth spectroscopy (AES) profile analysis leads to the modulation of threshold voltage. In addition, the corresponding Pd-gate morphologies are examined through atomic force microscopy (AFM) and scanning electron microscopy (SEM). By gate-sinking (525 K), an EP-based PHEMT with threshold voltage shifting of +0.33 V is converted to an E-mode operation. Based on inherent advantages of EP-gate formation, the studied EPHEMT shows excellent DC performance and well thermal stability. With a gate dimension of 1 × 100 μm 2 , the studied EPHEMT presents low gate current of 6.5 (74.5) μA/mm, maximum extrinsic transconductance of 185.2 (150.6) mS/mm, maximum drain saturation current of 219.9 (98.8) mA/mm, and threshold voltage of 0.203 (0.196) V at 300 (475) K. In addition, the thermal stabilities on gate current, extrinsic transconductance, and drain current are found for the studied EPHEMT. Furthermore, a designed direct-coupled FET logic (DCFL) inverter, combined with an EP-gate and a thermal evaporated (TE)-gate PHEMT, is achieved and characterized.

Direct current and direct-coupled FET logic (DCFL) characteristics of AlGaInP/InGaAs enhancement/depletion-mode pseudomorphic doping-channel field-effect transistors (DCFETs) are demonstrated by experimental results. After wet selectively etching process, the enhancement-mode pseudomorphic DCFET with single doping channel is formed. A large forward gate voltage up to +3 (2.6) V is observed for the depletion-mode (enhancement-mode) device for the presence of a relatively large conduction band discontinuity at Al 0.15 Ga 0.35 In 0.5 P/In 0.1 Ga 0.9 As heterojunction. In the depletion-mode device with double doping channels, the drain-to-source saturation voltage is only 0.5 V as the V GS is fixed at 0 V. A maximum extrinsic transconductance of 235 (274) mS/mm and a threshold voltage of −1.3 (+0.36) V are observed in the depletion-mode (enhancement-mode) device. Furthermore, the noise margins NM H and NM L are of 0.108 V (0.534 V), and 0.390 V (0.417 V) at a supply voltage of 1.5 V (2.0 V) in the DCFL application.

DC performance of GaAsSb/InGaAs type-II and InP/InGaAs type-I doped-channel field-effect transistors (DCFETs) is demonstrated and compared by two-dimensional simulated analysis. As compared with the traditional InP/InGaAs DCFET, the GaAsSb/InGaAs DCFET exhibits a higher drain current of 8.05 mA, a higher transconductance of 216.24 mS/mm, and a lower gate turn-on voltage of 0.25 V for the presence of a relatively large conduction band discontinuity (ΔE c ≈ 0.4 eV) at GaAsSb/InGaAs heterostructure and the formation of two-dimensional electron gas in the n +-InGaAs doping channel. However, due to the tunneling effect under large gate-to-source bias, it results in considerably large gate leakage current in the GaAsSb/InGaAs DCFET.

In this paper, a high-performance heterostructure-emitter bipolar transistor employing an AlGaInP quaternary compound tunneling layer is fabricated and demonstrated. In the studied device, a 50 A n-AlGaInP tunneling emitter layer together with a 200 A n-GaAs layer forms the heterostructure emitter to decrease the collector–emitter offset voltage. On the other hand, due to the relatively large valence band discontinuity (∼0.4 eV) at AlGaInP/GaAs heterojunction and the small hole transmission coefficient across the AlGaInP tunneling layer, most of holes injecting from base to emitter will be blocked at AlGaInP/GaAs heterojunction and then high collector current and current gain are achieved. The experimental results exhibit a large collector current of 92 mA, a large current gain of 446, and a relatively low offset voltage of only 45 mV, respectively. Furthermore, a large current-gain cutoff frequency ft up to 63.7 GHz is obtained for the device with a thin tunneling layer.

In this article, the characteristics of the GaAs homojunction camel-like gate field-effect transistors with and without the gate-to-source and gate-to-drain recesses structures are first investigated and compared. As to the device without the recesses structure, a second channel within the n+-GaAs cap layer is formed at large gate bias, which could enhance the drain output current and transconductance. Furthermore, a two-stage relationship between drain current (and transconductance) versus gate voltage is observed in the recesses structure. The simulated results exhibit a maximum drain saturation current of 447 (351 mA/mm) and a maximum transconductance of 525 (148 mS/mm) in the studied device without (with) the recesses structure. Consequentially, the demonstration and comparison of the variable structures provide a promise for design in circuit applications.

In this article, the characteristics of InP/InGaAs heterostructure-emitter bipolar transistors with 30 n-InP layer tunneling layers and a five-period InP/InGaAs superlattice are demonstrated and comparatively investigated by experimentally results and analysis. In the three devices, a 200 A n-In0.53Ga0.47As layer together with an n-InP tunneling emitter layer (or n-InP/n-InGaAs superlattice) forms heterostructure emitter to decrease collector-emitter offset voltage. The results exhibits that the largest collector current and current gain are obtained for the tunneling transistor with a 30 A n-InP tunneling emitter layer. On the other hand, some of holes injecting from base to emitter will be blocked at n-InP/n-InGaAs heterojunction due to the relatively small hole transmission coefficient in superlattice device, which will result in a considerable base recombination current in the n-InGaAs layer. Therefore, the collector current and current gain of the superlattice device are the smallest values among of the devices.

Enhanced light extraction efficiency (LEE) of high-power GaN-based light-emitting diodes (LEDs) is achieved by inserting a self-assembled SiO2 nanosphere monolayer between the substrate and backside reflectors. Due to the presence of concave surfaces and photonic crystal-like air voids, downward photons emitted from multiple quantum well toward 3-D backside reflectors, could be reflected, scattered, and redirected into arbitrary directions for light extraction. These textured 3-D backside reflectors with an SiO2 nanosphere monolayer could also extract the lateral light inside device into the normal direction and improve LEE. As compared with a conventional LED without a backside reflector and an LED with a planar hybrid backside reflector, at 350 mA, the studied device with a 3-D hybrid backside reflector exhibits 136.4% (165%) and 23.6% (27.4%) enhancements in light output power (luminous flux) without the degradation of electrical properties. Higher light intensities in light emission mapping image and far-field pattern are also obtained. These results show that a textured 3-D backside reflector could be easily formed by inserting an SiO2 nanosphere monolayer to significantly enhance the performance of high-power GaN-based LEDs.

In the InP/InGaAs metamorphic co-integrated heterostructure bipolar and field-effect transistors (BiFETs), the field-effect transistor (FET) with pseudomorphic channel layer was stacked on the top of the metamorphic heterostructure bipolar transistor (HBT) with pseudomorphic base–emitter spacer layers. In the FET, a relatively thin as well as heavily doped In0.65Ga0.35As pseudomorphic channel layer between two undoped InP layers was employed to enhance the gate forward operation voltage, drain current, and transconductance, simultaneously. On the other hand, after removing the top four layers of material structures, the studied HBT was fabricated on the metamorphic buffer layer. In the metamorphic HBT, the valence band discontinuity at InP/In0.65Ga0.35As heterojunction and emitter injection efficiency could be further extended than the conventional InP/In0.53Ga0.47As lattice-matched HBTs. Furthermore, the delta doping layer between two In0.65Ga0.35As spacer layers at emitter side could effectively eliminate the potential spike at base–emitter junction for reducing the collector–emitter offset voltage. Consequently, the co-integrated metamorphic devices show a good potential for mixed signal integrated circuits and systems applications.

DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17) mS/mm and a maximum saturation current density of 43 (−27) mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330 V at a supply voltage of 1.5 V in the complementary logic inverter application.

Based on the InAlAs/InGaAs heterostructure doping-channel field-effect transistors (DCFETs), three co-integrated devices are demonstrated. After removing some material layers, the enhancement/depletion-mode devices and inverter logic were formed. The InAlAs/InGaAs co-integrated structures consist of an enhancement-mode device with single channel and two depletion-mode devices with double and triple channels, respectively. The insertion of an undoped large energy-gap layer between the metal gate and active channels can improve the gate breakdown voltage and turn-on voltage. Besides, by the studied integrated DCFETs two transfer characteristics are implemented for direct-coupled FET logic (DCFL) circuit applications as compared to the previous reports with only single logic transfer characteristic. Consequently, the integrated AlInAs/GaInAs DCFETs provide a promise for signal amplification and multiple inverter logic applications.