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This paper proposes a novel metal–oxide (MOx) thin-film transistors (TFT)-based scan driver circuit with a DC power-supplied buffer. This circuit has two parts: a ‘carry generation block (CGB)’ and an ‘output generation block (OGB).’ The CGB generates a carry pulse by the bootstrapping effect of pull-up TFT with the aid of clock signal; clock-supplied bootstrapping. Then the OGB is controlled by the carry pulse, and the output pulse is generated by the bootstrapping effect of pull-up buffer TFT with DC power supply; DC-supplied bootstrapping. In the proposed circuit, the pull-up TFT in CGB does not need to have wide dimensions because the carry signal is separated from the large capacitive load in the pixel area. Accordingly, the capacitive load of the clock signal is significantly reduced, and the dynamic power consumption associated with clock toggling decreases remarkably compared with the conventional scan driver circuit that uses the clock-supplied bootstrapping for the wide output buffer TFT. In addition, a bootstrapping inverter in OGB makes the output pulse width the same as the clock-high duration, preventing the output pulses from overlapping, which is required for most of the organic light-emitting diode (OLED) pixel circuits with in-pixel compensation.

The small subthreshold swing (SS) of metal–oxide (MOx) thin-film transistors (TFTs) reduces the data voltage (VDAT) range of the organic light-emitting diode (OLED) display pixel circuit. This leads to a large OLED current error when a small change occurs in the gate-to-source voltage (VGS) of the driving TFT in the pixel. Therefore, we propose a new pixel circuit adopting a double-gate TFT structure for the driving TFT, which is mainly driven by the bottom gate with a thicker gate insulator to provide a wide VDAT range. The proposed pixel circuit further expands the VDAT range by employing threshold voltage (VTH) modulation effect depending on the gray level. It also allows for flexible adjustment of the VTH extraction time to reduce OLED current error at low gray levels. SPICE simulation and measured results verify that the proposed pixel circuit reduces the OLED current error rate to less than 10% even with a VTH variation of ±0.5 V or SS variation of ±5% for the current level from 0.1 nA to 30 nA.

The brightness of low-temperature polycrystalline silicon and metal-oxide (LTPO) active-matrix organic light-emitting diode (AMOLED) display under low-refresh-rate driving condition tends to increase during pixel voltage holding time of each frame even though there is no critical leakage current path from the storage capacitor. We have found that the main cause of the brightness increase is electron trapping into the gate insulator of driving thin-film transistor (DTFT) which operates in the saturation mode prone to hot carrier injection. We propose a novel driving method to suppress the brightness variation by applying a high voltage to the source and drain of the DTFT during the non-emitting time which is inserted periodically for dimming the organic light-emitting diode (OLED) display. Our experimental results show that the brightness variation can be reduced from 3.7 % to 1.4 % at the 63rd gray level by the proposed DTFT reset scheme.

We report the effects of grain boundary (GB) protrusion on the off-state current (IOFF) of p-channel polycrystalline silicon thin-film transistors by using three-dimensional technology computer-aided design (TCAD) simulation. We found that the IOFF at a high drain bias, VDS = −10 V, varies more than 10 times as the position of the GB protrusion changes, whereas it varies less than two times if the GB has no protrusion, i.e. has a flat surface. The TCAD analysis showed that the IOFF was mainly caused by band-to-band tunneling and that it increased noticeably when the GB protrusion was located at a certain distance from the highly doped drain region because the GB protrusion intensified the electric field at the drain junction. We also found that the IOFF increases further when the GB line is not perpendicular to the channel direction but has some tilt angle because the GB protrusion necessarily encompassed a critical region that maximized the electric field when it was positioned within the GB protrusion.

This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement- and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the VOUT ripple voltage because the threshold voltage (VTH) of the pull-down units is compensated regardless of the a-IGZO TFT operation characteristics (enhancement mode: positive value of VTH, depletion mode: negative value of VTH). Many groups proposed the VTH compensation method for pull-down TFTs in the gate driver circuit using a diode connection structure. However, the diode connection structure to extract the VTH value cannot be applied in the depletion-mode oxide TFTs because TFT enters the turn-on state even when the VGS value is 0 V. To solve this problem, we adopted the VTH extraction period only once in one frame time. As a result, our circuit can compensate for VTH of the pull-down unit in the enhancement mode and can be normally operated in the depletion mode. Adjunctively, two low signals (VGL1 and VGL2) and QC node were designed to prevent the leakage current path for Q and VOUT nodes. To verify the threshold voltage tolerance for various stress conditions, we demonstrated the reliability of the circuit according to the threshold voltage change of the TFTs. The simulation result shows that all the VOUT waveforms are maintained at +28 V (VGH) under the VTH shift conditions from -7 V to +11 V; further, the rising time and falling time are less than 0.62 μs and 0.96 μs, respectively. Based on a 120Hz ultra-high definition (UHD) graphics (3840×2160) display panel, the proposed circuit has uniform VOUT characteristics compared to previous VTH compensation circuit when ΔVTH changes from -3 V to +11 V. When ΔVTH changes from -4 V to -7 V, there is also no circuit malfunction, even with slight increase in the falling time and power consumption.

We propose a new gate driver circuit with an improved output pulse using depletion mode amorphous indium gallium zinc oxide thin film transistors. The previous reported gate driver circuit of our group has a weak point. It is that the peak voltage of the output pulse is decreased during the output pulse duration. A peak voltage drop of output pulse is larger by an increase the leakage current of the pull-down transistor as an increase of the threshold voltage (Vth) in the negative direction. Also, a power consumption is increase by that. In this paper, the new gate driver circuit is proposed to solve this weak point. The peak voltage drop of the output pulse of the new gate driver circuit is not occurred as an increase of the pull-down transistor Vth in the negative direction. The peak voltage of the output pulse of the previous reported circuit is 27.5 and 26.2 V at the transistor Vth of 0.5 and -2.9 V, respectively. However, the peak voltage of the output pulse of the new gate driver circuit is 27.8 and 27.6 V at the transistor Vth of 0.5 and -2.9 V, respectively.

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.

We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positive-bias temperature stress (VGS = +20 V, VDS = +0.1 V, and Temperature = 60 °C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS = -20 V, VDS = +10 V, and Temperature = 60 °C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is -9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe (-11.1 V). However, it remains as small as -0.7 V for the DG TFT. [ABSTRACT FROM AUTHOR]

A Ga-In-Zn-O thin-film transistor with double-gate structure is reported. Enhancement-mode operation that is essential to the constitution of a low-power digital circuitry is easily achieved when the upper and lower gate electrodes are tied together. The saturation mobility and the subthreshold swing are improved from 3.65 cm2/(V · s) and 0.44 V/dec to 18.9 cm2/(V · s) and 0.14 V/dec, respectively, compared with the single-gate structure. We can modulate the threshold voltage of either gate by adjusting the bias on the other gate. [ABSTRACT FROM AUTHOR]

We fabricated ultrathin flexible thin film transistors with hydrophobic encapsulation layer by debonding process. In the debonding process, to separate the transistors from the carrier glass in deionized (DI) water, a strong hydrophobic material such as CYTOP was used for encapsulation, thus increasing their resistance to moisture. PVA was used as a release layer and the debonding process was optimized to separate the carrier glass and the transistors. It was confirmed that water penetration into the device can be suppressed effectively when the CYTOP thickness is 800 nm. In addition, the electrical characteristics remained almost constant even in the presence of water for 50 min. The total thickness after debonding process was approximately 2 μm. Waterproof experiments and debonding process were performed for a simple inverter circuit as well as a discrete device, and the operation and voltage gain of the inverter did not change when water was placed on the device or after debonding process. Finally, the flexibility was measured by transferring the device to a flexible PI substrate. Consequently, it was confirmed that degradation in the electrical properties was slightly up to a bending radius of 2.5 mm. [ABSTRACT FROM AUTHOR]

We propose a new gate driver circuit, in which the Q node can be operated as a pull-up either as a hold-down controller. The number of transistors for the QB nodes is reduced because the one QB node can be replaced by the pull-up unit of the Q node. With an additional VOUT pull-down unit designed using only two transistors and one capacitance, we can control the discharge interval of the VOUT node to 100% duty ratio. Despite the simplified circuit configuration, the VOUT characteristic is almost the same as that of a conventional circuit with an AC-driven structure using one Q node, and two or more QB nodes. Our simulation results show that the VH voltage operates at +28 V from the 1071st to 1080th VOUT and the rising/falling time is less than 1 μs. To verify the reliability of this circuit, we further confirmed the VOUT according to the change in the threshold voltage (VTH). The proposed circuit can be operated even when the VTH is shifted to +20.5 V from the initial value (VTH = +1.09 V). Further, the VOUT characteristic is not degraded although the VTH was shifted by +18.5 V for the pull-up unit (TFT’s ΔVTH except for pull-up unit: +2 V), and the rising/falling time were confirmed to be less than 3.2 μs. [ABSTRACT FROM AUTHOR]