Search

In this paper, the oscillation mechanism limiting the ruggedness of insulated gate bipolar transistors (IGBTs) is investigated through both circuit and device analysis. The work presented here is based on a time-domain approach for two different IGBT cell structures (i.e., trench-gate and planar), illustrating the two-dimensional effects during one oscillation cycle. It has been found that the gate capacitance varies according to the strength of the electric field near the emitter, which in turn leads to charge-storage effects associated with low carrier velocity. For the first time, it has been discovered that a parametric oscillation takes place during the short circuit in IGBTs, whose time-varying element is the Miller capacitance, which is involved in the amplification mechanism. This hypothesis has been validated through simulations and its mitigation is possible by increasing the electric field at the emitter of the IGBT with the purpose of counteracting the Kirk effect.

In this paper, the impact of the p-n-p bipolar transistor gain on the short-circuit behavior of high-voltage trench insulated-gate bipolar transistors (IGBTs) is analyzed. The short-circuit ruggedness against high-frequency oscillations is strongly improved by increasing the hole current supplied by the collector. By doing so, the electric field at the emitter of the IGBT is increased and less influenced by the amount of the excess charge (i.e., the electric field is fixed). The charge-field interactions during the short circuit event, leading to periodic charge storage and charge removal effect and provoking miller capacitance variations, can be mitigated. The effectiveness of using IGBTs with a high bipolar gain is validated through both simulations and experiments, also a design rule to tradeoff the IGBT’s losses and short-circuit robustness is provided.

LDMOS is widely used as an ESD protection device. In high voltage BCD technology. However, due to the use of low concentration medium voltage well in HV process, the LDMOS is easily damaged by the Kirk effect under ESD stress, and the robustness is very low. A novel LDMOS is proposed in this work by using a high concentration well to surround the drain intraditional LDMOS, which, achieves a high ESD robustness with a current level of 0.76A,and the Ron is reduced from the original 25Ω to 6.25Ω. In other hand ,in order to save the area, the conventional LDMOS-SCR has been improved by the drain terminal segment, which make the improved LDMOS-SCR maintain a high robustness while the device area is smaller than that of the conventional LDMOS-SCR, thereby improving the area efficiency.

The design elements of the Bi-mode Insulated Gate Transistor BIGT show that the combination of the high hole injection levels supplied from the collector together with the presence of a localized lifetime control at the MOS cells have brought improvements on the short circuit capability, strongly minimizing the high-frequency oscillations observed in IGBTs. The BIGT concept and the traditional IGBT structures have been compared under short circuit conditions to investigate the charge-field interactions at the MOS cells, triggering the oscillation mechanism. The effect of the lifetime control and the irradiation method on the short circuit capability is investigated.

Hot-carrier-injection (HCI) effect is expected to well correlate with substrate current $(\mathrm{I}_{\mathrm{SUB}})$ . However, in high-voltage (HV) device which features extended lightly-doped drain region (Ndrift), two $\mathrm{I}_{\mathrm{S}\mathrm{U}\mathrm{B}}$ peaks are frequently observed and found to have different HCI degradation. Our data showed that the worst-case HCI after long term stress doesn't necessarily occur at largest $\mathrm{I}_{\mathrm{S}\mathrm{U}\mathrm{B}}$ which is usually found at full V G operation due to Kirk-effect. The HCI dependence on $\mathrm{I}_{\mathrm{S}\mathrm{U}\mathrm{B}}$ peak location in HV device is further investigated through TCAD simulation. Our study proved the changes in impact ionization location under 2nd $\mathrm{I}_{\mathrm{S}\mathrm{U}\mathrm{B}}$ peak by Kirk-effect, thus leads to less $\mathrm{Id}_{\mathrm{lin}}$ degradation in long term stress. Nit generation at pinch-off point is found to alter IIG (impact-ionization generation) location at HV high resistance drift region and could be explained through IIG simulation by TCAD.

In this paper, a 3.3-kV Enhanced Trench IGBT has been designed with a high emitter efficiency, for improving its short-circuit robustness. The carrier distribution profile has beenshaped in a way that it is possible to increase the electric field at the surface of the IGBT, and thereby, counteract the Kirk Effect onset. This design approach is beneficial for mitigatinghigh-frequency oscillations, typically observed in IGBTs under short-circuit conditions. The effectiveness of the proposed design rule is validated by means of mixed-mode device simulations. Then, two IGBTs have been fabricated with different emitter efficiencies and tested under short circuit, validating that the high-frequency oscillations can be mitigated, with higher emitter efficiency IGBT designs.

An optically generated kink observed in the Gummel plot of AlGaAs/GaAs single heterojunction phototransistors (sHPTs) is reported when illuminated with relatively high optical powers. The observed sudden rise in collector current and decrease in the base current, referred to as `optical kink effect', is carefully studied and analyzed. The measurements are performed for incident optical power of up to 225 μW at an incident wavelength of 635 nm. This rise in the current gain of HPTs, in three terminal configuration, is associated with the base-collector space-charge modulation similar to the kirk effect.

In this letter, hot-carrier-induced degradations of forward and reverse saturation current (I sat ) under the worst stress condition are experimentally investigated for the n-type symmetric extended drain MOS (ns-EDMOS) transistor. It shows that the degradation of the reverse I sat is much larger than that of the forward I sat . Further experiments demonstrate that the phenomenon mainly results from different influences of the substrate current (I sub ) degradation upon the I sat degradation between the forward and the reverse operational conditions. At forward operational condition, the generated acceptor-like interface states will capture the electrons and enhance the Kirk effect. Subsequently, the I sat degradation is partially neutralized by the increase of I sub . However, for the reverse operational condition, the I sub shift aggravates the degradation of the I sat . Therefore, instead of forward I sat , reverse I sat should be selected as the critical parameter to evaluate hot-carrier lifetime of the ns-EDMOS device.

Time evolution of self-heating and current filamentation are discussed in this paper for shallow-trench-isolation (STI)-type drained-enhanced n-channel metal-oxide-semiconductor (DeNMOS) devices. A deeper insight toward regenerative n-p-n action and its impact over various phases of filamentation and the final thermal runaway is presented. A modified STI-type DeNMOS device is proposed in order to achieve an improvement (similar to 2x) in the failure threshold (I(T2)) and electrostatic discharge (ESD) window (V(T2)). The performance and filament behavior of the standard device under charge-device-model-like ESD conditions is also presented, which is further compared with the proposed modified device.

We derive a generalized expression for the threshold current of the Kirk effect (base widening) in bipolar transistors that have a fully depleted collector and a nonuniform dopant distribution in the collector. This generalized expression can be helpful to the analysis of the electrical characteristics, such as the cutoff frequency as a function of bias conditions, and hence to the optimization of such devices

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF- and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

An improved bipolar transistor model considering heterojunction barrier effect (HBE) in SiGe double heterojunction bipolar transistors is developed. The effect of barrier formation due to high level injection, which is related to the rapid degradations of the dc current gain (/spl beta/) and cutoff frequency (f/sub T/), is carefully investigated and analyzed. As the collector current becomes high, the conduction band barrier is induced and increased. It causes the saturation of collector current (J/sub C/) due to the blocking of carrier transport, the sharp increase of base transit time (/spl tau//sub B/) due to the additional charge storage, the increase of base current (J/sub B/) due to the increased recombination, and the decrease of intrinsic base resistance (R/sub bi/) due to the increased charge and base pushout. Those phenomena are included into a vertical bipolar intercompany model (VBIC) compact model by employing a unified model of the HBE on J/sub C/, J/sub B/, /spl tau//sub B/, and R/sub bi/. Furthermore, portions of /spl tau//sub B/ and R/sub bi/ from the Kirk effect itself are modeled according to the high current model description and the new formulation of widened base, respectively. A full extraction of parameters has been performed and the modified VBIC model is applied. The modeling accuracy is significantly improved at the high current region for the dc and RF characteristics.

In this paper, a accuracy large-signal model based on agilentHBT model for InP dou-ble heterojunction bipolar transistors (DHBTs) is implemented as symbolically defined device (SDD) in Agilent ADS. The model accounts for most physical phenomena including the Kirk effect, soft knee effect, base collector capacitance and collector transit time. The validity and the accuracy of the large-signal model are assessed by comparing the simulation with the measurement of DC and multi-bias small S parameters for InP DHBTs.

Two-dimensional surface electric field in the drift region of RESURF LDMOS is modeled in the off-state and on-state. Numerical results are shown to support the analytical results. Based on these results, 3-D Kirk effect is modeled. The reason inducing high electric field near the drain is demonstrated and methods to lower the high electric field are proposed.

Electrostatic Discharge (ESD) failure mechanisms of 18V grounded gate NMOS (GGNMOS) for liquid crystal display driver IC (LDI) applications are investigated and effects of layout design parameters on the ESD immunity level are analyzed. Experimental results show that 18V GGNMOS exhibits snapback characteristics and the ESD immunity level is rather high when XO (N-drift overlap over n+ source/drain) is sufficiently large, while GGNMOS does not exhibit the sustaining region and is very vulnerable to ESD stress when XO is relatively small. Simulation results show that the ESD failure mechanism of 18V GGNMOS could be the low-temperature second breakdown induced by the Kirk effect. It is inferred that a certain amount of XO is indispensable to ensure snapback characteristics and high ESD immunity level. Simulation results also show that the ESD immunity level is increased as drain contact to gate space (DCGS) is increased.

First an analytical expression for the base transit time in an epitaxial n + pn − n + bipolar transistor considering the field-dependent mobility and the electron velocity saturation before the onset of the Kirk effect is obtained. The base transit time is found to increase at the high collector current density. Whereas the existing analytical models show decrease of the transit time with the increase of the collector current density. The base transit time with the Kirk effect is also studied with a simple equation for transit time obtained after modifying De Graaff–Kloosterman formula for collector current. The Kirk effect is found to influence the base transit time of a bipolar transistor with highly doped base significantly at large collector current density.

In this paper, a comprehensive study of different level hot carrier stress conditions for N-type symmetrical lateral double diffused MOS (ns-LDMOS) is carried out. It is noted that there are two peaks bulk current observed for different gate voltage due to Kirk effect happening. The experimental results show two turn-over of Idsat degradation with low Vgs (mainly caused by impact ionization current increase), and one turn-over of Idsat degradation with median Vgs, which is caused by interface states generation. For high Vgs condition, significant damage is occurred on ns-LDMOS. A series of EFA and PFA demonstrate that this damage is not caused by hot carrier injection, but the self-heating effect in body of ns-LDMOS.

DEMOS devices have poor ESD robustness due to kirk effect induced snapback. Isolated DEMOS devices, in addition to the kirk effect induced second snapback, are also vulnerable to failures induced by the parasitic NPN to isolation. In addition, we demonstrate here, that some DEMOS devices show intrinsically non-scalable breakdown current (IT1) behavior due to insufficient body resistance. We then demonstrate techniques to restore IT1 scalability in these devices. We finally demonstrate the effectiveness of using selectively SBLKed drain fingers to enable self protection in small DEMOS devices.

The collector epilayer is a crucial element in the behavior of modern bipolar transistors. Compact models for its description, like the Kull model, are therefore of crucial importance too. We give a Mextram-based improvement to these models for quasi-saturation and show that the output conductance and the cutoff frequency are less abrupt in this region. Apart from ohmic quasi-saturation, we also include quasi-saturation due to the Kirk effect, which results from velocity saturation.

An iteration scheme to calculate the base transit time (/spl tau//sub b/) for a given collector current density is developed in order to determine the optimal doping profile and Ge profile in the neutral base for minimizing the /spl tau//sub b/ of SiGe HBTs under all levels of injection before the onset of the Kirk effect. We adopt a consistent set of SiGe transport parameters, tuned to measurement data, and include important effects such as the electric-field dependency of the diffusion coefficient and plasma-induced bandgap narrowing in our study. The scheme has been verified with simulation results reported in the literature. Our study shows that under both low and high injection, for a given Ge dose, intrinsic base resistance, and base concentration near the emitter, a retrograde doping profile with a trapezoidal Ge profile gives the minimum /spl tau//sub b/.

The trade-off between the breakdown performance and the Kirk effect has been evaluated and compared among conventional bipolar transistors and resurfed lateral bipolar transistors. It was demonstrated that the traditional conflict of differing requirements on W c and N c by the breakdown performance and the Kirk effect can be eased by incorporating the resurf principle. Comparative studies have been carried out between the optimized devices with breakdown voltages from 20 to 40 V. It is shown that for an identical breakdown voltage, the high-current-level performance of the resurfed devices can be significantly improved by incorporating a gradually doped collector region. This further leads to a significant increase in the cut-off frequency without degrading the breakdown performance.

In this paper, for the first time, the influence of the Kirk effect on the on-state performance of a Lateral Insulated Gate Bipolar Transistor (LIGBT) in the Double Epitaxial Layer Dielectric Isolation (DELDI) technology is presented. Unlike Junction Isolation (JI) or dielectrically isolating (DI) technologies, due to confinement of carriers within a thin pseudo-substrate, the Kirk effect plays a vital role in the enhancement of the on-state performance of a MOS-Bipolar device such as the LIGBT in the DELDI technology. Furthermore, the influence of the Kirk effect on the lateral isolation of devices has also been evaluated under static conditions.

We have calculated the threshold current density of the Kirk effect in bipolar transistors with a nonuniform doping concentration in the collector. The threshold current is enhanced by more than 50% compared to the uniform doping case if the dopant profile is weighed toward the base and if velocity overshoot is small. Significant velocity overshoot restores the threshold value obtained with uniform doping.

The interaction between transferred-electron effect and base widening under transient conditions in III–V heterojunction bipolar transistors is considered. Modification of the collector field profile with an n + doping spike is shown to cause a time delay for the onset of Kirk effect creating conditions for the inception of charge instabilities. Numerical simulations suggest the possibility of sustainable intrinsic current oscillations in properly engineered bipolar transistor structures.

A thin high-doping layer was inserted in the uniform doped collector to extend the operational current before current gain and cut-off frequency roll-off. Two times higher collector current before onset of Kirk effect was obtained and the resulted John figure of merit was improved from 846 to 1008 V-GHz.

Linearity and power performance in both small-and large-signal region of low- and high-voltage SiGe HBTs has been investigated by on-wafer measurements and process/device simulator. The impact of Kirk effect and avalanche on power and linearity has been experimentally captured and analyzed, which indicates the limitation of each type of device for RF power amplifier applications.

There are usually two explanations for the physical reasons of the high injection effects in silicon bipolar transistors: one is the effective base widening effect proposed by Kirk, the other is the base conductivity modulation effect proposed by Webster, the emitter current crowding effect intensifies these two effects. In this paper, low temperature characteristics of these three important effects are analyzed and the dominant physical mechanism which determines the high injection effects at low temperatures is presented. The obtained calculate results are in agreement with the experiments.

An ESOA of LDMOS device is very critical for power device performance. Kirk effect is the one of the major problem which leads to poor ESOA performance. The cause of the problem mainly due to the high beta value of parasitic NPN transistor in the p-body. In this study, we proposed a new 3D high side Side–Isolated N-Channel LDMOS which we have obtained not only benchmark Ron and breakdown performance, but also better ESOA without Kirk effect. We have compared the analysis of Kirk effect between the new device and the conventional N–LDMOS structure with LATID technique for the formation of the p–body of both device structures.

The Kirk effect in GaAs BJTs has been compared with that of Si BJTs using a PISCES-IIB simulator. The simulation results have shown that, due to the high electron mobility and velocity overshoot effect of GaAs, the Kirk current density of GaAs BJTs is about two times larger than that of comparable Si BJTs. It is shown that the saturation velocity model of the Kirk effect is very accurate for Si BJTs, but not for GaAs BJTs. A modified structure GaAs BJT with n + − n − collector layer, which is generally believed to have a higher Kirk current, was also studied. We have found for that case that a retarding field is formed at the n + − n − interface and that the Kirk current does not increase at all.