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In recent years, the use of fan-out packaging solutions has boomed in semiconductor-related fields. There are primarily two versions used for mass production: wafer level and panel level. In this research, a glass substrate was used in the design of a fan-out wafer-level package (FO-WLP) and simulations were conducted to predict the reliability of the solder joints. The advantages of glass substrates are their excellent electrical properties, good mechanical rigidity, flatness, and adjustable coefficient of thermal expansion. To verify the robustness of the simulations, a FO-WLP test vehicle was designed, manufactured, and tested under JEDEC thermal cycling condition. In this study, the simulation results were used in an empirical equation to estimate the reliability of the FO-WLP under accelerated thermal-cycling conditions. After simulation validated by experiments, parametric simulations of different design factors can be performed. Using this methodology, we developed a reliable finite element analysis procedure. Thus, structural optimization of the FO-WLP was possible via simulations using various design factors to improve its reliability. The simulation results indicate that a suitable combination of upper, lower pad sizes and the thickness of buffer layer could significantly enhance the reliability life of FO-WLP, and that designers should devote greater attention to these factors to achieve better long-term reliability performance.

In this study, we developed a simple method to obtain the equivalent coefficient of thermal expansion (CTE) by comparing the results of the finite element method (FEM) with the experimental results. This equivalent CTE was used to effectively describe the final mechanical/chemical shrinkage behavior after post-molding curing (PMC). During fan-out panel-level packaging, the chemical/molding shrinkage, curing and temperature cool down processes can cause excessive warpage of the panel structure. When this warpage becomes excessively large, the subsequent processing is substantially more difficult. Thus, it is important to be able to accurately predict structural warpage before manufacturing. FEMs are commonly used to estimate panel warpage during molding, however, the shrinkage behavior of the epoxy resin during molding and the material properties after curing are difficult to fit, and a much experimentation is usually required to obtain the temperature-dependent material properties of the molding compound and parameters required for the empirical equation, e.g., PVTC (Pressure Volume Temperature Cure). Furthermore, the simulation results from these empirical equations are often inconsistent with the experimental results. However, our results showed that under various geometric conditions, the equivalent CTE remained almost constant, and thus can be used in FEM as a reliable material property to predict the warpage after a panel PMC process.

We applied an artificial intelligence (AI) algorithm, the random forest (RF) model, using finite element simulations to predict the reliability life of wafer-level packaging (WLP). Due to rapid growth and an increasingly fast cycle pace of integrated circuits, it is imperative to shorten the development time of electronic packaging. This study focuses on packaging reliability analysis and prediction. In recent years, package reliability analysis has been performed using finite element method simulations, which reduce the required number of accelerated thermal cyclic tests. Compared with conventional ball grid array-type packaging, WLP has become the mainstream packaging type due to its small form factor, batch-type manufacturing process and low cost. We applied the RF model, a machine learning algorithm, to predict the reliability life of WLP. The finite element procedure, theory and mesh size were validated by a set of experiments, and a large dataset was generated for AI training purposes through the finite element simulations. The RF method was built using Python®. A fast and robust reliability assessment AI model of WLP can be achieved once the AI training accuracy is located within the target range; the designer only needs to input the geometry of each WLP component to obtain the reliability life cycle. WLP structural optimization can thus be easily achieved. The AI model also significantly shortens the design cycle to meet current design demands.

Thermosonic wire bonding is a common fabrication process for connecting devices in electronic packaging. However, when the free air ball (FAB) is compressed onto the I/O pad of the chip during bonding procedure, chip cracking may occur if the contact pressure is too large. This study proposes an effective simulation technique that can predict the wire ball geometry after bonding in an accurate range. The contact force obtained in the simulation can be used for possible die cracking behavior evaluation. The simulation in this study used the explicit time integration scheme to deal with the time marching problem, and the second-order precision arbitrary Lagrangian-Eulerian (ALE) algorithm was used to deal with the large deformation of the wire ball during the bonding process. In addition, the equilibrium smoothing algorithm in LS-DYNA can make the contact behavior and geometry of the bonding wire almost the same as the experiment, which can also significantly reduce the distortion of the mesh geometry after remeshing.

For electronic packaging structure, there are many design parameters that will affect its reliability performance, using experimental way to obtain the reliability result will take a considerable amount of time. Therefore, how to shorten the design time becomes a critical issue for new electronic packaging structure development. This research will combine artificial intelligence (AI) and simulation technology to assess the long-term reliability of wafer level packaging (WLP). A simulation technology using finite element method (FEM) with appropriate mechanics theories has been validated by multiple experiments will replace the experiment to create reliability results for different WLP structures. After a big WLP structure-reliability database created, this study will apply artificial neural network (ANN) theory to analyze this database and obtains a regression model for structure-reliability relationship of WLP. Once the regression model is established and validated, the WLP geometry, such as pad size, die and buffer layer thickness, and solder volume, etc. can be simply entered, and then the WLP reliability results can be immediately obtained through the ANN regression model.

A semi-elliptical moving heat source approach is used to predict the in-process temperature profile inside the build part during laser-based metal additive manufacturing (AM) processes. The laser has a constant heat strength which releases its energy continuously on the semi-infinite medium. It is assumed that the medium is initially at room temperature. In the proposed analytical model, some details are considered to predict the melt pool geometry more accurately and realistically. The thermal material properties are considered to be temperature dependent since the existence of the steep temperature gradient affects the magnitude of the thermal conductivity and specific heat, and as a result, it changes the heat transfer mechanisms. Moreover, the melting/solidification phase change is considered using the modified heat capacity. The multi-layer aspect of the metal AM part is considered in the modeling of the temperature profile, since the thermal interaction of the successive layers has an influence on heat transfer mechanisms. The prediction of the temperature profile of an AM part is the building block for the prediction of the thermal stress, residual stress, part distortion, and microstructure evolution. Adding more details of the AM processes to the analytical models will help to increase the accuracy of the results. In this paper, the effect of time spacing (time delay between two irradiations) and hatch spacing on thermal material properties and melt pool geometry are studied. The effect of the number of scans on melt pool geometry is also investigated. The proposed model can be used to predict the temperature profile and melt pool geometry in laser-based metal additive manufacturing configurations of either direct metal deposition (DMD) or selective laser melting (SLM). In order to validate that the proposed model can capture the physical aspects of both powder bed systems, such as SLM, and powder feed systems, such as DMD, two sets of parts are chosen which are built using SLM and DMD processes and the predicted melt pool size is compared to experimental values.

Several design parameters affect the reliability of wafer-level type advanced packaging, such as upper and lower pad sizes, solder volume, buffer layer thickness, and chip thickness, etc. Conventionally, the accelerated thermal cycling test (ATCT) is used to evaluate the reliability life of electronic packaging; however, optimizing the design parameters through ATCT is time-consuming and expensive, reducing the number of experiments becomes a critical issue. In recent years, many researchers have adopted the finite-element-based design-on-simulation (DoS) technology for the reliability assessment of electronic packaging. DoS technology can effectively shorten the design cycle, reduce costs, and effectively optimize the packaging structure. However, the simulation analysis results are highly dependent on the individual researcher and are usually inconsistent between them. Artificial intelligence (AI) can help researchers avoid the shortcomings of the human factor. This study demonstrates AI-assisted DoS technology by combining artificial intelligence and simulation technologies to predict wafer level package (WLP) reliability. In order to ensure reliability prediction accuracy, the simulation procedure was validated by several experiments prior to creating a large AI training database. This research studies several machine learning models, including artificial neural network (ANN), recurrent neural network (RNN), support vector regression (SVR), kernel ridge regression (KRR), K-nearest neighbor (KNN), and random forest (RF). These models are evaluated in this study based on prediction accuracy and CPU time consumption.

The use of artificial intelligence (AI) to optimize product performance and increase product productivity has been adopted in many fields. Kernel Ridge Regression (KRR) is an AI algorithm that can be used to effectively predict the reliability life of wafer level packaging (WLP). Compared with the familiar artificial neural network (ANN), KRR's AI model can complete the data training of a huge data set in a short time, and has good generalization ability. In electronic packaging structure, there are many design parameters that will affects its reliability performance and using experiment way to obtain the reliability result will take lot of time and huge cost. Therefore, greatly shortening the development time and development cost has become a key issue for newly developed electronic packaging structures. The focus of this research is to combine artificial intelligence method and simulation technology to predict the reliability life of wafer-level packaging; this new concept is so called AI-assisted design-on-simulation technology. In order to overcome the time-consuming problem of experiment work, a validated finite element simulationwas used instead of experiment work to generate reliability life cycle databases of different WLP structures for AI training, this huge database will be used as a training set for AI training. After the completion of the AI training, a simple AI prediction model was obtained. Designers only need to input the geometry of each component of the newly designed wafer level package to immediately obtain the reliability life cycle of this specific WLP. Kernel Ridge Regression is a machine learning algorithm. In this research, it is used to analyze the database of the relationship between the geometric size input of each component of WLP and the reliability life output, and a regression model is developed after training. Because of its better generalization performance and faster computing time, KRR can immediately predict the reliability life of WLP. In addition, this study successfully established the accuracy and CPU time analysis of the KRR regression model for the reliability life prediction of wafer-level packaging structures. KRR preliminary results show that the average percentage difference between artificial intelligence predictions and finite element simulation results is 1.27% and maximum percentage of difference is 5.81% for 576 training dataset whereas, the percentage of average difference is 0.53% and maximum percentage of difference is 2.53% for 1,296 train dataset. Similarly, the CPU time required for 576 and 1,296 train dataset are 0.09 seconds and 0.42 seconds to predict the reliability life of WLP structure. KRR performance will also be compared with the results of other regression models, such as Artificial Neural Network (ANN) and Support Vector Regression (SVR) algorithms.

The Fan-out Panel Level Packaging model after the molding process is established. We simplify the complex curing reaction of epoxy molding compound with equivalent thermal expansion coefficient method. We successfully use finite element method to build different geometric Fan-out Panel Level Packaging model as training dataset for machine learning. In the end, we used the modified Convolution Neural Network to estimate the amount of fan-out panel-level package warpage under different geometries. To avoid local minimum, Particle Swarm Optimization, PSO, is introduced for neural network parameter.

The accelerated thermal cycling test (ATCT) is a method of testing the electronic packaging reliability characteristic. A component must pass this test before being launched into the market. According to many studies, under thermal loading, the excessive thermal strain and stress occur between the package and substrate because of the coefficient of thermal expansion mismatch, which damages the solder bump of electrical packaging. In the ATCT, −40° C to 125° C is the regular thermal range of packages tested. Furthermore, the homologous temperature exceeds one-third of the melting point (K) of solder, and one should consider the accumulation of creep strain and estimate the creep behavior during the loading procedure; however, the creep strain is very sensitive to mesh size in finite element simulation. Obtaining a stable and reliable creep stain for different packaging structures becomes a must for solder joint reliability assessment. In this paper, we study a feasible and fixed element size, which should be chosen carefully for the same type of electronic packaging structure, for example, wafer level packaging (WLP), as it can affect simulation results and cause the prediction of the packaging life cycle to deviate. In ATCT simulation, there is a big difference in reliability estimation for different element mesh size selection, even if all material properties and structures remain the same. It is essential to find an appropriate and fixed element size for packaging reliability prediction to yield precise and reliable simulation results. This paper aims to find an appropriate element mesh size that can consistently predict the reliability life of various WLPs in an accurate range, and the reliability results of different WLPs under the thermal cycling loading have been validated by experiments. Moreover, the simulation results are summarized by using the Anand and hyperbolic sine creep models with suitable empirical reliability assessment equations, and the results show both creep models can predict the reliability life of WLPs in an accurate range with appropriate mesh control.

In the field of electronic packaging, the main trend is toward lighter, smaller and more functional. In the evolution of packaging technology, from PTH(Pin Through Hole), SMT(Surface Mount Technology), BGA (Ball Grid Array) to higher density and smaller package like Flip Chip (FC) and Wafer Level Packaging (WLP).One of the important issues in the package structure is reliability. There are many factors that affect its reliability. For example, package structure size, material properties, process technology, etc. are all influencing factors. In the process of designing products, the experimental method is usually used, such as the Thermal Cycling Test, to test whether the designed product can pass the fatigue life standard, and in this way ensures that the designed product will not fail during the service period. However, in practice, if the reliability test is executed by experiment method, the cost and time spent will be quite high, resulting in delayed product launch time and rising development costs, even further caused a significant reduction in the competitiveness of enterprises.In order to improve the above shortcomings, Finite Element Analysis (FEA) has been widely used in reliability assessment. Only a small amount of experimental data is needed to verified the simulation then we can greatly reduce the time spent and cost for evaluating product reliability. In this study, ANSYS software was used to simulate the equivalent plastic strain increment in Wafer-Level Package under Accelerated thermal cycling load. The Coffin-Manson formula based on strain and fixed mesh size were used to predict the fatigue life of the solder ball. Finally, the simulation results are compared with the simulation results to verify the simulation analysis and its credibility.Although using the Finite Element Analysis (FEA) has reduced a lot of time spent and cost compared to Design on Experiment (DOE). The simulation results obtained by different researchers are not totally same. The purpose of this study is to apply Machine Learning (ML) to assess the reliability of electronic package structure. It can not only reduce the time spent for predicting the reliability prediction of different structures, but also eliminate the variance of the results simulated by different researchers. In this study, combined with finite element analysis and machine learning, a database built by verified simulation results, and the estimation model was trained through this database, making the reliability life prediction process more efficient.In the choice of machine learning model, this study chose to use the Recurrent Neural Network (RNN) and compare it with the basic Artificial Neural Network (ANN). The effects of different training data sizes and distributions on the performance of the regression model are also discussed.

In recent years’ fan-out panel level package (FOPLP) is playing a most important role in electronics packaging industry due to lower cost, thinner profile, better electrical and thermal performance. However, thermally induced warpage is the critical issue for each and every researcher’s problem. Using larger wafer and panel size, and mismatch of coefficient of thermal expansion (CTE) among the constituent material, the thermally induced warpage is occurred which needs to be controlled effectively for fan-out package industry. In this work, finite element method (FEM) is used to build the FOPLP by considering equivalent CTE of molding material and then thermally induced warpage issue in the molding process is investigated. To reduce the experimental time and cost, FEM is the best method to simulate and analysis of warpage in FOPLP. Simulation can build a set of warpage result database of different geometric structures of panel level package (PLP). In addition to that, this work has been introduced Artificial Intelligence (AI) approach and the main purpose of this AI technique is to build a best model for warpage analysis by considering the design parameters like chip size, chip thickness, gap between the chips, thin film thick and so on. The best part of AI model is that, if numbers of different geometric parameters are used in this model then AI can predict the better warpage value without the help of FEM simulation. The implementation of machine learning concept which is an AI technique is to train the model from the different geometric model related to warpage datasets which are generated by FEM simulation. Convolution Neural Network (CNN) algorithm is applied to learn the relationship between geometry and amount of warpage occurred from the generated database. To enhance the training process, it has also considered Edge Detection technique. Eventually, this AI approach is successfully used to remove data points with so many similar warpage values and it could reduce training data as well as training time. Moreover, this paper successfully digitized warpage model obtained by the FEM and also successfully used the Artificial Neural Network (ANN) to train the database to learn and estimate the warpage for FOPLP

When a power module is under a continuous electrical load, a temperature effect is induced by the current load in the module configuration. The joint material therefore has long-term temperature and mechanical loadings under supplied power. A long-term temperature load can change the material and mechanical properties, including voiding, cracking, creeping and fracturing. Au/20Sn eutectic alloy, a highly temperature resistant material, is typically used for electric interconnections in high-power modules. The Au/20Sn is converted into AuSn and an Au5Sn intermetallic compound (IMC) by solid liquid inter-diffusion (SLID) bonding to form joints with high melting points. In this study, a test vehicle based on an actual power module was designed and fabricated to investigate and understand the material properties and mechanical behavior of Au/20Sn solder under a temperature load. The joint microstructure exhibited variation under different thermal treatment conditions such as temperature and load durations. The shear strength test was conducted to examine the mechanical strength of the joints under different thermal load conditions. The failure mode of the joint was further determined using fracture morphology after the shear test. Finally, the shear strength of Au/20Sn was identified to investigate the high temperature resistance of joints under different temperatures. The mechanical strengths of joints under different temperature loads are expressions of different mechanical characteristics and can be used to determine reliability at an intended high application temperature.

The effective lifetimes of electronic packages are affected by various thermos-mechanical deformations. Creep is considered the most salient mechanism in the failure of solder joints. Many researchers have conducted reasonable studies to portray the behavior of creep deformation using numerical models and further extended their research scope to forecast the lifetimes of packages with the results obtained from creep models. Many studies have identified particular creep and lifetime models to be nominal based on experimental data.In this study, the characteristics of familiar creep models were examined in detail, and their significance was made known. Lifetime prediction models that seem prominent among researchers were discussed in detail. Finite element analysis of a wafer level chip-scale package (WLCSP) used to figure out the engagement of different creep models and their capability of materializing creep deformation was investigated via simulation. The results from the simulation were applied to different lifetime prediction models, and their predictions were examined carefully. After considering the various factors that affected the reliability study of the solders, the Garofalo-Arrhenius creep model and modified strain energy density model seemed to be convincingly productive for studying the reliability of various electronic packages.

Many microelectromechanical systems (MEMS) devices generate large deflections and stresses under some severe loads, and this cumulative stress often causes structural fatigue when applying high cyclic loads. It affects the reliability and quality of the product and can easily damage structures in harsh environments. For example, accelerometers and gyroscopes in motion sensors always combine a movable mass component with a bending or torsion spring, which can severely deform their structure at some large accelerations or angular accelerations. After this high cycle of deformation, the spring structure will be damaged and cause device failure, we call this failure mode high cycle fatigue (HCF). This is very common for MEMS products, but it is difficult for designers to predict it at design stage. To prevent early fatigue problems and reduce product development time, we developed a simulation process and empirical prediction model to help designers predict HCF and improve fatigue strength of moving structures used in MEMS devices. In this study, a bending and a torsion beam are used as test vehicles. A combination of dynamic and electromechanical coupling simulations was developed and applied to analyze the effects of frequency under HCF testing. The test structures were fabricated using silicon-on-insulator (SOI) MEMS technique and these test structures were used to validate empirical life prediction equation developed in this research. The frequency effect of HCF was also to be included in the developed prediction model. Based on the test results, the accuracy of the empirical prediction equation is improved by including frequency effect.

Among the thermomechanical creep models developed to predict the solder response to progressive inelastic deformation, the Anand model is the most common. However, recent studies have had markedly different formulations of the nine parameters in this model used to describe the stress-strain curve that occurs at nonlinear, temperature-dependent low strain levels under field conditions. Furthermore, this model lacks proper technical specifications compared to the hyperbolic sine model. This has led to the development of multiple user-defined creep models with customized codes that are incompatible with many commercial finite-element tools. Therefore, modifying the current Anand model to improve the reliability of its electronic packages has become an essential task. In this paper, a new creep model was developed based on the assumptions that an instantaneous steady-state creep form eliminates the evolution term, resulting in a creep equation with four parameters. The proposed model had a fundamental statement similar to that of the well-known hyperbolic sine model. The workability of the new model was demonstrated through a simulated solder response that tested the strain rate effect and different thermal cyclic loading profiles. This model greatly broadens the applicability of the hyperbolic model. Furthermore, the modified Anand model has better agreement than the Anand model with the experimental results for different types of electronic packages.

In recent years, the material Au-20Sn eutectic solder, which is resistant to high temperatures, is used for electric interconnections in high-power modules, the material properties such as temperature and strain rate dependent stress-strain curve are critically needed for reliability assessment of Au-20Sn solder joint. Thus, this study was performed to determine the material properties of Au-20Sn eutectic solder under various strain rates and temperature loads. Many researches using shear test to determine the shear resistance of solder joint, however, the mechanical strength as measured by the shear test is the maximum shear strength of the package joint, but this measurement does not represent the stress-strain behavior of Au-20Sn material. To identify the material properties of Au-20Sn eutectic solder, the tensile test was performed to measure its mechanical strength and nonlinear material properties. The strain rate effect was examined in terms of the influence of the mechanical strength on the Au-20Sn eutectic solder at different tensile rates. The temperature-dependent material properties of Au-20Sn solder were also measured under various thermal loadings, and material properties of Au-20Sn obtained in this research can be applied to the simulation model, the thermomechanical behavior and reliability of the power module can be further analyzed and evaluated.

Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

In regard to the design of new electronic packaging structure, e.g., wafer level packaging (WLP), one needs to consider many design factors that could affect the reliability characteristics of electronic package. Before mass production, the electrical packaging has to pass the reliability test. Thermal cycling test (TCT) is one of the standard reliability tests and has been commonly used in electrical packaging industry. To ensure the new products pass the thermal cyclic test is the critical issue in the electronic packaging industry. To react to the rapid growth of electronic components, it is imperative to shorten the development time and cycles of electronic packaging, design-on-experiment (DoE) method is quite time consuming and very costly, finite element method (FEM) based design-on-simulation technology could be used as a feasible development methodology for the reliability assessment and reliability prediction of electronic package. After the FEM model, mechanics theory, simulation procedures and reliability behavior, etc. being verified by experiments, simulation can be treated the same as the experiment if simulation can consistently get the results that similar to experiment. Simulation can build a set of reliability results database of different geometric structures of the WLP and provided this database for machine learning. Machine learning is an automatic analysis method which could learn a regression model from the database for predicting reliability cycles of package instantly. In this paper, the thermal cycling test (TCT) reliability of different geometry structures of Wafer Level Packaging is discussed through verified simulation technology. The database generated by FEM simulation is analyzed by artificial neural network (ANN), the training result shown ANN can predict the reliability of unknown structure of WLCSP in an accurate range.

Establishing a stress buffer layer under a solder ball is an effective method to improve the reliability of solder balls. However, large deformation of the stress buffer layer leads to a decrease in trace line reliability. In this study, we discussed the trace line reliability of FO-WLCSP structures after thermal cycling tests. We use three-dimensional finite element methods to analyze trace line reliability and the simulation process has been validated. This study designed and discussed many different wiring patterns. Simulation results show that stress and strain are mainly concentrated in the via, chip/filler interface and pad junction. In addition, the study also discussed the effect of delamination on trace line reliability. The simulation results show that the longer and deeper delamination along the interface boundary of the chip and molding compound, the worse the reliability of the trace line.

In an electronic packaging process, an improper molding process or design will result in excessive warpage of the package structure. When the warpage is too large, the subsequent process will be difficult to perform. The finite element method (FEM) is a common method for evaluating warpage during the molding process. However, in order to fully simulate the behavior of the epoxy resin during the molding process, a large number of experiments and simulations are required to obtain material parameters. Therefore, this study uses the equivalent thermal expansion coefficient method to simplify the simulation process and estimate the actual experimental warpage. And the method is used to build a panel-level package finite element model to estimate the amount of warpage.

A physics-based analytical model is proposed in order to predict the temperature profile during metal additive manufacturing (AM) processes, by considering the effects of temperature history in each layer, temperature-sensitivity of material properties and latent heat. The moving heat source analysis is used in order to predict the temperature distribution inside a semi-infinite solid material. The laser thermal energy deposited into a control volume is absorbed by the material thermodynamic latent heat and conducted through the contacting solid boundaries. The analytical model takes in to account the typical multi-layer aspect of additive manufacturing processes for the first time. The modeling of the problem involving multiple layers is of great importance because the thermal interactions of successive layers affect the temperature gradients, which govern the heat transfer and thermal stress development mechanisms. The temperature profile is calculated for isotropic and homogeneous material. The proposed model can be used to predict the temperature in laser-based metal additive manufacturing configurations of either direct metal deposition or selective laser melting. A numerical analysis is also conducted to simulate the temperature profile in metal AM. These two models are compared with experimental results. The proposed model also well captured the melt pool geometry as it is compared to experimental values. In order to emphasize the importance of solving the problem considering multiple layers, the peak temperature considering the layer addition and peak temperature not considering the layer addition are compared. The results show that considering the layer addition aspect of metal additive manufacturing can help to better predict the surface temperature and melt pool geometry. An analysis is conducted to show the importance of considering the temperature sensitivity of material properties in predicting temperature. A comparison of the computational time is also provided for analytical and numerical modeling. Based on the obtained results, it appears that the proposed analytical method provides an effective and accurate method to predict the temperature in metal AM.

Acceleration-factor (AF) equations have been developed to rapidly predict product lifetime, and the most widely used equation is Norris-Landzberg (N-L) equation. In recent years, some researchers have found that the current AF equation does not accurately predict the experimental results for thermal cyclic loading at high ramp rates; indeed, it may yield the opposite results, due to the changing effect of the solder strain rate at different ramp rates. Modifying the current AF equation to better assess product reliability has thus become an important task for researchers.In this study, a novel AF equation was developed from a wafer level chip-scale package (WLCSP) under different thermal cyclic loadings. The frequency term used in the N-L equation was replaced with a new term in the proposed AF equation to distinguish between the effects of ramp rate and dwell time under thermal cyclic loading conditions. Proposed AF equation showed a high level of correlation with the simulation and test results for various thermal cyclic loadings. In addition, the proposed AF equation was validated by confirming the consistency of its results with experimental data on a range of packages and thermal-cycling profiles reported in the literature.

Through-silicon-via (TSV)-based 3-D integrated circuit (IC) integration (herein termed 3-D TSV IC technology) generally comprises several TSV chips, each of which may be composed of a significant number of continuously aligned TSVs and microjoints with complex geometry and structure. Directly assessing their thermal–mechanical responses and hence reliability through the finite-element analysis (FEA) can be very challenging. In this paper, an elasticity/FEA-based macroscopic mechanical constitutive characterization technique incorporated with a global/local FE (GLFE) submodeling approach is proposed for effectively simulating the thermal–mechanical behaviors of 3-D TSV IC packages. The focus of the macroscopic mechanical constitutive characterization is placed on the prediction of the effective coefficients of thermal expansion (CTEs) of the TSV chips. The predicted effective CTEs are compared with those of two simplified analytical estimates based on rule-of-mixture and energy methods. In addition, the dependence of the effective CTEs on some essential geometry parameters is also examined, by which approximate mathematical formulas in the form of global response surface (RS) are constructed using an RS methodology. The proposed methodology is tested on a high-density, fine-pitch 3-D TSV IC package, where its effectiveness is demonstrated through a comparison with those of two baseline FEA models. Results show that the proposed methodology could efficiently and accurately predict the thermal–mechanical behaviors of the 3-D TSV IC package. In addition, the predicted effective CTEs of the TSV chips show a strong dependence on the geometry of the TSV chip structure. At the permissible range of the geometry parameters, the TSV chip structure reveals a CTE transverse isotropy, where the out-of-plane ones tend to be larger than the in-plane ones.

Graphene growth on a substrate has been widely investigated due to its broad application potential. Previous studies have found that the properties of graphene depend on its underlying substrate and their interaction. However, the dynamic behavior of the interfacial structure as a function of temperature has not been investigated, as well as the interfacial structure related to its mechanical properties. In this work, molecular dynamics has been employed to study the topographic characteristics and intrinsic mechanical properties of graphene when attached to a reconstructed silicon surface. The fitness between the interfacial structures plays an important role in stabilizing the attached graphene and forming pattern. The degree of planarity of the attached graphene determines the magnitude of the residual stress, while temperature affects atomic bonding and varies this residual stress. Findings suggest that the different pairings between graphene and surface structures significantly affects the topographic characteristics, residual stress, and interaction strength of the graphene sheet, which would further change the electronic properties of its application.

In assessing the solder joint reliability using an accelerated thermal cycling (ATC) test methodology, which is widely used in the microelectronics industry, a common type of solder joint failure is the formation of fatigue cracks at the interface between the solder joints and the components. However, ATC tests are quite time-consuming and can take more than a month to complete. Hence, its efficiency has become an important issue. The parameters of the ATC test, such as temperature ramp rate and dwell time, significantly influence fatigue failure in solder joints. Fast temperature cycles can reduce the testing time, but the effects of ramp rate cause variations in solder joints' material properties and mechanics behavior due to strain rates and stress changes. Commonly used lead-free materials with high homologous temperatures induce creep-related solder joint failures. This paper used a temperature-dependent Young's modulus and Garofalo–Arrhenius creep equation to describe the solder deformation response. An energy-density-based empirical equation was used, along with the optimized mesh size in a finite-element model calculation with different solder joint geometries and packaging types such as power modules, and wafer-level chip-scale packages to determine how to accommodate the strain rate effect given various ramp rates.

The fatigue characteristics of microelectromechanical systems (MEMS) material, such as silicon or polysilicon, have become very important. Many studies have focused on this topic, but none have defined a good methodology for extracting the applied stress and predicting fatigue life accurately. In this study, a methodology was developed for the life prediction of a polysilicon microstructure under bending tests. Based on the fatigue experiments conducted by Hocheng et al. (2008, “Various Fatigue Testing of Polycrystalline Silicon Microcantilever Beam in Bending,” Jpn. J. Appl. Phys., 47, pp. 5256–5261) and (Hung and Hocheng, 2012, “Frequency Effects and Life Prediction of Polysilicon Microcantilever Beams in Bending Fatigue,” J. Micro/Nanolithogr., MEMS MOEMS, 11, p. 021206), cantilever beams with different dimensions were remodeled with mesh control technology using finite element analysis (FEA) software to extract the stress magnitude. The mesh size, anchor boundary, loading boundary, critical stress definition, and solution type were well modified to obtain more correct stress values. Based on the new stress data extracted from the modified models, the optimized stress-number of life curve (S–N curve) was obtained, and the new life-prediction equation was found to be referable for polysilicon thin film life prediction under bending loads. After comparing the literature and confirming the new models, the frequency effect was observed only for the force control type and not for the displacement control type.

Fan-out solution is developed vigorous in advance assembly field, major solutions are two ways, one is wafer level, and other is panel level method. In this research, we plan to use glass as substrate and do wafer level fan-out structure design; the advantages of the glass substrate are smoothness, flatness, CTE adjustability, low power consumption, low dielectric constant, and ultra-high resistance of the glass substrate. We will explore different design factors with finite element model (FEM) coupled with the Coffin-Mason equation is used for life prediction in simulation models. Based on these design and investigation, we could come out design factors to enhance fan-out glass package property and we also manufacture real test vehicle to do OBTCT and verify the simulation investigation. The goal of this research is to design wafer-level package structure with the fan-out features, with the domestic manufacturers to develop the glass substrate design to complete wafer-level stack packaging technology development design and life performance. The preliminary study will be carried out for the stacking unit design finite element simulation analysis and with the appropriate test products to provide experimental data, by changing the package body geometry, material and other design parameters to understand the parameters on the reliability of the stacking unit. The preliminary study will be carried out for the stacking unit design finite element simulation analysis and investigate the critical point to cause failure, discuss package design factors and mesh size to come out stable simulation results, then comparing and checking the strain and estimate life time by thermal cycle loading. To define factors this could enhance fan-out structure with glass substrate. For this fan-put package with glass substrate, stress buffer layer and dummy ball is related to life cycle. The study of stress buffer layer related to life cycle result and ball matrix design are showed in figure 3. The final life cycle calculate by Coffin-Manson equation can varies from about 780 to 1218 while changing the SBL thickness from 5 to 20um. If add dummy ball design, we could increase 20% above performance. We found factors to enhance the reliability characteristic behavior of packaging on the thermal cycling test.