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The purpose of this study is that incident shock of special guards examines closely impact getting in job stress and coping ability. This study used judgement sampling method after establish special guards who is working at airport of capital region area in 2011 by population, and sample numbers used on interpretation finally were total 239 people. Questionnaire used in this study was consisted of the total 67 question, and executed frequency analysis, Factor analysis, reliability analysis, regression analysis by SPSSWIN 18.0. reliability of questionnaire appeared more than Cronbach`s value .779. Conclusion of this study was as following. First, incident shock of special guards affects in job stress. That is, stress about personal relations increases as invasion is often repeated. Also, stress about role increases as hyperarousal is often repeated. Second, incident shock of special guards affects in coping ability. That is, problem central coping ability decreases as hyperarousal is often repeated. On the other hand, problem central coping ability increases as evasion tendency acts continuously. Third, job stress of special guards affects in coping ability. That is, problem central coping ability increases as feeling of helplessness for job characteristic acts. On the other hand, problem central coping ability, social support pursuit ability decreases as ambiguity about role acts high.

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.

A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at

A 1.8 V 2 Gb NAND flash memory is fabricated in a 90 nm process resulting in a 141 mm/sup 2/ die and a 0.044 /spl mu/m/sup 2/ effective cell. To achieve the high level of integration, critical layers are patterned with KF photolithography and phase-shift masks with proximity correction.