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A residual fracture gap after intramedullary nailing is a known risk factor for delayed union and non-union. This study aimed to report the outcomes of a forward-striking technique to reduce fracture gaps during long cephalomedullary nailing in subtrochanteric femoral fractures (SFFs).A retrospective cohort study was conducted on patients with SFFs treated in a single institution between February 2013 and October 2018. A total of 58 patients treated via long cephalomedullary nailing with a forward-striking technique were included. The width of the fracture gap, location of the cephalic screw, tip-apex distance (TAD), and time to bone union were evaluated using intraoperative and postoperative radiographs. Complication rates, including fixation failure, non-union, implant breakage, and infection, were assessed. The mean follow-up duration was 4 (range, 2‒8) years.Of the 58 patients (mean age, 67.9 years), 38 (65.5%) were female. Thirty-two cases (55.2%) were classified as atypical femoral fractures. The mean fracture gap reduced from 5.1 mm to 1.6 mm by forward striking (P0.001). The reduced fracture gap was significantly greater in atypical SFFs (mean, 4.9 mm vs. 1.7 mm; P0.001). The lag screw was located in the center-center or center-inferior zones of the femoral head in 54 patients (93.1%). The mean TAD was 14.2 mm and was under 25 mm in 55 patients (94.8%). Bone union was achieved in all cases without reoperation at a mean of 5.4 months. One incident of lag screw breakage was noted at 5 months, but bone union was achieved at 7 months.The forward-striking technique with a long cephalomedullary nail demonstrated a 100% bone union rate in a consecutive series of 58 SFFs. This technique is effective in reducing the fracture gap as well as placing the cephalic screw into the optimal position. The forward-striking technique was particularly effective in reducing atypical SFFs with a transverse or short oblique configuration.

In this article, for the first time, we propose channel characteristic-based deep neural network (DNN) models for accurate eye-height (EH) and eye-width (EW) estimation of high bandwidth memory (HBM) silicon interposer channels. The proposed models preprocess the design parameters that are highly relevant to the characteristics of the HBM channels. By taking account of the contribution of each design parameter to the eye diagram, the proposed models can accurately estimate the EH and EW of the channels even with a limited number of datasets. For verification, the proposed DNN models were applied to the microstrip and stripline channels of an HBM silicon interposer. Only redistributed layer (RDL) was used to clearly see the effect of reflecting the channel characteristics of the proposed method. We compared the proposed DNN models with various regression methods and a conventional fully connected multilayer DNN model. As a result, the proposed DNN models reduced the EH and EW error rates by 22.7 and 43.9% compared to the other regression methods. In addition, the proposed DNN models not only reduced the error rates by 22.0–28.4% but also reduced the computing cost by 8.0–9.4%, compared to the conventional DNN model. Moreover, we compared the proposed models with various DNN models having other preprocessing structures. By showing 26.7 and 28.8% lower EH and EW error rates than the other DNN models, we validated that the proposed models properly consider the most dominant design factors in preprocessing.

In this paper, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into the logic layer of the HBM to expose an excess dynamic random-access memory (DRAM) bandwidth. With parallelized DRAM architecture and a high-speed through silicon via (TSV) structure, the proposed scheme successfully extends the DRAM bandwidth of PIM. Also, the total energy consumption is decreased by the reduced interconnection and capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility for application to the current HBM. The logic layer and DRAM layers in the HBM are configured to embed the processing units and parallelize the DRAM channels. For high-speed data transfer with low interconnect energy, the TSV and silicon interposer channels are designed and analyzed in consideration of signal integrity (SI). Based on the physical design, we obtained the interconnect length in detail. The interconnect energy and delay of the silicon interposer and on-chip interconnect were modeled through a SPICE simulation. We analyzed the accurate effects of interconnect reduction caused by PIM. For overall system performance and efficiency analysis, a cycle-level architectural simulation was conducted. We successfully evaluated and analyzed the system performance for memory-intensive applications. As a result, the proposed PIM-HBM achieves 53% and 10.4% improvement on average in computing performance and energy efficiency compared to the conventional GPU-HBM.

In this article, we first measured through glass via (TGV) noise coupling and the effectiveness of shielding structures in a glass interposer. To analyze the noise coupling between signal TGVs, an open-ended structure is adopted. Glass interposer test vehicles were fabricated to verify the noise coupling between signal TGVs. With these test vehicles, noise transfer functions between signal TGVs were measured. Based on these measurement results and the equivalent circuit model, the noise coupling between signal TGVs was analyzed. To suppress this TGV noise coupling, shielding structures for the TGV noise coupling were proposed and verified. The proposed shielding structures include the variation of signal TGV pitches and the number of grounded shield TGVs, ground pads, and guard rings, respectively. The effectiveness of the proposed shielding structures was verified up to 20 GHz in frequency-domain measurements. Using the proposed shielding structures, the noise transfer function decreased by 9.4 dB at 5 GHz. Also, the effectiveness of the proposed guard ring structure was verified by a time-domain coupling noise simulation with clock signals at frequencies of 1 GHz. The proposed guard ring successfully suppressed the clock noise coupling between signal TGVs by 60.5% and 69.2% when a signal TGV pitchis 300 and 900 $\mu {\text{m}}$ , respectively.

In this article, we modeled, analyzed, and evaluated a large-scale memristor crossbar array in a neuromorphic system for a deep neural network (DNN) considering signal integrity (SI). Since hardware-based DNN using a memristor crossbar array operates in an analog way, it has serious reliability problems caused by interconnects, driver, and nonlinear memory cells. The interconnects including an on-chip signal and power/ground (P/G) mesh were modeled as circuit parameters from a full 3-D-electromagnetic (EM) simulation. The memristor was electrically modeled including its nonlinear characteristics. These models were configured into a $512 \times 512$ memristor crossbar array with drivers and peripheral circuits for the implementation of DNN. Then, we analyzed the component-level SI and nonlinearity for the interconnects and memristors, and the system level for the total array configuration. Finally, the regression of DNN in the memristor crossbar array was evaluated for verification of the analysis. All the analyzed SI and nonlinearity effects from the interconnects, memristor, and array configuration affected the regression. As the input voltage level decreased, the effect of the SI effect on accuracy became more dominant than that of the nonlinearity of the memristor effect. In terms of SI, it was verified that there is a tradeoff relationship between IR drop and crosstalk according to the interconnects’ size. Finally, the accuracy and power consumption were verified according to the array configuration in the system level as an important issue of the memristor crossbar array. Through the overall process, it was possible to analyze how the SI and nonlinearity effects affect the computational results in the neuromorphic system.

In this article, we propose a double-sided electromagnetic bandgap (DS-EBG) structure for glass interposers (GIs) with low substrate loss to suppress power/ground noise. For the first time, we validated wideband power/ground noise suppression in the GI using the proposed DS-EBG structure based on dispersion analysis and experimental verification. We experimentally verified that the proposed DS-EBG structure achieved the power/ground noise suppression (below −40 dB) between 2.5 and 8.9 GHz in the GI. Derived stopband edges, $f_{L}$ and $f_{U}$ based on the dispersion analysis, and 3-D electromagnetic (EM) simulation showed a good correlation with measurements. The effectiveness of the proposed DS-EBG structure on the power/ground noise suppression is verified by analyzing noise propagation in the power distribution network and coupling to the GI channel. Using the 3-D EM simulation, we verified that the proposed DS-EBG structure suppressed the power/ground noise coupling and improved the eye diagram of the GI channel. Finally, we propose a design methodology to broaden the isolation bandgap or miniaturize the dimensions based on the dispersion analysis.

In this article, we first propose a deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs). The proposed method provides an optimal decap design that satisfies target impedance with a minimum area. Using deep RL algorithms based on reward feedback mechanisms, an optimal decap design guideline can be derived. For verification, the proposed method was applied to test power distribution networks (PDNs) and self-PDN impedance was compared with full search simulation results. We successfully verified by the full search simulation that the proposed method provides one of the solution sets. Conventional approaches are based on complex analytical models from power integrity (PI) domain expertise. However, the proposed method requires only specifications of the PDN structure and decap, along with a simple reward model, achieving fast and accurate data-driven results. Computing time of the proposed method was a few minutes, significantly reduced than that of the full search simulation, which took more than a month. Furthermore, the proposed deep RL method covered up to $10^{17}$ – $10^{18}$ cases, an approximately $10^{12}$ – $10^{13}$ order increase compared to the previous RL-based methods that did not utilize deep-learning techniques.

This paper proposes eye diagram estimation methods for linear feedback shift register (LFSR)-based bit streams in pseudorandom binary sequence (PRBS) test and scrambling. The PRBS test uses the LFSR as a random data source; scrambling suppresses the radiated EMI by exclusive-OR (XOR) between the data and the LFSR. Both cases include the LFSR as the last block, thus, the LFSR dominantly determines the eye diagram. This paper introduced the deterministic and statistical eye diagram for the PRBS test and scrambling, respectively. The deterministic eye diagram was verified by comparing to the measurement; the statistical eye diagram was verified by comparing to the transient simulation. We also compared the voltage bathtub curves for the scrambling. The measurement and proposed method were correlated up to the BER of 10−10.

In this paper, we first propose power distribution network (PDN) model of the perforated power and ground (P/G) planes including substrate effects and multiarray through-silicon vias (TSVs) for a silicon interposer. Since it is almost impossible to simulate a high metal density perforated PDN structure, we first suggest a modeling methodology for P/G perforated planes to reduce simulation time significantly with a high accuracy. To obtain the PDN impedance of a silicon interposer faster, we convert the perforated planes to solid planes with a dielectric mixture. The capacitance (C) and conductance (G) component of perforated P/G planes are precisely estimated based on the conformal mapping method. From the estimated C and G, the physical dimension and material properties of the dielectric mixture of solid P/G planes are determined, respectively. Because silicon interposer PDN consists of a periodic structure, we design and analyze the unit cell of a PDN thoroughly. From the unit cell analysis, the electrical characteristic of an entire PDN for a silicon interposer is successfully estimated. The PDN impedance of the proposed solid and perforated P/G planes and simulation time to obtain each PDN impedance are compared and evaluated, respectively. The proposed methodology is validated by a full 3-D electromagnetic (EM) simulation in the frequency range from 0.01 to 20 GHz. We also proposed models of multiarray P/G TSVs that can be applied to the various P/G patterns for a silicon interposer. From the inductance matrix considering current directions, the self- and mutual inductances of TSVs are accurately calculated. Because quasi-transverse electromagnetic mode is propagated through TSVs and the substrate dielectric of a silicon interposer can be regarded as a uniform dielectric, the capacitance and conductance of TSVs can be calculated from the inductance matrix. The proposed model of multiarray TSVs is also analyzed and verified by EM simulations in the frequency range from 0.01 to 20 GHz with a high accuracy.

This paper, for the first time, proposed a novel eye-diagram estimation method for pulse amplitude modulation with N -level (PAM-N) signaling. For verification, a through-silicon via (TSV) channel was fabricated. Because the input of the proposed method is an insertion loss, the loss of the fabricated TSV channel was measured up to 110 GHz. The estimated eye diagrams and measured eye diagrams were compared for the same TSV channel. The proposed method and measurements have nearly the same eye-height and eye-width values at data rates of 2, 4, and 8 Gb/s. Therefore, the proposed method successfully provides PAM-N's eye diagram with the insertion loss. Furthermore, bathtub curves were compared for the proposed method and measurements. The proposed method provides a bathtub curve up to 10–12, but in contrast, the measurements only provide a bathtub curve up to 10–5 due to a limited number of samples. Both of the bathtub curves are nearly the same up to 10–5 in amplitude. In conclusion, the eye-diagram estimation method for PAM-N signaling is successfully proposed and verified.

In this paper, we first proposed a novel hybrid loop array (HLA) for low leakage electromagnetic field (EMF) level and high efficiency in a wireless high power transfer system. The proposed HLA effectively enhances the system efficiency and shields leakage EMF in a wireless power transfer (WPT) system using kHz range resonant frequency. The key originality of the proposed HLA is the combination of two types of loop coil; shielding loop coil (SLC) and amplifying loop coil (ALC). SLCs reduce leakage EMF, and ALCs significantly enhance the magnetic field from a Tx coil. The simulation and experiment results show that the proposed solution successfully overcomes the limitations of the existing solutions. Analytical modeling and design procedure are introduced and discussed. In addition, the experimental verification of the simulation result is included. We first designed and modeled an HLA considering the coupling effect of neighboring loop coils to evaluate its efficiency and leakage EMF. With the proposed HLA, we demonstrated a 9.36% improvement in the efficiency and 3 dBm reduction in the leakage EMF near the WPT system.

In this paper, we first propose and demonstrate a novel on-interposer active power distribution network (PDN) scheme to efficiently suppress simultaneous switching noise (SSN) in a 2.5-D/3-D integrated circuit (IC). The on-interposer active PDN can change the PDN impedance by controlling on-interposer decoupling capacitors. The SSN in a 2.5-D/3-D IC is suppressed by optimal control of the on-interposer active PDN scheme. The active interposer is a silicon interposer including active circuits in its silicon substrate to enhance the electrical performance of the 2.5-D/3-D IC. A test interposer of the proposed on-interposer active PDN is fabricated with a 0.18- $\mu \text{m}$ CMOS process and assembled on a printed circuit board for measurement and analysis. The active circuits of the proposed scheme and hierarchical PDN are modeled with a distributed RLGC -lumped model for fast simulation. The modeling of the proposed scheme is experimentally verified in the frequency and time domains. We successfully demonstrate that an optimum on-interposer decoupling capacitance for the minimized SSN peak-to-peak voltage was obtained by using the proposed scheme. The proposed scheme efficiently suppressed the SSN in 2.5-D/3-D IC by preventing the SSN generation at antiresonance of the hierarchical PDN. In addition, the proposed scheme is compared with a conventional passive PDN scheme, and the maximum ratio of SSN suppression against the conventional scheme was 17.2%.

In this paper, we, for the first time, designed and analyzed differential high-speed serial links of the silicon interposer including differential through-silicon-via (TSV) channels for a high-bandwidth memory (HBM) graphic module. The meshed ground plane and various parameters were considered in designing the silicon interposer. In addition, superior designs were proposed to improve signal integrity (SI) for the differential channels in the redistribution layer, TSVs, and the meshed ground. SI of the silicon interposer was successfully analyzed, and the corresponding results were verified based on a full 3-D electromagnetic solver and circuit simulations. A number of RLGC parameters were extracted and calculated, then adopted to verify the simulation results. The simulation results for the differential characteristic impedance and insertion loss were compared with those of the equivalent circuit. A mixed-mode conversion matrix was utilized to analyze differential-mode transmission. Moreover, a model for differential TSV channels was proposed to precisely analyze the electrical characteristics. The eye-diagram simulation was conducted to evaluate SI of the proposed designs in terms of an eye-opening voltage and timing jitter. The eye-opening voltage of the proposed design was 0.594 V, which is 45.69% of a peak-to-peak voltage of the assumed peripheral component interconnect (PCI)-express 4.0 interfaces. It is expected that the analysis and design methodologies of differential high-speed serial links for a silicon interposer could be widely adopted in the semiconductor industry.

This paper, for the first time, proposes and verifies a new coaxial silicone rubber socket for high-bandwidth and high-density package test using a fabricated sample. In addition, this paper also characterizes and verifies the coaxial silicone rubber socket. Because of the proposed coaxial socket’s novel coaxial structure, the proposed socket successfully achieves the electrical performance improvement. For verification, we compare the proposed socket and the previous noncoaxial socket in time domain. The proposed socket has greater eye height and eye width in the measured eye diagram than those of the noncoaxial socket. Moreover, the slope in the eye diagram is also improved in the case of the proposed socket. Therefore, the measured eye diagram for the coaxial socket shows the improvement in electrical performances. This paper also characterizes the equivalent RLGC model for the coaxial silicone rubber socket. In order to verify the RLGC model, we compare the insertion losses and eye diagrams from measurement, 3-D electromagnetic simulation, and the proposed RLGC model, respectively. Their insertion losses are comparable up to 20 GHz. Furthermore, the obtained eye diagrams are almost identical at the data rate of 9.6 Gb/s. In conclusion, this paper successfully proposes, verifies, and characterizes a new coaxial silicone rubber socket for the first time.

This paper, for the first time, proposes a novel stochastic model-based eye-diagram estimation method for 8B/10B and transition-minimized differential signaling (TMDS)-encoded high-speed channels. A stochastic model describes a behavior of an encoder with respect to probability. The previous eye-diagram estimation methods are based on an assumption that each bit has the same probability for 1 s and 0 s. However, the assumption limits to estimate an accurate eye-diagram for encoded high-speed channels. We first propose and apply the stochastic model for two types of 8B/10B encodings: 8B/10B and TMDS. For verification, we design the 8B/10B and TMDS encoder within MATLAB. The transient simulation for the 8B/10B encoded channels requires 9700 and 6600 s, respectively. However, the proposed method only requires 23 s in both cases. Furthermore, in the bit-error rate, the transient simulation provides the bathtub curve up to ${10^{ - 2}}$ due to processing time and computing resources. In contrast, the proposed method with the stochastic model provides the bathtub curve up to ${10^{ - 8}}$ . In conclusion, this paper successfully proposes and verifies the stochastic model-based eye-diagram estimation method for 8B/10B-encoded high-speed channels.

In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s.

In this paper, we design and measure 28 GHz band pass filter (BPF) based on glass interposer for 5G applications. We design the parallel coupled resonator BPF based on the glass interposer. To control the even- and odd mode characteristic impedance, we adopt the multi-layer ground. Also, to reduce the channel loss, the wide coupled channels for 28 GHz BPF are designed. Designed 28 GHz glass BPF was verified by simulation using the 3D-EM simulator. Also, Designed 28 GHz glass BPF was fabricated to verify the electrical performance through measurement. Simulated and measured insertion loss of the designed 28 GHz glass BPF is −2.4 dB and −3.4 dB at 28 GHz, respectively.

Insatiable increase of power consumption of high performance computing, various types of workloads, and lowering supply voltage require a stable and rapidly responding power supply. Integrated voltage regulators (IVR) are considered and studied as a promising solution for the fine grain power supply. In this paper, we introduce an IVR on active interposer for high performance 2.5D/3D ICs and analyze the proposed IVR by comparison with off-chip and on-chip voltage regulators (VRs). The efficiency, transient response and power noise suppression effects of each VR are evaluated. By optimal design of 2-stage VR, the IVR scheme shows higher efficiency. As closer distance from VR to load, improved transient response and power noise suppression can be achieved. In addition, due to the integration of voltage regulator circuit on active interposer, the effective footprint of module with the proposed IVR is the smallest.

In this paper, we, for the first time, propose the modeling and verification of 3-dimensional storage class memory (SCM) using new memory with high speed circuits for core operation. For the memory analysis with the simulation, the RC model of interconnections and core operation circuit models are combined in the same simulation environment. Therefore, we modeled the memory elements using passive resistances and voltage controlled switches in circuit simulation system for compatibility. To verify the proposed model, we compared the characteristics of the memory cell with the behavior model which verified to the experimental data. The overall characteristics of memory cell model are similar with the conventional behavior model. In addition, we simulated the core operation of 3-dimensional resistive SCM with the proposed models and verify the applicability in time-domain.

In this paper, for the first time, we propose a processing-in-memory in high bandwidth memory (PIM-HBM) architecture for high bandwidth systems with low dynamic random-access memory (DRAM) access costs. The main concept of the proposed PIM-HBM architecture is to embed processing units into a logic base of high bandwidth memory (HBM) to decrease the energy consumption and latency of interconnections as the physical length between core and DRAM decreases. To verify the proposed PIM-HBM architecture, we designed on-chip and on-interposer I/O channels using a CMOS 0.18 µm process. We extracted channel parasitic using an electromagnetic (EM) solver and performed a SPICE simulation to compare the system performance of the proposed architecture with the conventional HBM. As a result, the performance of the proposed PIM-HBM architecture is successfully verified by reducing energy consumption and latency of interconnections by 77 % and 79 % compared to the conventional HBM system.

In this paper, we propose glass-interposer (GI) electromagnetic bandgap (EBG) structure with defected ground plane (DGP) for efficient and broadband suppression of power/ground noise coupling. We designed, fabricated, measured, and analyzed a GI-EBG structure with DGP for the first time. The proposed GI-EBG structure with DGP is thoroughly analyzed using the dispersion characteristics and estimated stopband edges, $f_{L}$ and $f_{U}$ . We experimentally verified that the proposed GI-EBG structure with DGP achieved power/ground noise isolation bandgap (below −30 dB) between $f_{L}$ of 5.7 GHz and $f_{U}$ of 11 GHz. Estimation of $f_{L}$ and $f_{U}$ using dispersion analysis, full 3-D electromagnetic (EM) simulation results, and measurement results achieved good correlation. Effectiveness of the proposed GI-EBG structure with DGP on suppression of the power/ground noise coupling to high-speed through glass via (TGV) channel is verified with 3-D EM simulation. As a result, the proposed EBG structure successfully and efficiently suppressed the power/ground noise coupling and improved the eye diagram of the TGV channel. Lastly, we embedded thin alumina film in the proposed EBG structure and achieved even broader power/ground noise suppression between 2.1 and 14.7 GHz.

In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f L and f U of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below –40 dB) between f L of 5.8 GHz and f U of 9.6 GHz. Derived f L and f U based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel.

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs $200\;{{\mu \text{m}}}$ away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.

This paper compared a coaxial silicone rubber socket and non-coaxial socket for high-performance package test. The silicone rubber socket is a kind of the elastomer test sockets consisting of metal powders in the elastomer material. The noncoaxial silicone rubber socket may have the limited electrical performances due to its pitch. Because the pitch is determined by the package's footprint. For this, the coaxial silicone rubber socket was proposed to provide the improved insertion loss and crosstalk noise. The coaxial silicone rubber socket has extra ground powders around the signal powders to configure the coaxial structure. This coaxial structure has advantages in characteristic impedance matching and crosstalk noise reduction. Therefore, this paper compared the insertion loss and crosstalk for the non-coaxial and coaxial silicone rubber socket.

In this paper, we, for the first time, modeled and analyzed through-silicon vias (TSVs) in the multi-conductor transmission. TSV is one of the essential technology for 2.5-D/3-D ICs, Definitely, a significant number of TSV must be integrated for the direct vertical interconnections. In this point of view, it is important to propose the accurate modeling and analysis for the multiple coupled-TSVs. Firstly, we utilized the loop inductance matrix to model the self- and mutual-inductance respectively. With the assumption of the quasi-TEM propagation, the capacitance and conductance matrix were subsequently calculated to model the self- and mutual- components. The proposed multiconductor TSVs model was compared with an electromagnetic (EM) solver. The analysis of TSVs was performed based on the insertion loss at frequencies ranging from 0.01 GHz to 20 GHz. From the proposed modeling methodology, the evaluation of an electrical performance for the multiple numbers of TSVs becomes possible. In addition, signal coupling paths were discussed based on the proposed equivalent circuit model and it was observed that the equivalent conductance path is dominant in the signal couplings.

In this paper, we, for the first time, modeled and analyzed through-silicon via (TSV) with an embedded high-density metal-insulator-metal (MIM) capacitor. For 2.5-D/3-D ICs, this technology could be a potential solution to improve electrical performance. We conduct the modeling and the proposed model were compared with an electromagnetic (EM) solver, to evaluate signal and power integrity (SI/PI). The analysis was performed based on the insertion loss and impedance in the frequency range from 0.01 GHz to 20 GHz. The dominant factors to determine the electrical characteristic were analyzed depending on the frequency range. In order to model the TSVs, the concept of loop inductance was applied. Then, the capacitance and conductance between the TSVs were calculated respectively including the MIM capacitance. From the results of modeling and EM simulations, it is predicted that the TSVs are beneficial to improve SI not PI. Because the equivalent capacitance is decreased in the low frequency range under 200 MHz and the equivalent conductance is increased in the high frequency range above 200 MHz

In this paper, we propose an interposer-level integrated voltage regulator (IIVR) scheme to suppress the power noise in next-generation high bandwidth memory (HBM) input and output (I/O) interface. The proposed IIVR is a CMOS switching voltage regulator consisting of active circuits and inductors fabricated on an active interposer and a package substrate respectively. To verify the proposed IIVR, it is analyzed by time and frequency domain simulations. The proposed IIVR can suppress internal simultaneous switching noise and isolate external broadband power noise. We have verified that the proposed IIVR successfully enables the 4 Gbps signal transfer of the next generation HBM.

In this paper, we emphasize superiority of glass interposers and address challenges with proper solutions. Electrical performance of the glass interposer channels is superior to other interposers such as silicon and organic. However, glass interposers are vulnerable to noises generated in power distribution network (PDN). We propose decoupling solutions for glass interposers to solve the PDN noise issues.

In this paper, for the first time, we propose a reinforcement learning-based optimal on-board decoupling capacitor (decap) design method. The proposed method can provide optimal decap designs for a given on-board power distribution network (PDN). An optimal decap design refers to the optimized combination of decaps at proper positions to satisfy a required target impedance. Moreover, a minimum number of decaps should be assigned for optimal decap designs. The proposed method is applied to the test on-board PDN and successfully provided 37 optimal decap designs with 4 decaps assigned each. Self impedance of PDN with the provided design satisfied the required target impedance while minimizing the number of assigned decaps.

In this paper, we design and analyze receiver channels of a glass interposer for a 5G small cell front end module (FEM). In RF systems, a 50 ohm impedance matching is important for RF channels to guarantee the target RF sensitivity of the RF system. Receiver channels of glass interposers for the 5G small cell FEM are designed, analyzed and characterized up to 40 GHz considering the impedance matching. Using the designed receiver channels, the glass interposer based the 5G small cell FEM is designed and analyzed up to 40 GHz.

3D XPoint memory is one of the new memory using phase change memory (PCM) and ovonic threshold switch (OTS) with 20 nm 3-dimensional cross array structure. This memory is non-volatile and has better performance in terms of memory process speed than NAND flash memory and memory density than DRAM. The space between interconnections are close so, the voltage coupling affects to the adjacent interconnections during read operation. In this paper, we analyzed the 3D XPoint memory with memory size variation during read operation considering signal integrity (SI). For the analysis, we assumed the overall structure of the 3D XPoint memory and modeled the memory cell that consist of PCM and OTS as behavior model and the interconnections as RC model with 3D electromagnetic (EM) simulator. We fully simulated the 3D XPoint memory including memory behavior model, RC model of interconnections and peripheral circuits such as the addressor and current sense amplifier. With variation of the memory size during read operation, there are SI issues such as voltage coupling and drop trends through the interconnections.

Bias-dependent power distribution network (PDN) impedance is analyzed with respect to MOS capacitor characteristics. The proposed analysis can be used to improve the PDN impedance of 2.5D and 3D ICs.

In This paper, we present an efficient crosstalk-included eye-diagram estimation with simulation and measurement results. Crosstalk level, total jitter, and eye height are analyzed from the obtained eye-diagram. Crosstalk effects show substantial impact on eye-diagram in HBM channel.

Silicon interposer with high bandwidth memory (HBM) has been developed to achieve a terabyte/s bandwidth graphic card module. However, silicon interposer still has critical drawbacks regarding the complexity of fabrication and manufacturing cost. Especially, expensive through-silicon-via (TSV) process has become a serious problem for cost reduction. An innovative package substrate called embedded multi-die interconnect bridge (EMIB) becomes alternative solution for memory industries to reduce manufacturing cost and complexity of fabrication process of silicon interposer. Consequently, signal and power integrity (SI/PI) design and analysis of silicon based EMIB package substrate becomes essential, because it will be dominantly affected to HBM interface. In this paper, superior SI designs of EMIB is proposed and analyzed considering manufacturing cost. In addition, the impact on hierarchical PDN impedance due to EMIB is discussed and we proposed further direction for PI improvement. Proposed designs and analysis of EMIB package substrate are expected to be widely adopted in memory industries for next generation HBM interface.

In this paper, we design and analyze the receiver channel of a glass interposer for a dual band Wi-Fi front end module (FEM). In RF systems, a RF sensitivity is the most important specification for a system performance and reliability. To guarantee a target RF sensitivity of the RF system, it is important to maintain a 50 Ohm impedance matching for RF channels. The 50 Ohm impedance matching of various transmission line structures is completely conducted for each layer of the glass interposer in a low band (2.4GHz – 2.5GHz) and high band (4.9GHz – 5.85GHz) respectively. Channel types for each layer are determined considering design rules and constraints. Moreover, we locate ground TGVs near signal TGVs as close as possible to suppress a ground-ground cavity resonance effect in the low band and high band. In order to test a suppression of the ground-ground cavity resonance, simulations that compare pitches between a ground TGV and signal TGV are conducted. Design considerations of receiver channels were analyzed and characterized by simulation results of channel insertion losses.

In this paper, eye-diagrams of High-Bandwidth Memory (HBM) interposer channel with crosstalk reduction schemes on 2.5D / 3D IC are estimated and analyzed. As data rate increases and metal-to-metal space decreases to achieve higher system bandwidth, crosstalk effects degrade the signal integrity. Therefore, estimation and reduction of the crosstalk effects are essential on HBM interposer channel. In order to estimate crosstalk effects in short time with high accuracy, PDA-based estimation method is proposed. In addition to the proposed method, wide space and guard trace with ground vias structures are suggested and compared based on the estimated eye-diagrams. With the estimated eye-diagrams, voltage fluctuation on DC levels due to the crosstalk effects can be analyzed. Worst and statistical eye-diagrams of interposer channels including crosstalk effects are estimated. Since the proposed method needs only output and crosstalk response of the channel, the proposed method can be applied to multiple wide I/O channels.

A 3-D stacked high bandwidth memory (HBM) becomes a promising solution to satisfy the memory bandwidth for the processor. Due to its unique memory architecture that consists of tremendous number of input/output (I/O), it is inevitable to employee Silicon based interposer. Therefore, power distribution network (PDN) design and analysis of HBM interposer becomes one of the important step to guarantee the performance of an entire memory interface. Since the back end of line (BEOL) process technology of a semiconductor industry is applied for HBM interposer, the control of a metal density and the management of wafer warpage are required. Therefore, we designed and analyzed meshed and grid type of PDN for HBM interposer because of the limit of a metal density. In addition, we also designed and analyzed PDN both a single- and double-sided interposer. Because, a double-sided interposer has an advantage of a warpage management compared to a single-sided interposer. For the suppression of simultaneous switching noise (SSN), PDN impedance with a decoupling capacitor scheme must be properly analyzed. In this paper, a single- and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV). PDN impedance of HBM interposer is simulated and analyzed in the frequency range from 100 MHz to 20 GHz. Based on the designed HBM interposer, we shows the great potential of HBM interposer in terms of the reduction of PDN impedance to suppress SSN with a metal-insulator-metal (MIM) decoupling capacitor.

In this paper, a bump-less high-speed through silicon via (TSV) channel is proposed for terabyte/s bandwidth 2.5D IC. The signal integrity of the proposed channel is analyzed based on the frequency and time domain simulation. To analyze the signal integrity of the proposed channel minutely, the proposed channel and the conventional channel are simulated and compared respectively. Moreover, unlike the conventional channel, the signal integrity of the proposed channel is significantly affected by the coupling pads capacitance. Therefore, the proposed channel performance is investigated with different coupling pads capacitances.