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This article explores the feasibility of high-temperature annealing for top-tier devices in a sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect design guidelines are provided. CMOS–SRAM partitioning is proposed to achieve performance gain from Seq3-D. The implications of thermally stable Seq3-D on system-level performance are evaluated. Seq3-D wafer and die cost of ownership are estimated.

We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ( $\rho _{\text {c}}$ ) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively.

Presence of a native oxide interlayer degrades seriously the contact resistivity ( $\rho _{{\text {c}}}$ ) of co-deposited TiSi (CD-TiSi) on Si:P. The oxide cannot be scavenged by the CD-TSi due to its low solid solubility of O. We tackle the problem by capping the CD-TiSi with an O gettering cap. Utilizing a Ti cap and two-step post-metal rapid thermal anneal, we reduce the $\rho _{{\text {c}}}$ of the CD-TiSi on ${2}\times {10}^{{21}}$ cm $^{-{3}}$ doped Si:P by ${\sim }{3}$ times, down to ${\sim }{2} \times {10}^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ . We also demonstrate efficiency of a La cap to scavenge the oxide.

Heavily n-doped epitaxially grown Si layers are of great importance for source/drain (S/D) application in advanced node nMOS devices. For contact resistivity reduction, the dopant activation level is very important. Various techniques are being used to evaluate dopant activation in Si:P layers. Among these two methods are Scanning Spreading Resistance Microscopy (SSRM) and Differential Hall Effect Metrology (DHEM). SSRM uses an atomic force microscope equipped with a hard conductive probe that is scanned in contact mode on the cross-sectioned sample’s surface and measures spreading resistance. Measured resistance values as a function of depth are converted into resistivity and carrier concentration depth profiles using calibration measurements and conversion relationships. DHEM provides depth profiles of mobility, resistivity and carrier concentration through a semiconductor layer by making successive sheet resistance (Rs) and Hall voltage measurements using Hall effect/Van der Pauw techniques, as the electrically active thickness of the layer is reduced through successive oxidation steps. Controlled oxidation is achieved by electrochemical anodization. Data collected can then be processed to yield the depth profiles. In this contribution we have carried out SSRM and DHEM measurements on Si:P epi layers subjected to different processing conditions including annealing and ohmic contact fabrication. Secondary Ion Mass Spectrometry (SIMS) was used to measure the total (active + inactive) dopant profiles through the films. Effects of these processes on dopant diffusion and activation were studied and the results from DHEM and SSRM were compared. In-situ phosphorus (P) doped Si epi-layers were grown over 300mm diameter boron doped monitor wafers. While one set was kept as the reference, a second set was treated by a spike-annealing process at 1000 °C. In a third set a Ti/TiN contact fabrication process was carried out and the contact was removed before analysis. In the fourth set contact process was applied to the spike annealed wafer before removal of the Ti/TiN layers. Bulk sheet resistance measurements were made using 4-point probe (4PP) for all the samples. SSRM measurements were carried out at IMEC. Cross-shaped Van der Pauw test-patterns were formed on 8mmx8mm areas on the samples and DHEM measurements were performed at ALP. Figure below shows the dopant depth profiles obtained by SIMS and the carrier concentration profiles from DHEM and SSRM techniques for samples D02 (as deposited Si:P) and D03 (spike annealed). One can make some general observations from the data in this figure. The total dopant concentration as measured by SIMS is ~ 1.4E21/cm3. There is only a small difference in the total dopant distribution profiles (SIMS) between the as deposited sample and the spike annealed sample. However, the spike annealed sample shows much higher dopant activation as measured by DHEM. Carrier concentration is ~2.5x higher in sample D03 (~5E20/cm3) compared to sample D02 (~2E20/cm3). Activation levels measured by SSRM, however, are lower for both samples, and the peak carrier concentration value increases only slightly upon spike annealing, going from ~2E20/cm3 in sample D02 to ~2.2E20/cm3 in sample D03. DHEM clearly indicates the sharp interface between the p-type substrate and the n-type epi-layer and its depth calibration agrees well with the expected thicknesses of the epi layers. The tail of the SSRM data is much more graded. Data from other samples will be presented and discussed in the final manuscript. Figure 1

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

This paper proposes a La/ultrathin TiSi x metallic bilayer contact (MBC) on moderately doped n+-Si, which can simultaneously reduce contact resistivity ( $\rho _{c}$ ) and at the same time improve the contact thermal endurance. In such an MBC, the top La defines the work function (WF), whereas the ultrathin (~1 nm) TiSi x (WF-transparent) interlayer acts as a Si-diffusion barrier and improves the thermal endurance of the whole contact. Moreover, incorporation of oxygen (O) into MBC further improves the contact performance. On n+-Si with a donor concentration of $\textsf {1} \times \textsf {10}^{\textsf {19}}$ cm−3, an O-incorporated MBC can achieve an $18.3\times $ and $2.2\times $ reduction in $\rho _{c}$ as compared with Ti/n+-Si and La/n+-Si references, respectively.

In this letter, the contact properties and thermal stability of TiN/Ti/p+ -Si0.3Ge0.7 contacts are investigated. We demonstrate that the insertion of an ultra-thin Ti interlayer is necessary to reduce the contact resistivity ( $\rho _{c}$ ) as compared with a standard TiN/p+-Si0.3Ge0.7 direct contact. However, the Ti interlayer has to be thin enough to avoid degradation of the contact morphology after 500 °C annealing. This letter reveals further that the Ti encroachment into grooved SiGe regions under the contact interface is responsible for the $\rho _{c}$ increase seen after this annealing.

In this contribution, we report a fundamental study of the factors that set the contact resistivity between metals and highly doped n-type 2D and 3D semiconductors. We investigate the case of n-type doped Si contacted with amorphous TiSi combining first principles calculations with Non-Equilibrium Green functions transport simulations. The evolution of the intrinsic contact resistivity with the doping concentration is found to saturate at similar to 2 x 10(-10) Omega.cm(2) for the case of TiSi and imposes an intrinsic limit to the ultimate contact resistance achievable for n-doped Silamorphous-TiSi (aTiSi). The limit arises from the intrinsic properties of the semiconductors and of the metals such as their electron effective masses and Fermi energies. We illustrate that, in this regime, contacting heavy electron effective mass metals with semiconductor helps reducing the interface intrinsic contact resistivity. This observation seems to hold true regardless of the 3D character of the semiconductor, as illustrated for the case of three 2D semiconducting materials, namely MoS2, ZrS2 and HfS2. (C) The Author(s) 2018. Published by ECS.

In this letter, we investigate contacts of a low work function rare-earth metal, La, and its silicides on n-Si. LaSi x / ${n}^{-}$ -Si contacts show low Schottky barrier height ( $\varphi _{b}$ ) of around 0.25–0.4 eV and promisingly low contact resistivity ( $\rho _{c}$ ) on moderately doped ${n}^{+}$ -Si. However, on highly doped ${n}^{++}$ -Si, we find $\rho _{c}$ of LaSi x near one order higher than the TiSi x control. This experiment indicates that low $\varphi _{b}$ does not guarantee low $\rho _{c}$ on highly doped substrates. We further discuss reasons behind this phenomenon.

$\mathrm{Ge}_{\mathrm{1}-\mathrm{x}}\mathrm{Sn}_{\mathrm{x}}$ and $\mathrm{Si}_{\mathrm{y}}\mathrm{Gei}_{1-\mathrm{x}-\mathrm{y}}\mathrm{Sn}_{\mathrm{x}}$ are being considered for novel device schemes as they have interesting electrical and optical material properties. We will show that the epitaxial material quality is higher if GeH 4 , instead of Ge 2 H 6 , is used as Ge-source gas. $\mathrm{Ge}_{\mathrm{1}-\mathrm{x}}\mathrm{Sn}_{\mathrm{x}}$ is an interesting source/drain (S/D) material in Ge p-type FETs because the achievable electrically active boron doping concentration is a factor 60 higher than the boron solubility limit in Ge. We present a selective, conformally boron doped $\mathrm{Ge}_{\mathrm{1}-\mathrm{x}}\mathrm{Sn}_{\mathrm{x}}$ source/drain fabrication scheme implemented on 10 nm wide fins and on Ge based Gate-All-Around devices. N-doped $\mathrm{Si}_{\mathrm{y}}\mathrm{Ge}_{1-\mathrm{x}-\mathrm{y}}\mathrm{Sn}_{\mathrm{x}}$ is being considered as S/D material for nGe channels as Si:P suffers from degraded material quality when epitaxially grown on Ge.

This paper reports ultralow contact resistivities ( $\rho _{c})$ achieved on highly doped p-SiGe with two low-temperature contact formation methods. One method combines precontact amorphization implantation with ~500 °C rapid thermal processing (RTP)-based Ti germano-silicidation; $\rho _{c}$ achieved was $\sim 2.9\times 10^{-9}~\Omega \cdot $ cm2. The other method combines codeposited TiSi—Ti:Si =1:1—with ~450 °C RTP-based Ti silicidation; $\rho _{c}$ achieved was $\sim 1.7\times 10^{-9}~\Omega \cdot $ cm2. When $\rho _{c}$ reaches minimum, the TiSi(Ge) alloy is generally amorphous with embedded small crystallites, similar to the previous observations on pure Si substrates.

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSi x ) and achieve ultralow contact resistivity ( $\rho _{c}$ ) of (1.3 – 1.5) $\times 10^{-9} ~\Omega \cdot \text {cm}^{2}$ on Si:P. This PCAI + TiSi x technique utilizes light amorphization (low-energy implantation), thin Ti and TiSi x film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSi x -induced $\rho _{c}$ reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced $\rho _{c}$ variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low $\rho _{c}$ is strongly correlated with the formation of interfacial TiSi x crystallites between amorphous TiSi alloy and Si.

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height ( $q\varphi _{b})$ MIS contact: Ti/TiO2/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO2/n-Si thermal stability study under different electron conduction mechanisms. We find that both $q\varphi _{b}$ and contact resistivity ( $\rho _{c})$ of the Ti/TiO2/n-Si MIS contacts vary dramatically after mere 300 °C–500 °C 1-min rapid thermal treatments. The variations in $q\varphi _{b}$ and $\rho _{c}$ are related to the thermally driven TiO2 decomposition. This thermal stability study of Ti/TiO2/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive low-work function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed.

The solid state reaction of an ultra-thin Ni film (6nm) with Si:P epi layers (P: 0.7 to 4.0%), grown on 300-mm Si wafers, is studied as a function of different rapid thermal process (RTP) annealing temperatures (250-550?C) before and after applying a selective etch. The films are characterized using sheet resistance (Rs), mass, glancing incidence X-ray diffraction (GIXRD), X-ray reflectivity (XRR) atomic force, scanning electron and transmission electron microscopy (AFM, SEM and TEM) analyses to follow the onset of the Ni reaction, the evolution of the different phases formed within the Ni-Si system and to investigate the NiSi film properties. Results demonstrate that, though the Ni conversion to form an intermediate Ni-rich silicide phase is complete at 300?C, showing no dependency on the P content, the complete transformation (to form low resistive NiSi) shows a temperature dependence with P content (350?C vs 400?C for 0.7% P and 2.0-4.0% P). Despite the delay in silicidation completion, the NiSi films exhibit comparable layer properties, for all P contents. All films show a uniform conversion with a similar volume expansion (2.1), good interface properties, comparable resistivity (18-20µ??cm) and exhibit a smooth morphology with limited rms roughness increase (0.37 to 0.56nm). The thermal stability studies carried out on NiSi, post RTP anneals, shows a different Rs stability (650 and 575?C for 0.7% and 2.0-4.0% P), while the morphological and phase stability is found to be similar (?500?C) for all P contents. The contact resistance measured using Circular Transmission Line Model (CTLM) structures for the synthesized NiSi films is found to be 4.8×10-8 and 1.2×10-8??cm2 for 0.7% and 4.0% P respectively, the latter meeting the requirements for 10-nm CMOS technology node as predicted by International Technology Road Map for Semiconductors (ITRS). Display Omitted The reaction of ultrathin Ni film with Si:P epi layer (P: 0.7 to 4.0% P) is studied.The silicidation reaction onset and completion show a dependency with P content.Independent of P content, comparable surface/interface properties are observed for NiSiContact resistivity using 4% P meets the ITRS requirements for 10nm technology nodes.

© 2016 IEEE. Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar- and fin-based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p-Ge contact resistivity of 1.1 × 10-8 Ω cm2 is achieved by using a multi-pulse laser annealing technique for B activation. ispartof: IEEE Electron Device Letters vol:37 issue:4 pages:482-485 status: published

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

The products of the solid state reaction involving ultra-thin Ni film (6nm) and Si1-xGex layers (Ge 25 and 55at.%), were analysed using sheet resistance (Rs), glancing angle X-ray diffraction (GIXRD), scanning electron and atomic force microscopy (SEM, AFM) techniques. The reaction was carried out via rapid thermal process (RTP) annealing using two different steps (RTP1 and RTP2) while applying a selective etch (SE) in between them. The intermediate and the end reaction products resulting after RTP1 and RTP2 were found to be dependent on the Ge content, forming Ni-rich silicide (Ni2Si) and NiSi on Si75Ge25, while Ni-rich germanide (Ni5Ge3) and NiGe were obtained by using Si45Ge55. Though the onset of intermediate Ni-rich silicide or germanide phase formation occurs at similar RTP1 temperature (275?C), the reaction completion to yield low resistive phase NiSi or NiGe phase results at different RTP2 temperatures (400?C vs 350?C). Based on the volume expansion, a resistivity value of 25µ?cm was obtained for the synthesized NiGe (12nm) and NiSi (14nm) layers. Independent of the phases obtained, the films were found to be closed and homogeneous and exhibit rms roughness of 0.5-0.8nm as evidenced by SEM and AFM analysis. Thermal stability studies carried out on NiSi and NiGe thin films, post RTP1/RTP2, show the latter phase to have limited stability and result in Rs degradation starting already at 475?C due to phase decomposition. Display Omitted The reaction of ultrathin Ni film with Si1-xGex layer (x: 25 and 55at.%) is studied.Depending of Ge%, NiSi or NiGe is obtained but with different formation temperatures.The morphology, roughness and resistivity were found to be the same for NiSi and NiGe.NiGe on Si45Ge55 has limited thermal stability compared to NiSi on Si75Ge25.

uIn this work, we discuss three novel Ti (germano-)silicidation techniques featuring respectively the pre-contact amorphization implantation (PCAI), the TiSi co-deposition, and Ti atomic layer deposition (ALD). All three techniques form TiSix(Ge-y) contacts with ultralow contact resistivity (rho(c)) of (1-3)x10(-9) Omega.cm(2) on both highly doped n-Si and p-SiGe substrates: these techniques meet rho(c) requirement of 5-14 nm CMOS technology and feature unified CMOS contact solutions. We further discuss the compatibility of these techniques to the realistic CMOS transistor fabrication.

A plasma enhanced ALD process for Ru using RuO4 and H2-plasma is reported at sample temperatures ranging from 50 °C to 100 °C. At 50 °C, low impurity content Ru thin films were grown with a saturated growth rate of 0.11 nm per cycle. A study of the influence of various process parameters on the Ru film properties is given.

In this paper we report a low temperature (100 °C) ALD process for Ru using the RuO4-precursor (ToRuS™) and H2 as the reactant. The thermal decomposition behaviour of the precursor in the range of 50 °C–250 °C was investigated and it was found that thermal decomposition of RuO4 to RuO2 starts at a sample temperature of 125 °C. The RuO4/H2 process (0.0045 mbar/4 mbar) was attempted at temperatures below this decomposition limit and it was found that ALD growth of pure Ru is possible in a narrow temperature window near 100 °C. The growth rate during steady state growth was found to be 0.1 nm per cycle. The Ru film nucleated easily on a wide range of substrates (H-terminated Si, TiN, Pt and Al2O3). Although the films are grown at a low temperature, they are considerably pure and are of good quality as evidenced by a resistivity of 18 μΩ cm for an 18 nm film and a relative atomic concentration of impurities

We report record breaking values for PMOS source drain (S/D) contact resistivity, ρ c 0.4 Ge 0.6 in combination with subsequent pulsed nanosecond laser anneal (NLA). Cross section transmission electron microscopy (XTEM) shows the pc reduction mechanism is based on Ga and Ge segregation towards the surface.

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

The synthesis of nickel silicide thin films via a vapor–solid reaction has been studied by exposing thin (10 nm) Ni films to silane (SiH4). The crystalline phases, the Ni/Si stoichiometric ratios, as well as the surface and interface properties of the resulting silicide films were investigated as a function of the growth parameters such as the SiH4 partial pressure, the reaction temperature, and the exposure time. At low temperature (300 °C), SiH4 exposure led to the self-limiting deposition of Si on Ni by catalytic decomposition of SiH4 but not to silicate formation. Between 350 and 400 °C, phase pure orthorhombic NiSi films were obtained that were formed directly without any apparent intermediate Ni-rich silicide phases. A transformation to NiSi2 occurred at 450 °C and above, and at 500 °C phase pure NiSi2 was obtained. Here, the transient formation of NiSi was observed that transformed into NiSi2 for prolonged SiH4 exposure. The results indicate that the Si solubility governs the phase formation sequen...

Nanoscale morphology of vanadium dioxide (VO2) films can be controlled to realize smooth ultrathin (

Low-loss deposited amorphous silicon ( α -Si:H) layers for nano-photonic integrated circuit have been prepared using complementary-metal-oxide-semiconductor (CMOS) compatible technology. Waveguide loss as low as 3.45 dB/cm is reported for films deposited at a low temperature (300 °C) using plasma enhanced chemical vapour deposition process. The influence of the deposition parameters such as gas dilution, plasma power and pressure on the quality of the deposited material is thoroughly characterized using Fourier transform infrared spectroscopy (FTIR), spectroscopic ellipsometry, X-ray diffraction and atomic force microscopy. We show that the optical quality of the deposited film can be directly assessed from distinct frequency bands (2090, 2000 and 840 cm −1 ) using FTIR, without the need for further waveguide loss measurements.

Crystalline vanadium dioxide (VO 2 ) thin films were prepared by annealing amorphous VO 2 films which were deposited by atomic layer deposition on a SiO 2 substrate. A large influence of the oxygen partial pressure in the annealing ambient was observed by means of in-situ X-ray diffraction. In the range between 1 and 10 Pa of oxygen the interesting VO 2 (R) phase crystallized near 450 °C. Between 2 and 10 Pa of oxygen, metastable VO 2 (B) was observed as an intermediate crystalline phase before it transformed to VO 2 (R). Anneals in inert gas did not show any crystallization, while oxygen partial pressures above 10 Pa resulted in oxidation into the higher oxide phase V 6 O 13 . Film thickness did not have much effect on the crystallization behavior, but thinner films suffered more from agglomeration during the high-temperature crystallization on the SiO 2 substrate. Nevertheless, continuous polycrystalline VO 2 (R) films were obtained with thicknesses down to 11 nm. In the case where VO 2 (R) was formed, the semiconductor–metal transition was observed by three complementary techniques. This transition near 68 °C was characterized by X-ray diffraction, showing the transformation of the crystal structure, by spectroscopic ellipsometry, mapping optical changes, and by sheet resistance measurements, showing resistance changes larger than 2 orders of magnitude between the low-temperature semiconducting state and the high-temperature metallic state.

We report on the synthesis of Cu3Ge films by exposing Cu films to germane (GeH4). The process window was established by investigating the influence of the GeH4 partial pressure, the soak temperature, and the soak time on Cu films of different thickness. It is shown that short exposures of germane led to Cu-rich germanides, while an excessive GeH4 supply resulted in a Cu3Ge/Ge mixed phase. The germanidation reaction was found to be selective and required the prior removal of the native Cu oxide by in situ plasma cleaning. X-ray diffraction and transmission electron microscopy showed that the Cu3Ge films were crystalline as deposited in the orthorhombic phase and were textured. The films were homogenous in composition. Thin films consisted of Cu3Ge islands connected by a thin wetting layer. Fully continuous layers were however found for larger film thicknesses. The continuity of the Cu3Ge film was also found to be influenced by the pseudosubstrate: the films were more continuous on TaN/Ta than on SiO2. The electric properties of the Cu3Ge films on both TaN/Ta and SiO2 pseudosubstrates are presented and compared.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

The electrical characteristics of Ti/p-SiGe contacts with Ti thicknesses of 3nm and 5nm have been investigated in this paper. TiN was used as a cap layer on Ti. It is observed that as Ti film becomes thinner, Ti/p-SiGe contact resistivity (ρc) increases, but its Schottky barrier height (SBH) decreases, which does not coincide with the regular ρc-SBH dependence. Using TiN/p-SiGe as a control sample, it is concluded that when Ti film is thinned down to nm scale, the contact property is strongly influenced by TiN cap layer.

Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ c ) of ∼2×10−9 Ω·cm2 on Si 0.3 Ge 0.7 :B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρ c on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P. A simple Ti based CMOS contact flow is thus proposed. Several B doping and activation methods on SiGe:B are also compared in this work.

Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage over MIS. On n-type substrates, on the one hand, we find MIS contacts have relatively high contact resistivity despite the low Schottky barrier height; the low thermal stability of MIS is also worrying. On the other hand, with MS contacts, we use a pre-amorphization based Ti silicidation technique and achieve contact resistivity of 1.5×10−9 Ω·cm2. Therefore, for both NMOS and PMOS, we confirm that MS contacts are still the prevailing contact scheme. Advanced MS interface engineering is able to help reach the target contact resistivity required by advanced CMOS technology.

This paper introduces the investigations on ultralow metal/semiconductor contact resistivity (ρc). First, we build a multiring circular transmission line model (MR-CTLM), a novel ρc test structure with simple process and high accuracy for rigorous ρc study. Based on that, we explore process options to achieve ultralow ρc on n-Si. We obtain high carrier concentration of ∼9e20 cm−3 by in situ P doped Si:P epitaxy followed by ms laser annealing. Besides, we use a pre-contact amorphization plus Ti silicidation technique to fabricate TiSix/Si:P contacts and achieve ultralow ρc of 1.5e–9 Ohm.cm2. Finally, we discuss sub-1e-9 Ohm.cm2 ρc solutions for future CMOS technology node.

© 2016 Author(s). Applying simulations and experiments, this paper systematically compares contact resistivities (ρc) of metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) contacts with various semiconductor doping concentrations (Nd). Compared with the MS contacts, the MIS contacts with the low Schottky barrier height are more beneficial for ρc on semiconductors with low Nd, but this benefit diminishes gradually when Nd increases. With high Nd, we find that even an "ideal" MIS contact with optimized parameters cannot outperform the MS contact. As a result, the MIS contacts mainly apply to devices that use relatively low doped semiconductors, while we need to focus on the MS contacts to meet the sub-1 × 10-8 Ω cm2 ρc requirement for future Complementary Metal-Oxide-Semiconductor (CMOS) technology. ispartof: Applied Physics Letters vol:108 issue:17 pages:1-5 status: published

NiO thin films are deposited by atomic layer deposition (ALD) from the Ni(dmamb)2 (dmamb = 1-dimethylamino-2-methyl-2-butanolate) precursor using O3 as the oxidizer. The films are analyzed for wafer uniformity, structure, composition, morphology, microstructure, and homogeneity. The Ni(dmamb)2 half-cycle shows an initial rapid partial saturation followed by slower further adsorption. By contrast, the O3 half-cycle shows good saturation behavior. In the studied deposition temperature range for ALD, the films are polycrystalline with negligible amounts of carbon in the films. Furthermore, the films are homogeneous in thickness and composition, demonstrating that high-quality NiO films can be deposited by ALD from Ni(dmamb)2.

In the framework of Resistive RAM we are investigating if the metal to insulator transition in vanadium dioxide can be used for memory applications. We investigate vanadium dioxide production by low pressure oxidation of metallic vanadium and demonstrate samples with 4 orders of magnitude transition in resistivity. We show that the relaxation times to the coexistence state are compatible with non-volatile memory requirements being longer than 10 years. We also investigate how metal doping influences the transition temperature.

Ruthenium is proposed as electrode for next generation DRAM metal-insulator-metal capacitors and interconnect barrier/seed. This study compares different ALD processes to deposit Ru and RuO2 films. ALD with oxygen results in the deposition of either Ru or RuO2, depending on deposition conditions. We also report the growth and scalability of Ru films by plasma-enhanced ALD (PEALD) with ammonia. The inorganic precursor RuO4 was studied as an alternative chemical pathway, of which the characteristics and film properties were studied at temperature range 100-250ºC using various process conditions. The quality of films deposited with thermal ALD and PEALD is compared with respect to the targeted applications. In particular, the investigation of the thermal stability of the different Ru and RuO2 films under typical DRAM anneal conditions is presented.

Silicon nanowires (SNWs) have recently attracted a lot of interest due to its explosive potential for nanoelectronic applications. To materialize these applications, the key role of thermal oxidation behavior of SNWs must be thoroughly understood. In the first half of the paper we review the results on SNW oxidation published up to date. It is commonly observed that SNW oxidation shows a retarded oxidation rate and stronger temperature dependence compared to those of planar Si; in addition, the SNW oxide thickness is also a strong function of SNW diameter. In the second half, we report our results on the SNW oxidation using an in-situ steam generation (ISSG) approach. ISSG oxidation is applied to oxidize the SNWs generated by a top-down lithography-etch approach, as an important technique to reduce the SNW diameter below 10nm. It is found that SNW oxidation with ISSG also exhibits a retared oxidation compared to that of planar Si using the same ISSG process, and a less dependance on SNW sizes than furnace SNW oxidation.

The metal resistance in the transmission line model (TLM) structures creates a serious obstacle to determine precisely the intrinsic contact resistivity. To tackle this problem, we propose a new model, the Lump Model, to evaluate the metal resistance influence in both TLM and circular TLM (CTLM) test structures. In this work, we demonstrate the high simplicity, great robustness and flexibility of the Lump Model. The previous reported contact resistivity values extracted with CTLM are usually above 1×10-7 Ω·cm2 because the metal resistance impact is commonly neglected. This is the first time that the role of the metal in CTLM is appropriately analyzed. Low contact resistivity, 3.6×10-8 Ω·cm2, of standard NiSi/n-Si contact has been extracted and this shows the high sensitivity of this method. ispartof: IEEE Electron Device Letters vol:35 issue:9 pages:957-959 status: published

A 300mm ALD HfZrOx process using TDEAH, TDEAZ, and H2O is developed. This process applies a nano-laminate approach to grow a HfZrOx film by intermixing ALD HfO2 and ZrO2 around 250{degree sign}C. It is found that the corresponding Zr content of the film, measured by RBS, increases linearly with the cycle ratio of Zr/(Zr+Hf). In addition, the initial growth behavior of the HfZrOx film of this unique process is insensitive to the starting surface condition and eliminates the long incubation as observed for the halide-based ALD processes. The as-deposited HfZrOx films are amorphous, which can be crystallized with a 950{degree sign}C postdeposition anneal. Depending on the film composition, a different crystalline phase is formed ranging from monoclinic to tetragonal with increasing Zr content. CMOS transistors, using HfZrOx as gate dielectric, are fabricated for the evaluation of the corresponding device performance. Device results show that all splits with HfZrOx as gate dielectric yield not only a similar EOTJg performance but also very low leakage, which demonstrate that ALD HfZrOx is a promising candidate for sub-1nm EOT scaling.

We report on the metal-organic chemical vapor deposition of Ti-doped NiO thin films on 300 mm wafers for the application in resistive switching memories. We have used molecular oxygen as the oxidizer and Ni(dmamb)2 and TDMAT as precursors for the supply of Ni and Ti respectively. A well-behaved process is proposed for which the Ti-concentration is tunable between 0% and ~15%. We will demonstrate the functionality of resistive switching devices consisting of the stack Ni/Ti-doped NiO/TiN, and we will discuss the potential benefits of the titanium doping.