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This work concerns high resolution topography characterization at die scale of 28nm FDSOI CMOS technology by interferometric microscopy. It shows that usual test boxes (T-boxes) in scribe line are not representative of the full die topography. Consequently, new parameters are needed in order to take full advantage of high resolution topography characterization at die scale. In that sense, it is observed in this study that coupling full die and die @s ranges can provide new and relevant information about the Chemical Mechanical Polishing (CMP) processes. Moreover, high resolution die topography data makes possible to characterize in-die impact of a structure on its neighborhood and evaluate the pattern density dependency of the CMP processes.

Direct wafer bonding and thinning technologies are now extensively used in combination to produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging demands of new functionalities at the material or device level for 3D integration have allowed increasing the level of maturity of these technologies. This paper will review the physics of wafer direct bonding and its implementation for vertical integration devices of processed strata with vertical interconnects.

3D technology will be the next step for the development of microelectronic devices. Vertical interconnection is one of the challenging issue. Metal bonding might be one of the possible technique to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure and ambient air is investigated. At room temperature, a 2.8 J/m2 bonding toughness is achieved. EELS spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions versus post bonding annealing are presented with TEM and XRD analyses. The ohmic behavior of the bonding is highlighted.

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

The formation of air gaps by means of a non-conformal chemical vapor deposition (CVD) on patterned wafers was successfully demonstrated using SiOC (K=2.9) as inter-level metal dielectric. This paper presents the results on physical characterization and electrical performance evaluation of integrated SiOC air gaps in a three-metal level Cu/SiOC interconnect module. The influence of the air gaps shape on parasitic coupling capacitance between copper lines was also discussed in accordance with mask design rules and processing steps.

This paper proposes the integration of MOS Capacitor Deep Trench Isolation (CDTI) as a solution to boost image sensors' pixels performances. We have investigated CDTI and compared it to oxide-filled Deep Trench Isolation (DTI) configurations, on silicon samples, with a fabrication based on TCAD simulations. The experiment measurements evaluated on CDTI without Sidewall Implantation (SWI) exhibit very low dark current (∼1aA at 60°C for a 1.4µm pixel), high full-well capacity (∼12000e-), and it shows quantum efficiency improvement compared to DTI configuration. Pixels with optimized CDTI gate oxide thickness have demonstrated comparable angular response to oxide-filled DTI counterparts.

This paper presents the development of CMP process optimization in order to obtain very good bondability of tungsten wafers. Surface quality of polished tungsten wafers under different conditions is analyzed through statistical tools like standard deviation, skewness and kurtosis. Good surface quality for planarized wafers is obtained by polishing under optimized conditions process, allowing highly improved bonding quality, as shown by Scanning Acoustic Microscopy.

Beyond C14nm, better W CMP performances are required due to new CMOS integration constraints such as contact density increase, wide W feature introduction or low oxide loss for any polishing steps related to gate building. In order to address these new requirements, this paper propose an approach similar to Cu damascene CMP, using three consecutive polishing steps respectively for planarization, selective stop on Ti/TiN barrier and barrier removal. This study discuss advantages and limitations of this approach and points out process improvement obtained among which lower oxide erosion, tunable W recess, better oxide WIWNU and minimized oxide loss.

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28nm and 22nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to 10nm node. Innovations will be necessary for lowest node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication (Fig. 1). High mobility materials are expected to replace silicon as the channel material: attention has been focused recently on the III-V and the Ge materials (Fig.1). Indeed, III-V semiconductors (such as GaAs, InP, InGaAs and InAs) have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass [3]. In order to avoid short channel effects, these “new” materials have to be transferred as thin layers on buried oxide layers. SOI substrates are fabricated using the Smart CutTM technology. This process, based on hydrogen implantation and wafer bonding, made it possible to transfer a thin layer of crystalline material from a donor substrate to another substrate. This versatile technique for thin layer transfer enables the fabrication of hetero-substrates with a large choice for the crystalline superficial layers, the buried layers and even the handle substrates (Fig. 2). For More Moore applications, this leaves the freedom to transfer Ge or III-V thin layer on an optimized buried oxide layer. In this paper, we will present our latest work on advanced SOI substrates for sub-28nm technology node and on novel “on insulator” substrates for sub-10nm node. We developed GeOI (Fig. 3) and InGaAs-OI (Fig. 4) substrates in 300mm. It is otherwise possible, thanks to low temperature direct bonding, to combine 3D CMOS integration (thereby increasing transistor density) and high mobility channel devices : a monolithic and vertical co-integration of GeOI pMOSFETs stacked on SOI nMOSFETs [4] or a III-V-OI nMOSFETs stacked on a SiGeOI pMOSFETs [5] have already been demonstrated with functional inverters and SRAM cells. Acknowledgments: the authors acknowledge financial support from the European Commission via the FP7-COMPOSE3 and from the French Government's Investissement d'Avenir program (eXact projet). [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] S. Takagi, IEEE TED, 2008 [4] P. Batude, VLSI 2009 [5] T. Irisawa, VLSI, 2013.

A new plasma etch-back planarization technique is presented with countermasking to preplanarize shallow trench isolation (STI) substrates before chemical mechanical polishing (CMP). A preplanarization step is necessary since CMP alone cannot provide effective planarization for sub 0.18 technology due to the dishing effect. The preplanarization step uses the principle of two layer planarization technique which consists of spin coating a first photoresist layer, using a countermask for the lithographic step, flowing and curing the resist blocks in STI topographies, spin coating a second photoresist layer to planarize the residual topography, and transferring the final flat surface into the substrate using conventional plasma etch back. In difference with previous techniques, we used a special mask with oversizing and exclusion of all STI critical dimensions smaller than 1.55 μm, the zones with the smaller STI dimensions being masked using a special narrow lines grid. Such a masking strategy avoids any misalignment problem, where the resized first photoresist blocks are reflowed in STI topographies, leading to an easy planarization by the second resist layer. Additionally, the lithographic step is a noncritical step using conventional i-line resist. Using appropriate planarization model and simulation, the first layer thickness can be adjusted to get an effectively planarized topography. The final surface is then transferred into the oxide substrate using the plasma etch-back technique. Various gas mixtures were tested using LAM 4520 plasma etching equipment. The (Ar/CF4/O2) gas mixture was observed to fulfill etch-back requirements with better performance. Equality of etch rate in resist and in oxide can be adjusted by the O2/CF4 gas ratio. A design of experiment was used to determine the optimum conditions of plasma transfer of the planarized profile into the substrate. Finally, the preplanarized wafer is polished by CMP, resulting in an effectively planarized topography with residual topography smaller than 50 nm. The technique is a noncritical lithographic technique scaleable for technologies below 0.18 μm.

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

We demonstrate the feasibility of producing advanced silicon photonic devices for future data communication nodes at 40Gbps using CMOS compatible processes in a 300mm wafer fab. Basic building blocks are shown together with various wavelength division multiplexing solutions. All the devices presented are integrated on 220nm SOI or locally grown epitaxial germanium.

We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. We report excellent ION, p=1020μA/μm at IOFF, p=100nA/μm at VDD=0.9V supply voltage for pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).

Graphical abstractDisplay Omitted We integrated a gate-last on high-k first on planar fully depleted SOI MOSFETs.pMOSFETs reach a low threshold voltage of VTp=-0.2V.Gate-last pMOSFETS present one decade gate current gain compared to gate first ones.The use of a TiN MOCVD capping decreases the EWF by 0.2eV and degrades the reliability compared to TiN ALD.EOT down to 0.8nm with midgap TaN are obtained on HfO2 in a high-k last integration. We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg=15nm and active widths of W=80nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of VTp=-0.2V and one decade gate current (JG) gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (VFB) shift under stress.

Localized metal bonding is one of the main drivers for 3D technology implementation as it allows high vertical interconnection densities between piled up dies. In this paper we will present the direct bonding of tungsten blanket. The copper and tungsten direct bonding will be compared in terms of bonding mechanism and temperature dependence.

We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22nm nodes. We demonstrate pFET devices with promising electrical behavior (ION=790µA/µm; I OFF =60nA/µm @ V DS =-1.2V; L g =30nm), suitable for high performance applications. Excellent SCE control is also reported down to 30nm (DIBL=50mV/V), through the use of Double Gate transistors.

This paper presents the implementation of a key technology developed for high density 3-D integration by circuit stacking. Direct copper bonding at room temperature, atmospheric pressure and ambient air of copper pads allowed the elaboration of a 10×10 9m vertical interconnect with a contact resistance of 10 mohms. First tests on tungsten bonding will be also reviewed.

We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345µA/µm and Ioff=30nA/µm at −1V for a 50nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow specifific contact resistivities as low as 0.1 Ω.µm2.

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.

In 3D integration circuits, metal bonding is a key stage for stacking wafers. In this contribution, the direct Cu/Cu bonding at atmospheric pressure is investigated. At room temperature, a 2.8 J/m2 bonding toughness is achieved without copper oxide at the interface. The vertical current of this bonding and the possibility to grind the top silicon down to 10 ?m have been demonstrated.

Air gaps were successfully integrated in a multi level metallization interconnect stack using 65 nm design rules on 300 mm wafers. The proposed approach allows a low cost integration of localized air cavities using a sacrificial material to solve via misalignment issues. Air gap integration is shown to be mechanically robust and presents excellent electrical results with high gains on RC delays. In addition, air gaps structures tested in electromigration pass the targeted lifetime criterion. This easily scalable approach can be seriously considered either in aggressive interconnect geometries or in specific applications of existing technologies for which high electrical performance is locally required.

In this work, we demonstrate the capability of Ecmp to meet the 45 nm and 32 nm technology node requirements in terms of topography behavior, the related electrical spread, lithography DOF budget and ULK compatibility.

Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed

An advanced CMOS process has been proposed which include key features : 75 nm gate length, damascene metal gate, high-k dielectrics with 1.35 nm equivalent oxide thickness (EOT). Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface Low gate current and low subthreshold slope make it attractive for low stand by power application.

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

This work was focused on the integration of Cu/SiOC dual damascene interconnect modules for 0.1 /spl mu/m node technology. A complete study was performed on the impact of the dielectric barrier material on the integration approach. It was shown that a nitrogen free SiC barrier layer was necessary to integrate SiOC in the currently used via first dual damascene architecture. The performance of this new material was evaluated in terms of etching selectivity, resist poisoning and ARC lithography behaviour, electrical and reliability results. On all these aspects, SiC was found better than SiCN.

In this paper we present for the first time mid-gap CoSi/sub 2/ metal gates obtained by total gate silicidation meaning that the silicidation process decay itself once the reaction front arrives down to the gate oxide and no more polysilicon is left. Metal gate are required for FDSOI but they may also be useful for low gate-resistance bulk RF devices. For simplicity, we have investigated totally silicided gates within a 0.1 /spl mu/m CMOS bulk technology. In the next step, CoSi/sub 2/ metal gates were processed after the poly CMP step (first CMP in damascene process) in order to protect source and drain from deep silicidation. Low gate resistivity transistors were obtained, exhibiting good performances without degradation in gate leakage, subthreshold slope nor in drive and off currents compared with reference poly-silicon gate transistors.

Monolithic 3D Integration (3DMI) consists in processing transistors on top of each other sequentially. This technology appears to be an alternative solution to scaling, from the 7nm node integration and below, as substantial gain in area and performance as compared to planar technology is expected without scaling the transistor technology node. 3DMI appears to be the most optimized way to take advantage of the vertical dimension as almost no alignment constraints remains. By using a standard lithography, the top transistors can be aligned directly onto their bottom counterparts with a high accuracy (see Fig. 1), contrary to TSV-based 3D technologies [2]. Furthermore, 3DMI is a highly versatile technology as the different transistor levels can be optimized independently, from the choice of the channel characteristics (e.g. material, orientation, strain) to the architecture itself (e.g. CMOS on CMOS, PMOS on NMOS, FinFET on BULK, LVT on RVT) [3]. Such sequential integration raises two main technological challenges: - Creating an active layer above a bottom transistor which will become the channel of the top transistor. In order to achieve similar performance for top FET than bottom FET, the substrate quality must be equivalent than commercial substrates. Thus, this layer must be monocristalline and defect free in order to optimize the mobility and to be consistent with high performance criteria. A precise thickness control is also necessary in order to avoid device performance dispersion. - Realizing a high performance top transistor level without degrading the bottom level as the stacked transistor levels are processed sequentially, i.e. at low temperature process –typically below 600°C. Recent results demonstrate some integration solutions, such as junction activation by Solid Phase Epitaxy Regrowth below 600°C [4]. To tackle the first challenge, we transfer a thin silicon layer from a high quality Silicon On Insulator (SOI) wafer by direct bonding. It appears to be the most effective solution to obtain a defect free monocristalline active layer with a well-controlled thickness. This method is preferred to different techniques which have been developed to create large monocristal grains of silicon either by laser anneal of amorphous Poly-Silicon [5] or by µ-Czochralsky process [6]. However, in both cases, large “seed layers” are necessary to control the orientation and the size of these grains, which is not consistent with for high density circuits. For this layer transfer, a blanket SOI wafer on which a Si02 layer is either grown or deposited, is bonded on the classical pre-metal dielectric above the bottom transistor level. The SOI backside is then removed by grinding and chemical etching to keep only the silicon layer. While expert knowledge has been reached for full sheet wafer bonding, the situation on a patterned layer can be really challenging with the design rules of 3DMI. In order to face these challenges, the surface preparation, the direct bonding process and the thinning steps have been optimized to prevent any defect on the whole 300mm surface. Also TMAH bevel edge protection and silicide protection layer have been added. This work will give a general overview of 3D monolithic challenges. Also, a specific focus will be made on direct bonding which is a major enabler of this type of integration. Indeed among the other alternative techniques, it appears to be the best solution to meet the high performance and high density criteria. REFERENCES: [1] P. Batude et al., VLSI Technology, pp. 158 (2011) [1] P. Batude et al., ECS Spring meeting, (16) pp. 47 (2008) [2] P. Batude et al., IITC-AMC (2014) [3] P. Batude et al., IEDM, pp.731-734 (2011) [4] C-H. Shen et al., IEDM, pp. 931-934 (2013) [5] J. Derakhshandeh et al., TED vol.58, no. 11 (2011) Fig.1: 3DMI demonstration with ultra-high alignment between the stacked transistors [1] obtained with 248nm stepper.

This paper presents a new counter-masking technique to pre- planarize Shallow Trench Isolation before Chemical Mechanical Polishing (CMP). A pre-planarization step is necessary since CMP alone cannot provide effective planarization for sub 0.18 technology due to dishing effect. The pre-planarization step uses the principle of Two Layer Planarization technique which consists in spin-coating a first photoresist layer, using a counter-mask for the lithographic step, flowing and curing the resist blocks in STI topographies, spin-coating a second photoresist layer to planarize the residual topography and transferring the final flat surface into the substrate using conventional plasma etch-back. In difference with previous techniques, we used a special mask with oversizing and exclusion of all STI critical dimensions smaller than 1.55 micrometers , the zones with the smaller STI dimensions being masked using a special narrow lines grid. Such a masking strategy avoids any misalignment problem, the resized first photoresist blocks are reflowed in STI topographies, leading to an easy planarization by the second resist layer. Additionally, the lithographic step is a non-critical step using conventional i-line resist. Using appropriate planarization modelization and simulation, the first layer thickness can be adjusted to get an effectively planarized topography. The final surface is then transferred into the oxide substrate using a gas mixture in a LAM 4520 plasma etching equipment. Finally, the pre-planarized wafer is polished by CMP, resulting in an effectively planarized topography with residual topography smaller than 50 nm. The technique is a non-critical lithographic technique scaleable for technologies below 0.18 micrometers .

Three-dimensional (3D) technology is the next step in the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Metal bonding might be one of the possible techniques to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure, and ambient air was investigated. At room temperature, a 2.8 J/m 2 bonding toughness was achieved. An electron energy loss spectroscopy spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions vs postbonding annealing were presented with transmission electron microscopy and X-ray diffraction analyses. The ohmic behavior of the bonding was highlighted.

not Available.

Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.